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Eric Benard3cbeb0f2014-04-04 19:05:55 +02001/*
2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com>
4 *
5 * Configuration settings for the Embest RIoTboard
6 *
7 * based on mx6*sabre*.h which are :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __RIOTBOARD_CONFIG_H
14#define __RIOTBOARD_CONFIG_H
15
Eric Benard3cbeb0f2014-04-04 19:05:55 +020016#define CONFIG_MXC_UART_BASE UART2_BASE
Simon Glass12ca05a2016-10-17 20:12:39 -060017#define CONSOLE_DEV "ttymxc1"
Eric Benard3cbeb0f2014-04-04 19:05:55 +020018
19#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
20
Adrian Alonso1368f992015-09-02 13:54:13 -050021#define CONFIG_IMX_THERMAL
Eric Benard3cbeb0f2014-04-04 19:05:55 +020022
23/* Size of malloc() pool */
24#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
25
Eric Benard3cbeb0f2014-04-04 19:05:55 +020026#define CONFIG_MXC_UART
27
Eric Benard3cbeb0f2014-04-04 19:05:55 +020028/* I2C Configs */
Eric Benard3cbeb0f2014-04-04 19:05:55 +020029#define CONFIG_SYS_I2C
30#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +020031#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
32#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -070033#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Eric Benard3cbeb0f2014-04-04 19:05:55 +020034#define CONFIG_SYS_I2C_SPEED 100000
35
36/* USB Configs */
Eric Benard3cbeb0f2014-04-04 19:05:55 +020037#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
38#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
39#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
40#define CONFIG_MXC_USB_FLAGS 0
41
42/* MMC Configs */
Eric Benard3cbeb0f2014-04-04 19:05:55 +020043#define CONFIG_SYS_FSL_ESDHC_ADDR 0
44
Eric Benard3cbeb0f2014-04-04 19:05:55 +020045#define CONFIG_FEC_MXC
46#define CONFIG_MII
47#define IMX_FEC_BASE ENET_BASE_ADDR
48#define CONFIG_FEC_XCV_TYPE RGMII
49#define CONFIG_ETHPRIME "FEC"
50#define CONFIG_FEC_MXC_PHYADDR 4
51
Eric Benard3cbeb0f2014-04-04 19:05:55 +020052#define CONFIG_PHY_ATHEROS
53
Eric Benard3cbeb0f2014-04-04 19:05:55 +020054#ifdef CONFIG_CMD_SF
Eric Benard3cbeb0f2014-04-04 19:05:55 +020055#define CONFIG_MXC_SPI
56#define CONFIG_SF_DEFAULT_BUS 0
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +030057#define CONFIG_SF_DEFAULT_CS 0
Eric Benard3cbeb0f2014-04-04 19:05:55 +020058#define CONFIG_SF_DEFAULT_SPEED 20000000
59#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
60#endif
61
Eric Benard3cbeb0f2014-04-04 19:05:55 +020062#define CONFIG_ARP_TIMEOUT 200UL
63
Eric Benard3cbeb0f2014-04-04 19:05:55 +020064#define CONFIG_SYS_MEMTEST_START 0x10000000
65#define CONFIG_SYS_MEMTEST_END 0x10010000
66#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
67
Eric Benard3cbeb0f2014-04-04 19:05:55 +020068/* Physical Memory Map */
69#define CONFIG_NR_DRAM_BANKS 1
70#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
71
72#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
73#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
74#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
75
76#define CONFIG_SYS_INIT_SP_OFFSET \
77 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
78#define CONFIG_SYS_INIT_SP_ADDR \
79 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
80
Peter Robinson056845c2015-05-22 17:30:45 +010081/* Environment organization */
Eric Benard3cbeb0f2014-04-04 19:05:55 +020082#define CONFIG_ENV_SIZE (8 * 1024)
83
84#if defined(CONFIG_ENV_IS_IN_MMC)
85/* RiOTboard */
Iain Patonc86efd82014-12-14 14:51:46 +000086#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
Eric Benard3cbeb0f2014-04-04 19:05:55 +020087#define CONFIG_SYS_FSL_USDHC_NUM 3
88#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
89#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
90#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
91#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
92/* MarSBoard */
Iain Patonc86efd82014-12-14 14:51:46 +000093#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
Eric Benard3cbeb0f2014-04-04 19:05:55 +020094#define CONFIG_SYS_FSL_USDHC_NUM 2
95#define CONFIG_ENV_OFFSET (768 * 1024)
96#define CONFIG_ENV_SECT_SIZE (8 * 1024)
97#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
98#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
99#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
100#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
101#endif
102
Eric Benard3cbeb0f2014-04-04 19:05:55 +0200103/* Framebuffer */
Eric Benard3cbeb0f2014-04-04 19:05:55 +0200104#define CONFIG_VIDEO_IPUV3
Eric Benard3cbeb0f2014-04-04 19:05:55 +0200105#define CONFIG_VIDEO_BMP_RLE8
106#define CONFIG_SPLASH_SCREEN
107#define CONFIG_SPLASH_SCREEN_ALIGN
108#define CONFIG_BMP_16BPP
109#define CONFIG_VIDEO_LOGO
110#define CONFIG_VIDEO_BMP_LOGO
Eric Benard3cbeb0f2014-04-04 19:05:55 +0200111#define CONFIG_IMX_HDMI
112#define CONFIG_IMX_VIDEO_SKIP
113
Iain Paton729d2a32014-12-14 14:51:32 +0000114#include <config_distro_defaults.h>
Peter Robinsone51c1e82015-05-22 17:30:52 +0100115#include "mx6_common.h"
Iain Paton729d2a32014-12-14 14:51:32 +0000116
Iain Patonc86efd82014-12-14 14:51:46 +0000117/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
118 * 1M script, 1M pxe and the ramdisk at the end */
119#define MEM_LAYOUT_ENV_SETTINGS \
120 "bootm_size=0x10000000\0" \
121 "kernel_addr_r=0x12000000\0" \
122 "fdt_addr_r=0x13000000\0" \
123 "scriptaddr=0x13100000\0" \
124 "pxefile_addr_r=0x13200000\0" \
125 "ramdisk_addr_r=0x13300000\0"
126
127#define BOOT_TARGET_DEVICES(func) \
128 func(MMC, mmc, 0) \
129 func(MMC, mmc, 1) \
130 func(MMC, mmc, 2) \
131 func(USB, usb, 0) \
132 func(PXE, pxe, na) \
133 func(DHCP, dhcp, na)
134
135#include <config_distro_bootcmd.h>
136
137#define CONSOLE_STDIN_SETTINGS \
138 "stdin=serial\0"
139
140#define CONSOLE_STDOUT_SETTINGS \
141 "stdout=serial\0" \
142 "stderr=serial\0"
143
144#define CONSOLE_ENV_SETTINGS \
145 CONSOLE_STDIN_SETTINGS \
146 CONSOLE_STDOUT_SETTINGS
147
148#define CONFIG_EXTRA_ENV_SETTINGS \
149 CONSOLE_ENV_SETTINGS \
150 MEM_LAYOUT_ENV_SETTINGS \
151 "fdtfile=" CONFIG_FDTFILE "\0" \
Fabio Berton0f29a612017-07-10 17:04:11 -0300152 "finduuid=part uuid mmc 0:1 uuid\0" \
Iain Patonc86efd82014-12-14 14:51:46 +0000153 BOOTENV
154
Eric Benard3cbeb0f2014-04-04 19:05:55 +0200155#endif /* __RIOTBOARD_CONFIG_H */