Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 2 | /* |
| 3 | * PCI autoconfiguration library |
| 4 | * |
| 5 | * Author: Matt Porter <mporter@mvista.com> |
| 6 | * |
| 7 | * Copyright 2000 MontaVista Software Inc. |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Simon Glass | 4439bc3 | 2016-01-18 20:19:16 -0700 | [diff] [blame] | 11 | #include <dm.h> |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 12 | #include <errno.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 14 | #include <pci.h> |
Vladimir Oltean | 7f76084 | 2021-09-17 15:11:21 +0300 | [diff] [blame] | 15 | #include "pci_internal.h" |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 16 | |
| 17 | /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ |
| 18 | #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE |
| 19 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 |
| 20 | #endif |
| 21 | |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 22 | static void dm_pciauto_setup_device(struct udevice *dev, |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 23 | struct pci_region *mem, |
| 24 | struct pci_region *prefetch, |
| 25 | struct pci_region *io) |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 26 | { |
| 27 | u32 bar_response; |
| 28 | pci_size_t bar_size; |
| 29 | u16 cmdstat = 0; |
| 30 | int bar, bar_nr = 0; |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 31 | int bars_num; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 32 | u8 header_type; |
| 33 | int rom_addr; |
| 34 | pci_addr_t bar_value; |
Bin Meng | 6796704 | 2016-02-17 23:14:47 -0800 | [diff] [blame] | 35 | struct pci_region *bar_res = NULL; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 36 | int found_mem64 = 0; |
| 37 | u16 class; |
| 38 | |
| 39 | dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); |
| 40 | cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
| 41 | PCI_COMMAND_MASTER; |
| 42 | |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 43 | dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); |
| 44 | header_type &= 0x7f; |
| 45 | |
| 46 | switch (header_type) { |
| 47 | case PCI_HEADER_TYPE_NORMAL: |
| 48 | bars_num = 6; |
| 49 | break; |
| 50 | case PCI_HEADER_TYPE_BRIDGE: |
| 51 | bars_num = 2; |
| 52 | break; |
| 53 | case PCI_HEADER_TYPE_CARDBUS: |
| 54 | /* CardBus header does not have any BAR */ |
| 55 | bars_num = 0; |
| 56 | break; |
| 57 | default: |
| 58 | /* Skip configuring BARs for unknown header types */ |
| 59 | bars_num = 0; |
| 60 | break; |
| 61 | } |
| 62 | |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 63 | for (bar = PCI_BASE_ADDRESS_0; |
| 64 | bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { |
Simon Glass | 6a73cf3 | 2019-09-25 08:56:16 -0600 | [diff] [blame] | 65 | int ret = 0; |
| 66 | |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 67 | /* Tickle the BAR and get the response */ |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 68 | dm_pci_write_config32(dev, bar, 0xffffffff); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 69 | dm_pci_read_config32(dev, bar, &bar_response); |
| 70 | |
Phil Sutter | c1b1263 | 2021-01-03 23:06:45 +0100 | [diff] [blame] | 71 | /* If BAR is not implemented (or invalid) go to the next BAR */ |
| 72 | if (!bar_response || bar_response == 0xffffffff) |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 73 | continue; |
| 74 | |
| 75 | found_mem64 = 0; |
| 76 | |
| 77 | /* Check the BAR type and set our address mask */ |
| 78 | if (bar_response & PCI_BASE_ADDRESS_SPACE) { |
Phil Sutter | c1b1263 | 2021-01-03 23:06:45 +0100 | [diff] [blame] | 79 | bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK; |
| 80 | bar_size &= ~(bar_size - 1); |
| 81 | |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 82 | bar_res = io; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 83 | |
| 84 | debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", |
| 85 | bar_nr, (unsigned long long)bar_size); |
| 86 | } else { |
| 87 | if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == |
| 88 | PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 89 | u32 bar_response_upper; |
| 90 | u64 bar64; |
| 91 | |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 92 | dm_pci_write_config32(dev, bar + 4, 0xffffffff); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 93 | dm_pci_read_config32(dev, bar + 4, |
| 94 | &bar_response_upper); |
| 95 | |
| 96 | bar64 = ((u64)bar_response_upper << 32) | |
| 97 | bar_response; |
| 98 | |
| 99 | bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) |
| 100 | + 1; |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 101 | found_mem64 = 1; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 102 | } else { |
| 103 | bar_size = (u32)(~(bar_response & |
| 104 | PCI_BASE_ADDRESS_MEM_MASK) + 1); |
| 105 | } |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 106 | |
| 107 | if (prefetch && |
| 108 | (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) |
| 109 | bar_res = prefetch; |
| 110 | else |
| 111 | bar_res = mem; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 112 | |
Phil Sutter | a62de44 | 2021-03-03 01:57:35 +0100 | [diff] [blame] | 113 | debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ", |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 114 | bar_nr, bar_res == prefetch ? "Prf" : "Mem", |
Phil Sutter | a62de44 | 2021-03-03 01:57:35 +0100 | [diff] [blame] | 115 | found_mem64 ? "64" : "", |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 116 | (unsigned long long)bar_size); |
| 117 | } |
| 118 | |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 119 | ret = pciauto_region_allocate(bar_res, bar_size, |
| 120 | &bar_value, found_mem64); |
| 121 | if (ret) |
| 122 | printf("PCI: Failed autoconfig bar %x\n", bar); |
| 123 | |
| 124 | if (!ret) { |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 125 | /* Write it out and update our limit */ |
| 126 | dm_pci_write_config32(dev, bar, (u32)bar_value); |
| 127 | |
| 128 | if (found_mem64) { |
| 129 | bar += 4; |
| 130 | #ifdef CONFIG_SYS_PCI_64BIT |
| 131 | dm_pci_write_config32(dev, bar, |
| 132 | (u32)(bar_value >> 32)); |
| 133 | #else |
| 134 | /* |
| 135 | * If we are a 64-bit decoder then increment to |
| 136 | * the upper 32 bits of the bar and force it to |
| 137 | * locate in the lower 4GB of memory. |
| 138 | */ |
| 139 | dm_pci_write_config32(dev, bar, 0x00000000); |
| 140 | #endif |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? |
| 145 | PCI_COMMAND_IO : PCI_COMMAND_MEMORY; |
| 146 | |
| 147 | debug("\n"); |
| 148 | |
| 149 | bar_nr++; |
| 150 | } |
| 151 | |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 152 | /* Configure the expansion ROM address */ |
Pali Rohár | b9caab8 | 2021-10-07 14:50:57 +0200 | [diff] [blame] | 153 | if (header_type == PCI_HEADER_TYPE_NORMAL || |
| 154 | header_type == PCI_HEADER_TYPE_BRIDGE) { |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 155 | rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? |
| 156 | PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; |
| 157 | dm_pci_write_config32(dev, rom_addr, 0xfffffffe); |
| 158 | dm_pci_read_config32(dev, rom_addr, &bar_response); |
| 159 | if (bar_response) { |
| 160 | bar_size = -(bar_response & ~1); |
| 161 | debug("PCI Autoconfig: ROM, size=%#x, ", |
| 162 | (unsigned int)bar_size); |
| 163 | if (pciauto_region_allocate(mem, bar_size, &bar_value, |
| 164 | false) == 0) { |
| 165 | dm_pci_write_config32(dev, rom_addr, bar_value); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 166 | } |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 167 | cmdstat |= PCI_COMMAND_MEMORY; |
| 168 | debug("\n"); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 169 | } |
| 170 | } |
| 171 | |
| 172 | /* PCI_COMMAND_IO must be set for VGA device */ |
| 173 | dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); |
| 174 | if (class == PCI_CLASS_DISPLAY_VGA) |
| 175 | cmdstat |= PCI_COMMAND_IO; |
| 176 | |
| 177 | dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); |
| 178 | dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, |
| 179 | CONFIG_SYS_PCI_CACHE_LINE_SIZE); |
| 180 | dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); |
| 181 | } |
| 182 | |
| 183 | void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) |
| 184 | { |
| 185 | struct pci_region *pci_mem; |
| 186 | struct pci_region *pci_prefetch; |
| 187 | struct pci_region *pci_io; |
| 188 | u16 cmdstat, prefechable_64; |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 189 | u8 io_32; |
Simon Glass | 4439bc3 | 2016-01-18 20:19:16 -0700 | [diff] [blame] | 190 | struct udevice *ctlr = pci_get_controller(dev); |
| 191 | struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 192 | |
| 193 | pci_mem = ctlr_hose->pci_mem; |
| 194 | pci_prefetch = ctlr_hose->pci_prefetch; |
| 195 | pci_io = ctlr_hose->pci_io; |
| 196 | |
| 197 | dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); |
| 198 | dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); |
| 199 | prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; |
Pali Rohár | f209414 | 2021-11-25 11:30:58 +0100 | [diff] [blame] | 200 | dm_pci_read_config8(dev, PCI_IO_BASE, &io_32); |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 201 | io_32 &= PCI_IO_RANGE_TYPE_MASK; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 202 | |
| 203 | /* Configure bus number registers */ |
| 204 | dm_pci_write_config8(dev, PCI_PRIMARY_BUS, |
Simon Glass | 8b85dfc | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 205 | PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr)); |
| 206 | dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr)); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 207 | dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); |
| 208 | |
| 209 | if (pci_mem) { |
| 210 | /* Round memory allocator to 1MB boundary */ |
| 211 | pciauto_region_align(pci_mem, 0x100000); |
| 212 | |
| 213 | /* |
| 214 | * Set up memory and I/O filter limits, assume 32-bit |
| 215 | * I/O space |
| 216 | */ |
| 217 | dm_pci_write_config16(dev, PCI_MEMORY_BASE, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 218 | ((pci_mem->bus_lower & 0xfff00000) >> 16) & |
| 219 | PCI_MEMORY_RANGE_MASK); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 220 | |
| 221 | cmdstat |= PCI_COMMAND_MEMORY; |
| 222 | } |
| 223 | |
| 224 | if (pci_prefetch) { |
| 225 | /* Round memory allocator to 1MB boundary */ |
| 226 | pciauto_region_align(pci_prefetch, 0x100000); |
| 227 | |
| 228 | /* |
| 229 | * Set up memory and I/O filter limits, assume 32-bit |
| 230 | * I/O space |
| 231 | */ |
| 232 | dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 233 | (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & |
| 234 | PCI_PREF_RANGE_MASK) | prefechable_64); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 235 | if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) |
| 236 | #ifdef CONFIG_SYS_PCI_64BIT |
| 237 | dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, |
| 238 | pci_prefetch->bus_lower >> 32); |
| 239 | #else |
| 240 | dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); |
| 241 | #endif |
| 242 | |
| 243 | cmdstat |= PCI_COMMAND_MEMORY; |
| 244 | } else { |
| 245 | /* We don't support prefetchable memory for now, so disable */ |
Pali Rohár | 95ab578 | 2021-11-25 11:34:37 +0100 | [diff] [blame^] | 246 | dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 | |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 247 | prefechable_64); |
| 248 | dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | |
| 249 | prefechable_64); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 250 | if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { |
| 251 | dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); |
| 252 | dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | if (pci_io) { |
| 257 | /* Round I/O allocator to 4KB boundary */ |
| 258 | pciauto_region_align(pci_io, 0x1000); |
| 259 | |
| 260 | dm_pci_write_config8(dev, PCI_IO_BASE, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 261 | (((pci_io->bus_lower & 0x0000f000) >> 8) & |
| 262 | PCI_IO_RANGE_MASK) | io_32); |
| 263 | if (io_32 == PCI_IO_RANGE_TYPE_32) |
| 264 | dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 265 | (pci_io->bus_lower & 0xffff0000) >> 16); |
| 266 | |
| 267 | cmdstat |= PCI_COMMAND_IO; |
Pali Rohár | 06f25bd | 2021-11-25 11:32:43 +0100 | [diff] [blame] | 268 | } else { |
| 269 | /* Disable I/O if unsupported */ |
| 270 | dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32); |
| 271 | dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32); |
| 272 | if (io_32 == PCI_IO_RANGE_TYPE_32) { |
| 273 | dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0); |
| 274 | dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0); |
| 275 | } |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | /* Enable memory and I/O accesses, enable bus master */ |
| 279 | dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); |
| 280 | } |
| 281 | |
| 282 | void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) |
| 283 | { |
| 284 | struct pci_region *pci_mem; |
| 285 | struct pci_region *pci_prefetch; |
| 286 | struct pci_region *pci_io; |
Simon Glass | 4439bc3 | 2016-01-18 20:19:16 -0700 | [diff] [blame] | 287 | struct udevice *ctlr = pci_get_controller(dev); |
| 288 | struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 289 | |
| 290 | pci_mem = ctlr_hose->pci_mem; |
| 291 | pci_prefetch = ctlr_hose->pci_prefetch; |
| 292 | pci_io = ctlr_hose->pci_io; |
| 293 | |
| 294 | /* Configure bus number registers */ |
Simon Glass | 8b85dfc | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 295 | dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr)); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 296 | |
| 297 | if (pci_mem) { |
| 298 | /* Round memory allocator to 1MB boundary */ |
| 299 | pciauto_region_align(pci_mem, 0x100000); |
| 300 | |
| 301 | dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 302 | ((pci_mem->bus_lower - 1) >> 16) & |
| 303 | PCI_MEMORY_RANGE_MASK); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | if (pci_prefetch) { |
| 307 | u16 prefechable_64; |
| 308 | |
| 309 | dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, |
| 310 | &prefechable_64); |
| 311 | prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; |
| 312 | |
| 313 | /* Round memory allocator to 1MB boundary */ |
| 314 | pciauto_region_align(pci_prefetch, 0x100000); |
| 315 | |
| 316 | dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 317 | (((pci_prefetch->bus_lower - 1) >> 16) & |
| 318 | PCI_PREF_RANGE_MASK) | prefechable_64); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 319 | if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) |
| 320 | #ifdef CONFIG_SYS_PCI_64BIT |
| 321 | dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, |
| 322 | (pci_prefetch->bus_lower - 1) >> 32); |
| 323 | #else |
| 324 | dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); |
| 325 | #endif |
| 326 | } |
| 327 | |
| 328 | if (pci_io) { |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 329 | u8 io_32; |
| 330 | |
| 331 | dm_pci_read_config8(dev, PCI_IO_LIMIT, |
| 332 | &io_32); |
| 333 | io_32 &= PCI_IO_RANGE_TYPE_MASK; |
| 334 | |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 335 | /* Round I/O allocator to 4KB boundary */ |
| 336 | pciauto_region_align(pci_io, 0x1000); |
| 337 | |
| 338 | dm_pci_write_config8(dev, PCI_IO_LIMIT, |
Pali Rohár | 8e85f36 | 2021-09-10 13:33:35 +0200 | [diff] [blame] | 339 | ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & |
| 340 | PCI_IO_RANGE_MASK) | io_32); |
| 341 | if (io_32 == PCI_IO_RANGE_TYPE_32) |
| 342 | dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 343 | ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * HJF: Changed this to return int. I think this is required |
| 349 | * to get the correct result when scanning bridges |
| 350 | */ |
| 351 | int dm_pciauto_config_device(struct udevice *dev) |
| 352 | { |
| 353 | struct pci_region *pci_mem; |
| 354 | struct pci_region *pci_prefetch; |
| 355 | struct pci_region *pci_io; |
| 356 | unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); |
| 357 | unsigned short class; |
Simon Glass | 4439bc3 | 2016-01-18 20:19:16 -0700 | [diff] [blame] | 358 | struct udevice *ctlr = pci_get_controller(dev); |
| 359 | struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); |
Simon Glass | 42f3663 | 2020-12-16 21:20:18 -0700 | [diff] [blame] | 360 | int ret; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 361 | |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 362 | pci_mem = ctlr_hose->pci_mem; |
| 363 | pci_prefetch = ctlr_hose->pci_prefetch; |
| 364 | pci_io = ctlr_hose->pci_io; |
| 365 | |
| 366 | dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); |
| 367 | |
| 368 | switch (class) { |
| 369 | case PCI_CLASS_BRIDGE_PCI: |
| 370 | debug("PCI Autoconfig: Found P2P bridge, device %d\n", |
| 371 | PCI_DEV(dm_pci_get_bdf(dev))); |
| 372 | |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 373 | dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 374 | |
Simon Glass | 42f3663 | 2020-12-16 21:20:18 -0700 | [diff] [blame] | 375 | ret = dm_pci_hose_probe_bus(dev); |
| 376 | if (ret < 0) |
| 377 | return log_msg_ret("probe", ret); |
| 378 | sub_bus = ret; |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 379 | break; |
| 380 | |
| 381 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 382 | /* |
| 383 | * just do a minimal setup of the bridge, |
| 384 | * let the OS take care of the rest |
| 385 | */ |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 386 | dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 387 | |
| 388 | debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", |
| 389 | PCI_DEV(dm_pci_get_bdf(dev))); |
| 390 | |
| 391 | break; |
| 392 | |
| 393 | #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) |
| 394 | case PCI_CLASS_BRIDGE_OTHER: |
| 395 | debug("PCI Autoconfig: Skipping bridge device %d\n", |
| 396 | PCI_DEV(dm_pci_get_bdf(dev))); |
| 397 | break; |
| 398 | #endif |
Tom Rini | 6843862 | 2021-05-14 21:34:17 -0400 | [diff] [blame] | 399 | #if defined(CONFIG_ARCH_MPC834X) |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 400 | case PCI_CLASS_BRIDGE_OTHER: |
| 401 | /* |
| 402 | * The host/PCI bridge 1 seems broken in 8349 - it presents |
| 403 | * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ |
| 404 | * device claiming resources io/mem/irq.. we only allow for |
| 405 | * the PIMMR window to be allocated (BAR0 - 1MB size) |
| 406 | */ |
| 407 | debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); |
| 408 | dm_pciauto_setup_device(dev, 0, hose->pci_mem, |
Stefan Roese | a7a029d | 2021-01-12 12:03:43 +0100 | [diff] [blame] | 409 | hose->pci_prefetch, hose->pci_io); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 410 | break; |
| 411 | #endif |
| 412 | |
| 413 | case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ |
| 414 | debug("PCI AutoConfig: Found PowerPC device\n"); |
Simon Glass | f19345b | 2016-01-15 05:23:21 -0700 | [diff] [blame] | 415 | /* fall through */ |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 416 | |
| 417 | default: |
Pali Rohár | c7cd6f7 | 2021-10-07 14:50:59 +0200 | [diff] [blame] | 418 | dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 419 | break; |
| 420 | } |
| 421 | |
| 422 | return sub_bus; |
| 423 | } |