blob: 2f21fbb4e383802092a036fc2c0ee5d3174fa208 [file] [log] [blame]
Niklaus Giger69b06342008-01-17 12:53:56 +01001/*
2 *(C) Copyright 2005-2008 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20
21#include <common.h>
22#include <ppc4xx.h>
23#include <asm/processor.h>
24#include "nm.h"
25
26#if defined(DEBUG)
27void show_sdram_registers(void)
28{
29 u32 value;
30
31 printf("SDRAM Controller Registers --\n");
Stefan Roese95b602b2009-09-24 13:59:57 +020032 mfsdram(SDRAM0_CFG, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010033 printf(" SDRAM0_CFG : 0x%08x\n", value);
Stefan Roese95b602b2009-09-24 13:59:57 +020034 mfsdram(SDRAM0_STATUS, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010035 printf(" SDRAM0_STATUS: 0x%08x\n", value);
Stefan Roese95b602b2009-09-24 13:59:57 +020036 mfsdram(SDRAM0_B0CR, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010037 printf(" SDRAM0_B0CR : 0x%08x\n", value);
Stefan Roese95b602b2009-09-24 13:59:57 +020038 mfsdram(SDRAM0_B1CR, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010039 printf(" SDRAM0_B1CR : 0x%08x\n", value);
Stefan Roese95b602b2009-09-24 13:59:57 +020040 mfsdram(SDRAM0_TR, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010041 printf(" SDRAM0_TR : 0x%08x\n", value);
Stefan Roese95b602b2009-09-24 13:59:57 +020042 mfsdram(SDRAM0_RTR, value);
Niklaus Giger69b06342008-01-17 12:53:56 +010043 printf(" SDRAM0_RTR : 0x%08x\n", value);
44}
45#endif
46
Niklaus Giger74973122008-02-05 11:31:28 +010047long int init_ppc405_sdram(unsigned int dram_size)
Niklaus Giger69b06342008-01-17 12:53:56 +010048{
49#ifdef DEBUG
50 printf(__FUNCTION__);
51#endif
52 /* disable memory controller */
Stefan Roese95b602b2009-09-24 13:59:57 +020053 mtsdram(SDRAM0_CFG, 0x00000000);
Niklaus Giger69b06342008-01-17 12:53:56 +010054
55 udelay (500);
56
57 /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
Stefan Roese95b602b2009-09-24 13:59:57 +020058 mtsdram(SDRAM0_BESR0, 0xffffffff);
Niklaus Giger69b06342008-01-17 12:53:56 +010059
60 /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
Stefan Roese95b602b2009-09-24 13:59:57 +020061 mtsdram(SDRAM0_BESR1, 0xffffffff);
Niklaus Giger69b06342008-01-17 12:53:56 +010062
63 /* Clear SDRAM0_ECCCFG (disable ECC) */
Stefan Roese95b602b2009-09-24 13:59:57 +020064 mtsdram(SDRAM0_ECCCFG, 0x00000000);
Niklaus Giger69b06342008-01-17 12:53:56 +010065
66 /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
Stefan Roese95b602b2009-09-24 13:59:57 +020067 mtsdram(SDRAM0_ECCESR, 0xffffffff);
Niklaus Giger69b06342008-01-17 12:53:56 +010068
69 /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
70 */
Stefan Roese95b602b2009-09-24 13:59:57 +020071 mtsdram(SDRAM0_TR, 0x008a4015);
Niklaus Giger69b06342008-01-17 12:53:56 +010072
73 /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
74 * and refresh timer
75 */
76 switch (dram_size >> 20) {
77 case 32:
Stefan Roese95b602b2009-09-24 13:59:57 +020078 mtsdram(SDRAM0_B0CR, 0x00062001);
79 mtsdram(SDRAM0_RTR, 0x07F00000);
Niklaus Giger69b06342008-01-17 12:53:56 +010080 break;
81 case 64:
Stefan Roese95b602b2009-09-24 13:59:57 +020082 mtsdram(SDRAM0_B0CR, 0x00084001);
83 mtsdram(SDRAM0_RTR, 0x04100000);
Niklaus Giger69b06342008-01-17 12:53:56 +010084 break;
85 case 128:
Stefan Roese95b602b2009-09-24 13:59:57 +020086 mtsdram(SDRAM0_B0CR, 0x000A4001);
87 mtsdram(SDRAM0_RTR, 0x04100000);
Niklaus Giger69b06342008-01-17 12:53:56 +010088 break;
89 default:
90 printf("Invalid memory size of %d MB given\n", dram_size >> 20);
91 }
92
93 /* Power management idle timer set to the default. */
Stefan Roese95b602b2009-09-24 13:59:57 +020094 mtsdram(SDRAM0_PMIT, 0x07c00000);
Niklaus Giger69b06342008-01-17 12:53:56 +010095
96 udelay (500);
97
98 /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
Stefan Roese95b602b2009-09-24 13:59:57 +020099 mtsdram(SDRAM0_CFG, 0x90800000);
Niklaus Giger69b06342008-01-17 12:53:56 +0100100
101#ifdef DEBUG
102 printf("%s: done\n", __FUNCTION__);
103#endif
104 return dram_size;
105}