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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * mv_eth.h - header file for the polled mode GT ethernet driver
29 */
30
31#ifndef __DB64360_ETH_H__
32#define __DB64360_ETH_H__
33
34#include <asm/types.h>
35#include <asm/io.h>
36#include <asm/byteorder.h>
37#include <common.h>
38#include <net.h>
39#include "mv_regs.h"
Michal Simekbc0d3292009-06-30 23:47:30 +100040#include <asm/errno.h>
wdenk3a473b22004-01-03 00:43:19 +000041
42/*************************************************************************
43**************************************************************************
44**************************************************************************
45* The first part is the high level driver of the gigE ethernet ports. *
46**************************************************************************
47**************************************************************************
48*************************************************************************/
49#ifndef TRUE
50#define TRUE 1
51#endif
52#ifndef FALSE
53#define FALSE 0
54#endif
55
56/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
57#ifndef MAX_SKB_FRAGS
58#define MAX_SKB_FRAGS 0
59#endif
60
61/* Port attributes */
62/*#define MAX_RX_QUEUE_NUM 8*/
63/*#define MAX_TX_QUEUE_NUM 8*/
64#define MAX_RX_QUEUE_NUM 1
65#define MAX_TX_QUEUE_NUM 1
66
67
68/* Use one TX queue and one RX queue */
69#define MV64360_TX_QUEUE_NUM 1
70#define MV64360_RX_QUEUE_NUM 1
71
72/*
73 * Number of RX / TX descriptors on RX / TX rings.
74 * Note that allocating RX descriptors is done by allocating the RX
75 * ring AND a preallocated RX buffers (skb's) for each descriptor.
76 * The TX descriptors only allocates the TX descriptors ring,
77 * with no pre allocated TX buffers (skb's are allocated by higher layers.
78 */
79
80/* Default TX ring size is 10 descriptors */
81#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
82#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
83#else
84#define MV64360_TX_QUEUE_SIZE 4
85#endif
86
87/* Default RX ring size is 4 descriptors */
88#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
89#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
90#else
91#define MV64360_RX_QUEUE_SIZE 4
92#endif
93
94#ifdef CONFIG_RX_BUFFER_SIZE
95#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
96#else
97#define MV64360_RX_BUFFER_SIZE 1600
98#endif
99
100#ifdef CONFIG_TX_BUFFER_SIZE
101#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
102#else
103#define MV64360_TX_BUFFER_SIZE 1600
104#endif
105
106
107/*
108 * Network device statistics. Akin to the 2.0 ether stats but
109 * with byte counters.
110 */
111
112struct net_device_stats
113{
114 unsigned long rx_packets; /* total packets received */
115 unsigned long tx_packets; /* total packets transmitted */
116 unsigned long rx_bytes; /* total bytes received */
117 unsigned long tx_bytes; /* total bytes transmitted */
118 unsigned long rx_errors; /* bad packets received */
119 unsigned long tx_errors; /* packet transmit problems */
120 unsigned long rx_dropped; /* no space in linux buffers */
121 unsigned long tx_dropped; /* no space available in linux */
122 unsigned long multicast; /* multicast packets received */
123 unsigned long collisions;
124
125 /* detailed rx_errors: */
126 unsigned long rx_length_errors;
127 unsigned long rx_over_errors; /* receiver ring buff overflow */
128 unsigned long rx_crc_errors; /* recved pkt with crc error */
129 unsigned long rx_frame_errors; /* recv'd frame alignment error */
130 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
131 unsigned long rx_missed_errors; /* receiver missed packet */
132
133 /* detailed tx_errors */
134 unsigned long tx_aborted_errors;
135 unsigned long tx_carrier_errors;
136 unsigned long tx_fifo_errors;
137 unsigned long tx_heartbeat_errors;
138 unsigned long tx_window_errors;
139
140 /* for cslip etc */
141 unsigned long rx_compressed;
142 unsigned long tx_compressed;
143};
144
145
146/* Private data structure used for ethernet device */
147struct mv64360_eth_priv {
148 unsigned int port_num;
149 struct net_device_stats *stats;
150
151/* to buffer area aligned */
152 char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
153 char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
154
155 /* Size of Tx Ring per queue */
156 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
157
158
159 /* Size of Rx Ring per queue */
160 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
161
162 /* Magic Number for Ethernet running */
163 unsigned int eth_running;
164
165};
166
167
168int mv64360_eth_init (struct eth_device *dev);
169int mv64360_eth_stop (struct eth_device *dev);
170int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
171/* return db64360_eth0_poll(); */
172
173int mv64360_eth_open (struct eth_device *dev);
174
175
176/*************************************************************************
177**************************************************************************
178**************************************************************************
179* The second part is the low level driver of the gigE ethernet ports. *
180**************************************************************************
181**************************************************************************
182*************************************************************************/
183
184
185/********************************************************************************
186 * Header File for : MV-643xx network interface header
187 *
188 * DESCRIPTION:
189 * This header file contains macros typedefs and function declaration for
190 * the Marvell Gig Bit Ethernet Controller.
191 *
192 * DEPENDENCIES:
193 * None.
194 *
195 *******************************************************************************/
196
197
198#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
199#ifdef CONFIG_MV64360_SRAM_CACHEABLE
200/* In case SRAM is cacheable but not cache coherent */
201#define D_CACHE_FLUSH_LINE(addr, offset) \
202{ \
203 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
204}
205#else
206/* In case SRAM is cache coherent or non-cacheable */
207#define D_CACHE_FLUSH_LINE(addr, offset) ;
208#endif
209#else
210#ifdef CONFIG_NOT_COHERENT_CACHE
211/* In case of descriptors on DDR but not cache coherent */
212#define D_CACHE_FLUSH_LINE(addr, offset) \
213{ \
214 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
215}
216#else
217/* In case of descriptors on DDR and cache coherent */
218#define D_CACHE_FLUSH_LINE(addr, offset) ;
219#endif /* CONFIG_NOT_COHERENT_CACHE */
220#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
221
222
223#define CPU_PIPE_FLUSH \
224{ \
225 __asm__ __volatile__ ("eieio"); \
226}
227
228
229/* defines */
230
231/* Default port configuration value */
232#define PORT_CONFIG_VALUE \
233 ETH_UNICAST_NORMAL_MODE | \
234 ETH_DEFAULT_RX_QUEUE_0 | \
235 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
236 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
237 ETH_RECEIVE_BC_IF_IP | \
238 ETH_RECEIVE_BC_IF_ARP | \
239 ETH_CAPTURE_TCP_FRAMES_DIS | \
240 ETH_CAPTURE_UDP_FRAMES_DIS | \
241 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
242 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
243 ETH_DEFAULT_RX_BPDU_QUEUE_0
244
245/* Default port extend configuration value */
246#define PORT_CONFIG_EXTEND_VALUE \
247 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
248 ETH_PARTITION_DISABLE
249
250
251/* Default sdma control value */
252#ifdef CONFIG_NOT_COHERENT_CACHE
253#define PORT_SDMA_CONFIG_VALUE \
254 ETH_RX_BURST_SIZE_16_64BIT | \
255 GT_ETH_IPG_INT_RX(0) | \
256 ETH_TX_BURST_SIZE_16_64BIT;
257#else
258#define PORT_SDMA_CONFIG_VALUE \
259 ETH_RX_BURST_SIZE_4_64BIT | \
260 GT_ETH_IPG_INT_RX(0) | \
261 ETH_TX_BURST_SIZE_4_64BIT;
262#endif
263
264#define GT_ETH_IPG_INT_RX(value) \
265 ((value & 0x3fff) << 8)
266
267/* Default port serial control value */
268#define PORT_SERIAL_CONTROL_VALUE \
269 ETH_FORCE_LINK_PASS | \
270 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
271 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
272 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
273 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
274 ETH_FORCE_BP_MODE_NO_JAM | \
275 BIT9 | \
276 ETH_DO_NOT_FORCE_LINK_FAIL | \
277 ETH_RETRANSMIT_16_ETTEMPTS | \
278 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
279 ETH_DTE_ADV_0 | \
280 ETH_DISABLE_AUTO_NEG_BYPASS | \
281 ETH_AUTO_NEG_NO_CHANGE | \
282 ETH_MAX_RX_PACKET_1552BYTE | \
283 ETH_CLR_EXT_LOOPBACK | \
284 ETH_SET_FULL_DUPLEX_MODE | \
285 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
286
287#define RX_BUFFER_MAX_SIZE 0xFFFF
288#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
289
290#define RX_BUFFER_MIN_SIZE 0x8
291#define TX_BUFFER_MIN_SIZE 0x8
292
293/* Tx WRR confoguration macros */
294#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
295#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
296#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
297
298/* MAC accepet/reject macros */
299#define ACCEPT_MAC_ADDR 0
300#define REJECT_MAC_ADDR 1
301
302/* Size of a Tx/Rx descriptor used in chain list data structure */
303#define RX_DESC_ALIGNED_SIZE 0x20
304#define TX_DESC_ALIGNED_SIZE 0x20
305
306/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
307#define TX_BUF_OFFSET_IN_DESC 0x18
308/* Buffer offset from buffer pointer */
309#define RX_BUF_OFFSET 0x2
310
311/* Gap define */
312#define ETH_BAR_GAP 0x8
313#define ETH_SIZE_REG_GAP 0x8
314#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
315#define ETH_PORT_ACCESS_CTRL_GAP 0x4
316
317/* Gigabit Ethernet Unit Global Registers */
318
319/* MIB Counters register definitions */
320#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
321#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
322#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
323#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
324#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
325#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
326#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
327#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
328#define ETH_MIB_FRAMES_64_OCTETS 0x20
329#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
330#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
331#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
332#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
333#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
334#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
335#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
336#define ETH_MIB_GOOD_FRAMES_SENT 0x40
337#define ETH_MIB_EXCESSIVE_COLLISION 0x44
338#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
339#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
340#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
341#define ETH_MIB_FC_SENT 0x54
342#define ETH_MIB_GOOD_FC_RECEIVED 0x58
343#define ETH_MIB_BAD_FC_RECEIVED 0x5c
344#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
345#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
346#define ETH_MIB_OVERSIZE_RECEIVED 0x68
347#define ETH_MIB_JABBER_RECEIVED 0x6c
348#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
349#define ETH_MIB_BAD_CRC_EVENT 0x74
350#define ETH_MIB_COLLISION 0x78
351#define ETH_MIB_LATE_COLLISION 0x7c
352
353/* Port serial status reg (PSR) */
354#define ETH_INTERFACE_GMII_MII 0
355#define ETH_INTERFACE_PCM BIT0
356#define ETH_LINK_IS_DOWN 0
357#define ETH_LINK_IS_UP BIT1
358#define ETH_PORT_AT_HALF_DUPLEX 0
359#define ETH_PORT_AT_FULL_DUPLEX BIT2
360#define ETH_RX_FLOW_CTRL_DISABLED 0
361#define ETH_RX_FLOW_CTRL_ENBALED BIT3
362#define ETH_GMII_SPEED_100_10 0
363#define ETH_GMII_SPEED_1000 BIT4
364#define ETH_MII_SPEED_10 0
365#define ETH_MII_SPEED_100 BIT5
366#define ETH_NO_TX 0
367#define ETH_TX_IN_PROGRESS BIT7
368#define ETH_BYPASS_NO_ACTIVE 0
369#define ETH_BYPASS_ACTIVE BIT8
370#define ETH_PORT_NOT_AT_PARTITION_STATE 0
371#define ETH_PORT_AT_PARTITION_STATE BIT9
372#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
373#define ETH_PORT_TX_FIFO_EMPTY BIT10
374
375
376/* These macros describes the Port configuration reg (Px_cR) bits */
377#define ETH_UNICAST_NORMAL_MODE 0
378#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
379#define ETH_DEFAULT_RX_QUEUE_0 0
380#define ETH_DEFAULT_RX_QUEUE_1 BIT1
381#define ETH_DEFAULT_RX_QUEUE_2 BIT2
382#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
383#define ETH_DEFAULT_RX_QUEUE_4 BIT3
384#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
385#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
386#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
387#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
388#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
389#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
390#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
391#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
392#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
393#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
394#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
395#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
396#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
397#define ETH_RECEIVE_BC_IF_IP 0
398#define ETH_REJECT_BC_IF_IP BIT8
399#define ETH_RECEIVE_BC_IF_ARP 0
400#define ETH_REJECT_BC_IF_ARP BIT9
401#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
402#define ETH_CAPTURE_TCP_FRAMES_DIS 0
403#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
404#define ETH_CAPTURE_UDP_FRAMES_DIS 0
405#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
406#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
407#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
408#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
409#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
410#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
411#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
412#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
413#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
414#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
415#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
416#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
417#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
418#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
419#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
420#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
421#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
422#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
423#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
424#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
425#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
426#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
427#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
428#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
429#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
430
431
432/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
433#define ETH_CLASSIFY_EN BIT0
434#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
435#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
436#define ETH_PARTITION_DISABLE 0
437#define ETH_PARTITION_ENABLE BIT2
438
439
440/* Tx/Rx queue command reg (RQCR/TQCR)*/
441#define ETH_QUEUE_0_ENABLE BIT0
442#define ETH_QUEUE_1_ENABLE BIT1
443#define ETH_QUEUE_2_ENABLE BIT2
444#define ETH_QUEUE_3_ENABLE BIT3
445#define ETH_QUEUE_4_ENABLE BIT4
446#define ETH_QUEUE_5_ENABLE BIT5
447#define ETH_QUEUE_6_ENABLE BIT6
448#define ETH_QUEUE_7_ENABLE BIT7
449#define ETH_QUEUE_0_DISABLE BIT8
450#define ETH_QUEUE_1_DISABLE BIT9
451#define ETH_QUEUE_2_DISABLE BIT10
452#define ETH_QUEUE_3_DISABLE BIT11
453#define ETH_QUEUE_4_DISABLE BIT12
454#define ETH_QUEUE_5_DISABLE BIT13
455#define ETH_QUEUE_6_DISABLE BIT14
456#define ETH_QUEUE_7_DISABLE BIT15
457
458
459/* These macros describes the Port Sdma configuration reg (SDCR) bits */
460#define ETH_RIFB BIT0
461#define ETH_RX_BURST_SIZE_1_64BIT 0
462#define ETH_RX_BURST_SIZE_2_64BIT BIT1
463#define ETH_RX_BURST_SIZE_4_64BIT BIT2
464#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
465#define ETH_RX_BURST_SIZE_16_64BIT BIT3
466#define ETH_BLM_RX_NO_SWAP BIT4
467#define ETH_BLM_RX_BYTE_SWAP 0
468#define ETH_BLM_TX_NO_SWAP BIT5
469#define ETH_BLM_TX_BYTE_SWAP 0
470#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
471#define ETH_DESCRIPTORS_NO_SWAP 0
472#define ETH_TX_BURST_SIZE_1_64BIT 0
473#define ETH_TX_BURST_SIZE_2_64BIT BIT22
474#define ETH_TX_BURST_SIZE_4_64BIT BIT23
475#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
476#define ETH_TX_BURST_SIZE_16_64BIT BIT24
477
478
479/* These macros describes the Port serial control reg (PSCR) bits */
480#define ETH_SERIAL_PORT_DISABLE 0
481#define ETH_SERIAL_PORT_ENABLE BIT0
482#define ETH_FORCE_LINK_PASS BIT1
483#define ETH_DO_NOT_FORCE_LINK_PASS 0
484#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
485#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
486#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
487#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
488#define ETH_ADV_NO_FLOW_CTRL 0
489#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
490#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
491#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
492#define ETH_FORCE_BP_MODE_NO_JAM 0
493#define ETH_FORCE_BP_MODE_JAM_TX BIT7
494#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
495#define ETH_FORCE_LINK_FAIL 0
496#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
497#define ETH_RETRANSMIT_16_ETTEMPTS 0
498#define ETH_RETRANSMIT_FOREVER BIT11
499#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
500#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
501#define ETH_DTE_ADV_0 0
502#define ETH_DTE_ADV_1 BIT14
503#define ETH_DISABLE_AUTO_NEG_BYPASS 0
504#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
505#define ETH_AUTO_NEG_NO_CHANGE 0
506#define ETH_RESTART_AUTO_NEG BIT16
507#define ETH_MAX_RX_PACKET_1518BYTE 0
508#define ETH_MAX_RX_PACKET_1522BYTE BIT17
509#define ETH_MAX_RX_PACKET_1552BYTE BIT18
510#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
511#define ETH_MAX_RX_PACKET_9192BYTE BIT19
512#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
513#define ETH_SET_EXT_LOOPBACK BIT20
514#define ETH_CLR_EXT_LOOPBACK 0
515#define ETH_SET_FULL_DUPLEX_MODE BIT21
516#define ETH_SET_HALF_DUPLEX_MODE 0
517#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
518#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
519#define ETH_SET_GMII_SPEED_TO_10_100 0
520#define ETH_SET_GMII_SPEED_TO_1000 BIT23
521#define ETH_SET_MII_SPEED_TO_10 0
522#define ETH_SET_MII_SPEED_TO_100 BIT24
523
524
525/* SMI reg */
526#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
527#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
528#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
529#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
530
531/* SDMA command status fields macros */
532
533/* Tx & Rx descriptors status */
534#define ETH_ERROR_SUMMARY (BIT0)
535
536/* Tx & Rx descriptors command */
537#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
538
539/* Tx descriptors status */
540#define ETH_LC_ERROR (0 )
541#define ETH_UR_ERROR (BIT1 )
542#define ETH_RL_ERROR (BIT2 )
543#define ETH_LLC_SNAP_FORMAT (BIT9 )
544
545/* Rx descriptors status */
546#define ETH_CRC_ERROR (0 )
547#define ETH_OVERRUN_ERROR (BIT1 )
548#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
549#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
550#define ETH_VLAN_TAGGED (BIT19)
551#define ETH_BPDU_FRAME (BIT20)
552#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
553#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
554#define ETH_OTHER_FRAME_TYPE (BIT22)
555#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
556#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
557#define ETH_FRAME_HEADER_OK (BIT25)
558#define ETH_RX_LAST_DESC (BIT26)
559#define ETH_RX_FIRST_DESC (BIT27)
560#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
561#define ETH_RX_ENABLE_INTERRUPT (BIT29)
562#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
563
564/* Rx descriptors byte count */
565#define ETH_FRAME_FRAGMENTED (BIT2)
566
567/* Tx descriptors command */
568#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
569#define ETH_FRAME_SET_TO_VLAN (BIT15)
570#define ETH_TCP_FRAME (0 )
571#define ETH_UDP_FRAME (BIT16)
572#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
573#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
574#define ETH_ZERO_PADDING (BIT19)
575#define ETH_TX_LAST_DESC (BIT20)
576#define ETH_TX_FIRST_DESC (BIT21)
577#define ETH_GEN_CRC (BIT22)
578#define ETH_TX_ENABLE_INTERRUPT (BIT23)
579#define ETH_AUTO_MODE (BIT30)
580
581/* Address decode parameters */
582/* Ethernet Base Address Register bits */
583#define EBAR_TARGET_DRAM 0x00000000
584#define EBAR_TARGET_DEVICE 0x00000001
585#define EBAR_TARGET_CBS 0x00000002
586#define EBAR_TARGET_PCI0 0x00000003
587#define EBAR_TARGET_PCI1 0x00000004
588#define EBAR_TARGET_CUNIT 0x00000005
589#define EBAR_TARGET_AUNIT 0x00000006
590#define EBAR_TARGET_GUNIT 0x00000007
591
592/* Window attributes */
593#define EBAR_ATTR_DRAM_CS0 0x00000E00
594#define EBAR_ATTR_DRAM_CS1 0x00000D00
595#define EBAR_ATTR_DRAM_CS2 0x00000B00
596#define EBAR_ATTR_DRAM_CS3 0x00000700
597
598/* DRAM Target interface */
599#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
600#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
601#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
602
603/* Device Bus Target interface */
604#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
605#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
606#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
607#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
608#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
609
610/* PCI Target interface */
611#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
612#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
613#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
614#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
615#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
616#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
617#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
618#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
619#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
620#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
621
622/* CPU 60x bus or internal SRAM interface */
623#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
624#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
625#define EBAR_ATTR_CBS_SRAM 0x00000000
626#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
627
628/* Window access control */
629#define EWIN_ACCESS_NOT_ALLOWED 0
630#define EWIN_ACCESS_READ_ONLY BIT0
631#define EWIN_ACCESS_FULL (BIT1 | BIT0)
632#define EWIN0_ACCESS_MASK 0x0003
633#define EWIN1_ACCESS_MASK 0x000C
634#define EWIN2_ACCESS_MASK 0x0030
635#define EWIN3_ACCESS_MASK 0x00C0
636
637/* typedefs */
638
639typedef enum _eth_port
640{
641 ETH_0 = 0,
642 ETH_1 = 1,
643 ETH_2 = 2
644}ETH_PORT;
645
646typedef enum _eth_func_ret_status
647{
648 ETH_OK, /* Returned as expected. */
649 ETH_ERROR, /* Fundamental error. */
650 ETH_RETRY, /* Could not process request. Try later. */
651 ETH_END_OF_JOB, /* Ring has nothing to process. */
652 ETH_QUEUE_FULL, /* Ring resource error. */
653 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
654}ETH_FUNC_RET_STATUS;
655
656typedef enum _eth_queue
657{
658 ETH_Q0 = 0,
659 ETH_Q1 = 1,
660 ETH_Q2 = 2,
661 ETH_Q3 = 3,
662 ETH_Q4 = 4,
663 ETH_Q5 = 5,
664 ETH_Q6 = 6,
665 ETH_Q7 = 7
666} ETH_QUEUE;
667
668typedef enum _addr_win
669{
670 ETH_WIN0,
671 ETH_WIN1,
672 ETH_WIN2,
673 ETH_WIN3,
674 ETH_WIN4,
675 ETH_WIN5
676} ETH_ADDR_WIN;
677
678typedef enum _eth_target
679{
680 ETH_TARGET_DRAM ,
681 ETH_TARGET_DEVICE,
682 ETH_TARGET_CBS ,
683 ETH_TARGET_PCI0 ,
684 ETH_TARGET_PCI1
685}ETH_TARGET;
686
687typedef struct _eth_rx_desc
688{
689 unsigned short byte_cnt ; /* Descriptor buffer byte count */
690 unsigned short buf_size ; /* Buffer size */
691 unsigned int cmd_sts ; /* Descriptor command status */
692 unsigned int next_desc_ptr; /* Next descriptor pointer */
693 unsigned int buf_ptr ; /* Descriptor buffer pointer */
694 unsigned int return_info ; /* User resource return information */
695} ETH_RX_DESC;
696
697
698typedef struct _eth_tx_desc
699{
700 unsigned short byte_cnt ; /* Descriptor buffer byte count */
701 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
702 unsigned int cmd_sts ; /* Descriptor command status */
703 unsigned int next_desc_ptr; /* Next descriptor pointer */
704 unsigned int buf_ptr ; /* Descriptor buffer pointer */
705 unsigned int return_info ; /* User resource return information */
706} ETH_TX_DESC;
707
708/* Unified struct for Rx and Tx operations. The user is not required to */
709/* be familier with neither Tx nor Rx descriptors. */
710typedef struct _pkt_info
711{
712 unsigned short byte_cnt ; /* Descriptor buffer byte count */
713 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
714 unsigned int cmd_sts ; /* Descriptor command status */
715 unsigned int buf_ptr ; /* Descriptor buffer pointer */
716 unsigned int return_info ; /* User resource return information */
717} PKT_INFO;
718
719
720typedef struct _eth_win_param
721{
722 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
723 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
724 unsigned short attributes; /* BAR attributes. See above macros. */
725 unsigned int base_addr; /* Window base address in unsigned int form */
726 unsigned int high_addr; /* Window high address in unsigned int form */
727 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
728 bool enable; /* Enable/disable access to the window. */
729 unsigned short access_ctrl; /* Access ctrl register. see above macros */
730} ETH_WIN_PARAM;
731
732
733/* Ethernet port specific infomation */
734
735typedef struct _eth_port_ctrl
736{
737 ETH_PORT port_num; /* User Ethernet port number */
738 int port_phy_addr; /* User phy address of Ethrnet port */
739 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
740 unsigned int port_config; /* User port configuration value */
741 unsigned int port_config_extend; /* User port config extend value */
742 unsigned int port_sdma_config; /* User port SDMA config value */
743 unsigned int port_serial_control; /* User port serial control value */
744 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
745 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
746
747 /* User function to cast virtual address to CPU bus address */
748 unsigned int (*port_virt_to_phys)(unsigned int addr);
749 /* User scratch pad for user specific data structures */
750 void *port_private;
751
752 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
753 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
754
755 /* Tx/Rx rings managment indexes fields. For driver use */
756
757 /* Next available Rx resource */
758 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
759 /* Returning Rx resource */
760 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
761
762 /* Next available Tx resource */
763 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
764 /* Returning Tx resource */
765 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
766 /* An extra Tx index to support transmit of multiple buffers per packet */
767 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
768
769 /* Tx/Rx rings size and base variables fields. For driver use */
770
771 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
772 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
773 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
774
775 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
776 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
777 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
778
779} ETH_PORT_INFO;
780
781
782/* ethernet.h API list */
783
784/* Port operation control routines */
785static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
786static void eth_port_reset(ETH_PORT eth_port_num);
787static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
788
789
790/* Port MAC address routines */
791static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
792 unsigned char *p_addr,
793 ETH_QUEUE queue);
794#if 0 /* FIXME */
795static void eth_port_mc_addr (ETH_PORT eth_port_num,
796 unsigned char *p_addr,
797 ETH_QUEUE queue,
798 int option);
799#endif
800
801/* PHY and MIB routines */
802static bool ethernet_phy_reset(ETH_PORT eth_port_num);
803
804static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
805 unsigned int phy_reg,
806 unsigned int value);
807
808static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
809 unsigned int phy_reg,
810 unsigned int* value);
811
812static void eth_clear_mib_counters(ETH_PORT eth_port_num);
813
814/* Port data flow control routines */
815static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
816 ETH_QUEUE tx_queue,
817 PKT_INFO *p_pkt_info);
818static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
819 ETH_QUEUE tx_queue,
820 PKT_INFO *p_pkt_info);
821static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
822 ETH_QUEUE rx_queue,
823 PKT_INFO *p_pkt_info);
824static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
825 ETH_QUEUE rx_queue,
826 PKT_INFO *p_pkt_info);
827
828
829static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
830 ETH_QUEUE tx_queue,
831 int tx_desc_num,
832 int tx_buff_size,
833 unsigned int tx_desc_base_addr,
834 unsigned int tx_buff_base_addr);
835
836static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
837 ETH_QUEUE rx_queue,
838 int rx_desc_num,
839 int rx_buff_size,
840 unsigned int rx_desc_base_addr,
841 unsigned int rx_buff_base_addr);
842
843#endif /* MV64360_ETH_ */