blob: 548d52c6a00fa2141412c2d5c490c16ab1a8c0dc [file] [log] [blame]
Graeme Russc620c012008-12-07 10:28:57 +11001/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Graeme Russbf165002010-04-24 00:05:47 +100024#include <asm/ibmpc.h>
Graeme Russc620c012008-12-07 10:28:57 +110025/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
Graeme Russc620c012008-12-07 10:28:57 +110033 * High Level Configuration Options
34 * (easy to change)
35 */
Graeme Russcfbe8612011-02-12 15:11:48 +110036#define CONFIG_SYS_SC520
Graeme Russ6d83e3a2009-02-24 21:12:20 +110037#define CONFIG_SYS_SC520_SSI
Graeme Russcfbe8612011-02-12 15:11:48 +110038#define CONFIG_SHOW_BOOT_PROGRESS
39#define CONFIG_LAST_STAGE_INIT
Graeme Russc620c012008-12-07 10:28:57 +110040
Graeme Russcfbe8612011-02-12 15:11:48 +110041/*-----------------------------------------------------------------------
42 * Watchdog Configuration
43 * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
Graeme Russc620c012008-12-07 10:28:57 +110044 * bottom (processor) board MUST be removed!
45 */
46#undef CONFIG_WATCHDOG
Graeme Russ880c59e2010-04-24 00:05:58 +100047#define CONFIG_HW_WATCHDOG
Graeme Russc620c012008-12-07 10:28:57 +110048
Graeme Russcfbe8612011-02-12 15:11:48 +110049/*-----------------------------------------------------------------------
50 * Real Time Clock Configuration
51 */
52#define CONFIG_RTC_MC146818
53#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
54
55/*-----------------------------------------------------------------------
56 * Serial Configuration
57 */
Graeme Russbf165002010-04-24 00:05:47 +100058#define CONFIG_SERIAL_MULTI
Graeme Russcfbe8612011-02-12 15:11:48 +110059#define CONFIG_CONS_INDEX 1
Graeme Russbf165002010-04-24 00:05:47 +100060#define CONFIG_SYS_NS16550
61#define CONFIG_SYS_NS16550_SERIAL
Graeme Russcfbe8612011-02-12 15:11:48 +110062#define CONFIG_SYS_NS16550_REG_SIZE 1
63#define CONFIG_SYS_NS16550_CLK 1843200
64#define CONFIG_BAUDRATE 9600
65#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
66 9600, 19200, 38400, 115200}
67#define CONFIG_SYS_NS16550_COM1 UART0_BASE
68#define CONFIG_SYS_NS16550_COM2 UART1_BASE
69#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
70#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
Graeme Russbf165002010-04-24 00:05:47 +100071#define CONFIG_SYS_NS16550_PORT_MAPPED
72
Graeme Russcfbe8612011-02-12 15:11:48 +110073/*-----------------------------------------------------------------------
74 * Video Configuration
Graeme Russc620c012008-12-07 10:28:57 +110075 */
Graeme Russcfbe8612011-02-12 15:11:48 +110076#undef CONFIG_VIDEO
77#undef CONFIG_CFB_CONSOLE
Graeme Russc620c012008-12-07 10:28:57 +110078
Graeme Russc620c012008-12-07 10:28:57 +110079/*-----------------------------------------------------------------------
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
Graeme Russcfbe8612011-02-12 15:11:48 +110084#define CONFIG_CMD_BDI
85#define CONFIG_CMD_BOOTD
86#define CONFIG_CMD_CONSOLE
Graeme Russ21831002011-02-12 15:11:43 +110087#define CONFIG_CMD_DATE
Graeme Russcfbe8612011-02-12 15:11:48 +110088#define CONFIG_CMD_ECHO
89#define CONFIG_CMD_FLASH
90#define CONFIG_CMD_FPGA
91#define CONFIG_CMD_IMI
92#define CONFIG_CMD_IMLS
93#define CONFIG_CMD_IRQ
94#define CONFIG_CMD_ITEST
95#define CONFIG_CMD_LOADB
96#define CONFIG_CMD_LOADS
97#define CONFIG_CMD_MEMORY
98#define CONFIG_CMD_MISC
99#define CONFIG_CMD_NET
100#undef CONFIG_CMD_NFS
101#define CONFIG_CMD_PCI
102#define CONFIG_CMD_PING
103#define CONFIG_CMD_RUN
104#define CONFIG_CMD_SAVEENV
105#define CONFIG_CMD_SETGETDCR
106#define CONFIG_CMD_SOURCE
107#define CONFIG_CMD_XIMG
Graeme Russc620c012008-12-07 10:28:57 +1100108
Graeme Russcfbe8612011-02-12 15:11:48 +1100109#define CONFIG_BOOTDELAY 15
110#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
Graeme Russc620c012008-12-07 10:28:57 +1100111
112#if defined(CONFIG_CMD_KGDB)
Graeme Russcfbe8612011-02-12 15:11:48 +1100113#define CONFIG_KGDB_BAUDRATE 115200
114#define CONFIG_KGDB_SER_INDEX 2
Graeme Russc620c012008-12-07 10:28:57 +1100115#endif
116
117/*
118 * Miscellaneous configurable options
119 */
Graeme Russcfbe8612011-02-12 15:11:48 +1100120#define CONFIG_SYS_LONGHELP
121#define CONFIG_SYS_PROMPT "boot > "
122#define CONFIG_SYS_CBSIZE 256
123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
124 sizeof(CONFIG_SYS_PROMPT) + \
125 16)
126#define CONFIG_SYS_MAXARGS 16
127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Graeme Russc620c012008-12-07 10:28:57 +1100128
Graeme Russcfbe8612011-02-12 15:11:48 +1100129#define CONFIG_SYS_MEMTEST_START 0x00100000
130#define CONFIG_SYS_MEMTEST_END 0x01000000
131#define CONFIG_SYS_LOAD_ADDR 0x100000
132#define CONFIG_SYS_HZ 1000
Graeme Russc620c012008-12-07 10:28:57 +1100133
Graeme Russc620c012008-12-07 10:28:57 +1100134/*-----------------------------------------------------------------------
135 * SDRAM Configuration
136 */
Graeme Russcfbe8612011-02-12 15:11:48 +1100137#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
Graeme Russ96cd6642011-02-12 15:11:54 +1100138#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
Graeme Russcfbe8612011-02-12 15:11:48 +1100139#define CONFIG_NR_DRAM_BANKS 4
Graeme Russc620c012008-12-07 10:28:57 +1100140
141/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
142#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
Graeme Russc620c012008-12-07 10:28:57 +1100143#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
144#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
145#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
146
147/*-----------------------------------------------------------------------
148 * CPU Features
149 */
Graeme Russcfbe8612011-02-12 15:11:48 +1100150#define CONFIG_SYS_SC520_HIGH_SPEED 0
151#define CONFIG_SYS_SC520_RESET
152#define CONFIG_SYS_SC520_TIMER
153#undef CONFIG_SYS_GENERIC_TIMER
Graeme Russabf0cd32009-02-24 21:13:40 +1100154#define CONFIG_SYS_PCAT_INTERRUPTS
Graeme Russcfbe8612011-02-12 15:11:48 +1100155#define CONFIG_SYS_NUM_IRQS 16
Graeme Russc620c012008-12-07 10:28:57 +1100156
157/*-----------------------------------------------------------------------
Graeme Russcfbe8612011-02-12 15:11:48 +1100158 * Memory organization:
159 * 32kB Stack
Graeme Russec8016c2011-04-13 19:43:24 +1000160 * 16kB Cache-As-RAM @ 0x19200000
Graeme Russcfbe8612011-02-12 15:11:48 +1100161 * 256kB Monitor
Graeme Russec8016c2011-04-13 19:43:24 +1000162 * (128kB + Environment Sector Size) malloc pool
Graeme Russc620c012008-12-07 10:28:57 +1100163 */
Graeme Russec8016c2011-04-13 19:43:24 +1000164#define CONFIG_SYS_STACK_SIZE (32 * 1024)
Graeme Russed4cba72011-02-12 15:11:52 +1100165#define CONFIG_SYS_CAR_ADDR 0x19200000
Graeme Russec8016c2011-04-13 19:43:24 +1000166#define CONFIG_SYS_CAR_SIZE (16 * 1024)
Graeme Russed4cba72011-02-12 15:11:52 +1100167#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
168 CONFIG_SYS_CAR_SIZE)
Graeme Russcfbe8612011-02-12 15:11:48 +1100169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
170#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Graeme Russec8016c2011-04-13 19:43:24 +1000171#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
172 128*1024)
Graeme Russ2e2613d2011-02-12 15:11:50 +1100173/* Address of temporary Global Data */
Graeme Russ8b1a7142011-02-12 15:12:14 +1100174#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR
Graeme Russ2e2613d2011-02-12 15:11:50 +1100175
Graeme Russc620c012008-12-07 10:28:57 +1100176
177/* allow to overwrite serial and ethaddr */
178#define CONFIG_ENV_OVERWRITE
179
Graeme Russcfbe8612011-02-12 15:11:48 +1100180/*-----------------------------------------------------------------------
181 * FLASH configuration
182 * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
183 * 16MB StrataFlash #1 @ 0x10000000
184 * 16MB StrataFlash #2 @ 0x11000000
185 */
186#define CONFIG_FLASH_CFI_DRIVER
Graeme Russc620c012008-12-07 10:28:57 +1100187#define CONFIG_FLASH_CFI_LEGACY
Graeme Russcfbe8612011-02-12 15:11:48 +1100188#define CONFIG_SYS_FLASH_CFI
189#define CONFIG_SYS_MAX_FLASH_BANKS 3
190#define CONFIG_SYS_FLASH_BASE 0x38000000
191#define CONFIG_SYS_FLASH_BASE_1 0x10000000
192#define CONFIG_SYS_FLASH_BASE_2 0x11000000
193#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
194 CONFIG_SYS_FLASH_BASE_1, \
195 CONFIG_SYS_FLASH_BASE_2}
Graeme Russc620c012008-12-07 10:28:57 +1100196#define CONFIG_SYS_FLASH_EMPTY_INFO
Graeme Russ6fd445c2010-04-24 00:05:51 +1000197#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Graeme Russcfbe8612011-02-12 15:11:48 +1100198#define CONFIG_SYS_MAX_FLASH_SECT 128
199#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Graeme Russc620c012008-12-07 10:28:57 +1100200#define CONFIG_SYS_FLASH_LEGACY_512Kx8
Graeme Russcfbe8612011-02-12 15:11:48 +1100201#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
202#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
Graeme Russec8016c2011-04-13 19:43:24 +1000203
Graeme Russcfbe8612011-02-12 15:11:48 +1100204/*-----------------------------------------------------------------------
205 * Environment configuration
Graeme Russec8016c2011-04-13 19:43:24 +1000206 * - Boot flash is 512kB with 64kB sectors
207 * - StrataFlash is 32MB with 128kB sectors
208 * - Redundant embedded environment is 25% of the Boot flash
209 * - Redundant StrataFlash environment is <1% of the StrataFlash
210 * - Environment is therefore located in StrataFlash
211 * - Primary copy is located in first sector of first flash
212 * - Redundant copy is located in second sector of first flash
213 * - Stack is only 32kB, so environment size is limited to 4kB
Graeme Russcfbe8612011-02-12 15:11:48 +1100214 */
215#define CONFIG_ENV_IS_IN_FLASH
216#define CONFIG_ENV_SECT_SIZE 0x20000
Graeme Russec8016c2011-04-13 19:43:24 +1000217#define CONFIG_ENV_SIZE 0x01000
Graeme Russcfbe8612011-02-12 15:11:48 +1100218#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
Graeme Russcfbe8612011-02-12 15:11:48 +1100219#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
220 CONFIG_ENV_SECT_SIZE)
Graeme Russec8016c2011-04-13 19:43:24 +1000221#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Graeme Russc620c012008-12-07 10:28:57 +1100222
Graeme Russcfbe8612011-02-12 15:11:48 +1100223/*-----------------------------------------------------------------------
224 * PCI configuration
225 */
226#define CONFIG_PCI
227#define CONFIG_PCI_PNP
228#define CONFIG_SYS_FIRST_PCI_IRQ 10
229#define CONFIG_SYS_SECOND_PCI_IRQ 9
230#define CONFIG_SYS_THIRD_PCI_IRQ 11
231#define CONFIG_SYS_FORTH_PCI_IRQ 15
Graeme Russc620c012008-12-07 10:28:57 +1100232
Graeme Russcfbe8612011-02-12 15:11:48 +1100233/*-----------------------------------------------------------------------
Graeme Russ8fd80562010-04-24 00:05:55 +1000234 * Network device (TRL8100B) support
235 */
236#define CONFIG_NET_MULTI
237#define CONFIG_RTL8139
238
Graeme Russc620c012008-12-07 10:28:57 +1100239/*-----------------------------------------------------------------------
Graeme Russ420c7c02011-02-12 15:11:45 +1100240 * BOOTCS Control (for AM29LV040B-120JC)
241 *
242 * 000 0 00 0 000 11 0 011 }- 0x0033
243 * \ / | \| | \ / \| | \ /
244 * | | | | | | | |
245 * | | | | | | | +---- 3 Wait States (First Access)
246 * | | | | | | +------- Reserved
247 * | | | | | +--------- 3 Wait States (Subsequent Access)
248 * | | | | +------------- Reserved
249 * | | | +---------------- Non-Paged Mode
250 * | | +------------------ 8 Bit Wide
251 * | +--------------------- GP Bus
252 * +------------------------ Reserved
253 */
254#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
255
256/*-----------------------------------------------------------------------
257 * ROMCS Control (for E28F128J3A-150 StrataFlash)
258 *
259 * 000 0 01 1 000 01 0 101 }- 0x0615
260 * \ / | \| | \ / \| | \ /
261 * | | | | | | | |
262 * | | | | | | | +---- 5 Wait States (First Access)
263 * | | | | | | +------- Reserved
264 * | | | | | +--------- 1 Wait State (Subsequent Access)
265 * | | | | +------------- Reserved
266 * | | | +---------------- Paged Mode
267 * | | +------------------ 16 Bit Wide
268 * | +--------------------- GP Bus
269 * +------------------------ Reserved
270 */
271#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
272#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
273
274/*-----------------------------------------------------------------------
275 * SC520 General Purpose Bus configuration
276 *
277 * Chip Select Offset 1 Clock Cycle
278 * Chip Select Pulse Width 8 Clock Cycles
279 * Chip Select Read Offset 2 Clock Cycles
280 * Chip Select Read Width 6 Clock Cycles
281 * Chip Select Write Offset 2 Clock Cycles
282 * Chip Select Write Width 6 Clock Cycles
283 * Chip Select Recovery Time 2 Clock Cycles
284 *
285 * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
286 *
287 * |<-------------General Purpose Bus Cycle---------------->|
288 * | |
289 * ----------------------\__________________/------------------
290 * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
291 *
292 * ------------------------\_______________/-------------------
293 * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
294 *
295 * --------------------------\_______________/-----------------
296 * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
297 *
298 * ________/-----------\_______________________________________
299 * |<--->|<--------->|
300 * ^ ^
301 * (GPALEOFF + 1) |
302 * |
303 * (GPALEW + 1)
304 */
305#define CONFIG_SYS_SC520_GPCSOFF 0x00
306#define CONFIG_SYS_SC520_GPCSPW 0x07
307#define CONFIG_SYS_SC520_GPRDOFF 0x01
308#define CONFIG_SYS_SC520_GPRDW 0x05
309#define CONFIG_SYS_SC520_GPWROFF 0x01
310#define CONFIG_SYS_SC520_GPWRW 0x05
311#define CONFIG_SYS_SC520_GPCSRT 0x01
312
313/*-----------------------------------------------------------------------
314 * SC520 Programmable I/O configuration
315 *
316 * Pin Mode Dir. Description
317 * ----------------------------------------------------------------------
318 * PIO0 PIO Output Unused
319 * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
320 * PIO2 PIO Output Auxiliary power output enable
321 * PIO3 GPAEN Output GP Bus Address Enable
322 * PIO4 PIO Output Top Board Enable (active low)
323 * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
324 * PIO6 PIO Input Data output of Power Supply ADC
325 * PIO7 PIO Output Clock input to Power Supply ADC
326 * PIO8 PIO Output Chip Select input of Power Supply ADC
327 * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
328 * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
329 * PIO11 PIO Input StrataFlash 1 Status
330 * PIO12 PIO Input StrataFlash 2 Status
331 * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
332 * PIO14 PIO Input Low Input Voltage Warning (active low)
333 * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
334 * PIO16 PIO Input Power Fail
335 * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
336 * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
337 * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
338 * PIO20 GPIRQ3 Input UART D IRQ
339 * PIO21 GPIRQ2 Input UART C IRQ
340 * PIO22 GPIRQ1 Input UART B IRQ
341 * PIO23 GPIRQ0 Input UART A IRQ
342 * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
343 * PIO25 PIO Input Battery OK Indication
344 * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
345 * PIO27 GPCS0# Output SRAM 1 Chip Select
346 * PIO28 PIO Input Top Board UART CTS
347 * PIO29 PIO Output FPGA Program Mode (active low)
348 * PIO30 PIO Input FPGA Initialised (active low)
349 * PIO31 PIO Input FPGA Done (active low)
350 */
351#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
352#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
353#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
354#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
355
356/*-----------------------------------------------------------------------
357 * PIO Pin defines
358 */
359#define CONFIG_SYS_ENET_AUX_PWR 0x0004
360#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
361#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
362#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
363#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
364#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
365#define CONFIG_SYS_ENET_SF1_MODE 0x0200
366#define CONFIG_SYS_ENET_SF2_MODE 0x0400
367#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
368#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
369#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
370#define CONFIG_SYS_ENET_WATCHDOG 0x8000
371
372#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
373#define CONFIG_SYS_ENET_BAT_OK 0x0200
374#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
375#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
376#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
377#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
378
379/*-----------------------------------------------------------------------
380 * Chip Select Pin Function Select
381 *
382 * 1 1 1 1 1 0 0 0 }- 0xf8
383 * | | | | | | | |
384 * | | | | | | | +--- Reserved
385 * | | | | | | +----- GPCS1_SEL = ROMCS1#
386 * | | | | | +------- GPCS2_SEL = ROMCS2#
387 * | | | | +--------- GPCS3_SEL = GPCS3
388 * | | | +----------- GPCS4_SEL = GPCS4
389 * | | +------------- GPCS5_SEL = GPCS5
390 * | +--------------- GPCS6_SEL = GPCS6
391 * +----------------- GPCS7_SEL = GPCS7
392 */
393#define CONFIG_SYS_SC520_CSPFS 0xf8
394
395/*-----------------------------------------------------------------------
396 * Clock Select (CLKTIMER[CLKTEST] pin)
397 *
398 * 0 111 00 1 0 }- 0x72
399 * | \ / \| | |
400 * | | | | +--- Pin Disabled
401 * | | | +----- Pin is an output
402 * | | +------- Reserved
403 * | +----------- Disabled (pin stays Low)
404 * +-------------- Reserved
405 */
406#define CONFIG_SYS_SC520_CLKSEL 0x72
407
408/*-----------------------------------------------------------------------
409 * Address Decode Control
410 *
411 * 0 00 0 0 0 0 0 }- 0x00
412 * | \| | | | | |
413 * | | | | | | +--- Integrated UART 1 is enabled
414 * | | | | | +----- Integrated UART 2 is enabled
415 * | | | | +------- Integrated RTC is enabled
416 * | | | +--------- Reserved
417 * | | +----------- I/O Hole accesses are forwarded to the external GP bus
418 * | +------------- Reserved
419 * +---------------- Write-protect violations do not generate an IRQ
420 */
421#define CONFIG_SYS_SC520_ADDDECCTL 0x00
422
423/*-----------------------------------------------------------------------
424 * UART Control
425 *
426 * 00000 1 1 1 }- 0x07
427 * \___/ | | |
428 * | | | +--- Transmit TC interrupt enable
429 * | | +----- Receive TC interrupt enable
430 * | +------- 1.8432 MHz
431 * +----------- Reserved
432 */
433#define CONFIG_SYS_SC520_UART1CTL 0x07
434#define CONFIG_SYS_SC520_UART2CTL 0x07
435
436/*-----------------------------------------------------------------------
437 * System Arbiter Control
438 *
439 * 00000 1 1 0 }- 0x06
440 * \___/ | | |
441 * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
442 * | | +----- The system arbiter operates in concurrent mode
443 * | +------- Park the PCI bus on the last master that acquired the bus
444 * +----------- Reserved
445 */
446#define CONFIG_SYS_SC520_SYSARBCTL 0x06
447
448/*-----------------------------------------------------------------------
449 * System Arbiter Master Enable
450 *
451 * 00000000000 0 0 0 1 1 }- 0x06
452 * \_________/ | | | | |
453 * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
454 * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
455 * | | | +------- PCI master REQ2 disabled
456 * | | +--------- PCI master REQ3 disabled
457 * | +----------- PCI master REQ4 disabled
458 * +------------------ Reserved
459 */
460#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
461
462/*-----------------------------------------------------------------------
463 * System Arbiter Master Enable
464 *
465 * 0 0000 0 00 0000 1 000 }- 0x06
466 * | \__/ | \| \__/ | \_/
467 * | | | | | | +---- Reserved
468 * | | | | | +------- Enable CPU-to-PCI bus write posting
469 * | | | | +---------- Reserved
470 * | | | +-------------- PCI bus reads to SDRAM are not automatically
471 * | | | retried
472 * | | +----------------- Target read FIFOs are not snooped during write
473 * | | transactions
474 * | +-------------------- Reserved
475 * +------------------------ Deassert the PCI bus reset signal
476 */
477#define CONFIG_SYS_SC520_HBCTL 0x08
478
479/*-----------------------------------------------------------------------
480 * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
481 * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
482 * \ / | | | | \----+----/ \-----+------/
483 * | | | | | | +---------- Start at 0x38000000
484 * | | | | | +----------------------- 512kB Region Size
485 * | | | | | ((7 + 1) * 64kB)
486 * | | | | +------------------------------ 64kB Page Size
487 * | | | +-------------------------------- Writes Enabled (So it can be
488 * | | | reprogrammed!)
489 * | | +---------------------------------- Caching Disabled
490 * | +------------------------------------ Execution Enabled
491 * +--------------------------------------- BOOTCS
492 */
493#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
494
495/*-----------------------------------------------------------------------
Graeme Russed4cba72011-02-12 15:11:52 +1100496 * Cache-As-RAM (Targets Boot Flash)
497 *
498 * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
499 * \ / | | | | \--+--/ \-------+--------/
500 * | | | | | | +------------ Start at 0x19200000
501 * | | | | | +------------------------- 64k Region Size
502 * | | | | | ((15 + 1) * 4kB)
503 * | | | | +------------------------------ 4kB Page Size
504 * | | | +-------------------------------- Writes Enabled
505 * | | +---------------------------------- Caching Enabled
506 * | +------------------------------------ Execution Prevented
507 * +--------------------------------------- BOOTCS
508 */
509#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
510
511/*-----------------------------------------------------------------------
Graeme Russ420c7c02011-02-12 15:11:45 +1100512 * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
513 *
514 * 001 110 0 000100000 0001000000000000 }- 0x38201000
515 * \ / \ / | \---+---/ \------+-------/
516 * | | | | +----------- Start at 0x00001000
517 * | | | +------------------------ 33 Bytes (0x20 + 1)
518 * | | +------------------------------ Ignored
519 * | +--------------------------------- GPCS6
520 * +------------------------------------- GP Bus I/O
521 */
522#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
523
524/*-----------------------------------------------------------------------
525 * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
526 * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
527 *
528 * 010 101 0 0000000 100000000000000000 }- 0x54020000
529 * 010 111 0 0000000 100000000000000001 }- 0x5c020001
530 * \ / \ / | \--+--/ \-------+--------/
531 * | | | | +------------ Start at 0x200000000
532 * | | | | 0x200010000
533 * | | | +------------------------- 4kB Region Size
534 * | | | ((0 + 1) * 4kB)
535 * | | +------------------------------ 4k Page Size
536 * | +--------------------------------- GPCS5
537 * | GPCS7
538 * +------------------------------------- GP Bus Memory
539 */
540#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
541#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
542
543/*-----------------------------------------------------------------------
544 * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
545 * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
546 * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
547 * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
548 *
549 * 001 000 0 000000111 0001001111111000 }- 0x200713f8
550 * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
551 * 001 011 0 000000111 0001001011111000 }- 0x300711f8
552 * 001 011 0 000000111 0001001011111000 }- 0x340710f8
553 * \ / \ / | \---+---/ \------+-------/
554 * | | | | +----------- Start at 0x013f8
555 * | | | | 0x012f8
556 * | | | | 0x011f8
557 * | | | | 0x010f8
558 * | | | +------------------------ 33 Bytes (32 + 1)
559 * | | +------------------------------ Ignored
560 * | +--------------------------------- GPCS6
561 * +------------------------------------- GP Bus I/O
562 */
563#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
564#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
565#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
566#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
567
568/*-----------------------------------------------------------------------
569 * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
570 * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
571 *
572 * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
573 * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
574 * \ / | | | | \----+----/ \-----+------/
575 * | | | | | | +---------- Start at 0x10000000
576 * | | | | | | 0x11000000
577 * | | | | | +----------------------- 16MB Region Size
578 * | | | | | ((255 + 1) * 64kB)
579 * | | | | +------------------------------ 64kB Page Size
580 * | | | +-------------------------------- Writes Enabled
581 * | | +---------------------------------- Caching Disabled
582 * | +------------------------------------ Execution Enabled
583 * +--------------------------------------- ROMCS1
584 * ROMCS2
585 */
586#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
587#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
588
589/*-----------------------------------------------------------------------
590 * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
591 * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
592 *
593 * 010 000 1 00000001111 01100100000000 }- 0x4203d900
594 * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
595 * \ / \ / | \----+----/ \-----+------/
596 * | | | | +---------- Start at 0x19000000
597 * | | | | 0x19100000
598 * | | | +----------------------- 1MB Region Size
599 * | | | ((15 + 1) * 64kB)
600 * | | +------------------------------ 64kB Page Size
601 * | +--------------------------------- GPCS0
602 * | GPCS3
603 * +------------------------------------- GP Bus Memory
604 */
605#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
606#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
607
608/*-----------------------------------------------------------------------
609 * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
610 *
611 * 010 100 0 00000000 11000000100000000 }- 0x50018100
612 * \ / \ / | \---+--/ \-------+-------/
613 * | | | | +----------- Start at 0x18100000
614 * | | | +------------------------ 4kB Region Size
615 * | | | ((0 + 1) * 4kB)
616 * | | +------------------------------ 4kB Page Size
617 * | +--------------------------------- GPCS4
618 * +------------------------------------- GP Bus Memory
619 */
620#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
621
Graeme Russc620c012008-12-07 10:28:57 +1100622#endif /* __CONFIG_H */