blob: d1bb159aefa82b90cf019fba87dae5f2bf1349ce [file] [log] [blame]
Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * Copyright 2004 Freescale Semiconductor, Inc.
3 * Liberty Eran (liberty@freescale.com)
4 */
5
6#ifndef __E300_H__
7#define __E300_H__
8
Scott Wood95e7ef82007-04-16 14:34:16 -05009#define PVR_E300C1 0x80830000
10#define PVR_E300C2 0x80840000
11#define PVR_E300C3 0x80850000
Dave Liu24c3aca2006-12-07 21:13:15 +080012
Eran Libertyf046ccd2005-07-28 10:08:46 -050013/*
14 * Hardware Implementation-Dependent Register 0 (HID0)
15 */
Jon Loeligerde1d0a62005-08-01 13:20:47 -050016
Eran Libertyf046ccd2005-07-28 10:08:46 -050017/* #define HID0 1008 already defined in processor.h */
18#define HID0_MASK_MACHINE_CHECK 0x00000000
19#define HID0_ENABLE_MACHINE_CHECK 0x80000000
20
21#define HID0_DISABLE_CACHE_PARITY 0x00000000
22#define HID0_ENABLE_CACHE_PARITY 0x40000000
23
24#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
25#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
26
27#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
28#define HID0_ENABLE_DATE_PARITY 0x10000000
29
30#define HID0_CORE_CLK_OUT 0x00000000
31#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
32
33#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
34#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
35
36#define HID0_DISABLE_DOSE_MODE 0x00000000
37#define HID0_ENABLE_DOSE_MODE 0x00800000
38
39#define HID0_DISABLE_NAP_MODE 0x00000000
40#define HID0_ENABLE_NAP_MODE 0x00400000
41
42#define HID0_DISABLE_SLEEP_MODE 0x00000000
43#define HID0_ENABLE_SLEEP_MODE 0x00200000
44
45#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
46#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
47
48#define HID0_SOFT_RESET 0x00010000
49
50#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
51#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
52
53#define HID0_DISABLE_DATA_CACHE 0x00000000
54#define HID0_ENABLE_DATA_CACHE 0x00004000
55
56#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
57
58#define HID0_LOCK_DATA_CACHE 0x00001000
59
60#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
61
62#define HID0_INVALIDATE_DATA_CACHE 0x00000400
63
64#define HID0_DISABLE_M_BIT 0x00000000
65#define HID0_ENABLE_M_BIT 0x00000080
66
67#define HID0_FBIOB 0x00000010
68
69#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
70#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
71
72#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
73#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
74
75/*
76 * Hardware Implementation-Dependent Register 2 (HID2)
77 */
78#define HID2 1011
79
80#define HID2_LET 0x08000000
81#define HID2_HBE 0x00040000
82#define HID2_IWLCK_000 0x00000000 /* no ways locked */
83#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
84#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
85#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
86#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
87#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
88#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
89
90
91/* BAT (block address translation */
92#define BATU_BEPI_MSK 0xfffe0000
93#define BATU_BL_MSK 0x00001ffc
94
95#define BATU_BL_128K 0x00000000
96#define BATU_BL_256K 0x00000004
97#define BATU_BL_512K 0x0000000c
98#define BATU_BL_1M 0x0000001c
99#define BATU_BL_2M 0x0000003c
100#define BATU_BL_4M 0x0000007c
101#define BATU_BL_8M 0x000000fc
102#define BATU_BL_16M 0x000001fc
103#define BATU_BL_32M 0x000003fc
104#define BATU_BL_64M 0x000007fc
105#define BATU_BL_128M 0x00000ffc
106#define BATU_BL_256M 0x00001ffc
107
108#define BATU_VS 0x00000002
109#define BATU_VP 0x00000001
110
111#define BATL_BRPN_MSK 0xfffe0000
112#define BATL_WIMG_MSK 0x00000078
113
114#define BATL_WRITETHROUGH 0x00000040
115#define BATL_CACHEINHIBIT 0x00000020
116#define BATL_MEMCOHERENCE 0x00000010
117#define BATL_GUARDEDSTORAGE 0x00000008
118
119#define BATL_PP_MSK 0x00000003
120#define BATL_PP_00 0x00000000 /* No access */
121#define BATL_PP_01 0x00000001 /* Read-only */
122#define BATL_PP_10 0x00000002 /* Read-write */
123#define BATL_PP_11 0x00000003
124
125#endif /* __E300_H__ */