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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 95eca8612b7ba790dfe5d72ce3269ef3a7cdae84 / . / arch / arm / dts / am335x-evm.dts
blob: 2a2972f441f019acfd4df305b9c70239218fb95c [file] [log] [blame]
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 model = "TI AM335x EVM";
15 compatible = "ti,am335x-evm", "ti,am33xx";
16
17 chosen {
18 stdout-path = &uart0;
Mugunthan V Nd3e25ae2015-12-24 16:08:16 +0530[diff] [blame]19 tick-timer = &timer2;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]20 };
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
31 };
32
33 vbat: fixedregulator@0 {
34 compatible = "regulator-fixed";
35 regulator-name = "vbat";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 regulator-boot-on;
39 };
40
41 lis3_reg: fixedregulator@1 {
42 compatible = "regulator-fixed";
43 regulator-name = "lis3_reg";
44 regulator-boot-on;
45 };
46
47 wlan_en_reg: fixedregulator@2 {
48 compatible = "regulator-fixed";
49 regulator-name = "wlan-en-regulator";
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
52
53 /* WLAN_EN GPIO for this board - Bank1, pin16 */
54 gpio = <&gpio1 16 0>;
55
56 /* WLAN card specific delay */
57 startup-delay-us = <70000>;
58 enable-active-high;
59 };
60
61 matrix_keypad: matrix_keypad@0 {
62 compatible = "gpio-matrix-keypad";
63 debounce-delay-ms = <5>;
64 col-scan-delay-us = <2>;
65
66 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
67 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
68 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
69
70 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
71 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
72
73 linux,keymap = <0x0000008b /* MENU */
74 0x0100009e /* BACK */
75 0x02000069 /* LEFT */
76 0x0001006a /* RIGHT */
77 0x0101001c /* ENTER */
78 0x0201006c>; /* DOWN */
79 };
80
81 gpio_keys: volume_keys@0 {
82 compatible = "gpio-keys";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]83 autorepeat;
84
85 switch@9 {
86 label = "volume-up";
87 linux,code = <115>;
88 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
89 gpio-key,wakeup;
90 };
91
92 switch@10 {
93 label = "volume-down";
94 linux,code = <114>;
95 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
96 gpio-key,wakeup;
97 };
98 };
99
100 backlight {
101 compatible = "pwm-backlight";
102 pwms = <&ecap0 0 50000 0>;
103 brightness-levels = <0 51 53 56 62 75 101 152 255>;
104 default-brightness-level = <8>;
105 };
106
107 panel {
108 compatible = "ti,tilcdc,panel";
109 status = "okay";
110 pinctrl-names = "default";
111 pinctrl-0 = <&lcd_pins_s0>;
112 panel-info {
113 ac-bias = <255>;
114 ac-bias-intrpt = <0>;
115 dma-burst-sz = <16>;
116 bpp = <32>;
117 fdd = <0x80>;
118 sync-edge = <0>;
119 sync-ctrl = <1>;
120 raster-order = <0>;
121 fifo-th = <0>;
122 };
123
124 display-timings {
125 800x480p62 {
126 clock-frequency = <30000000>;
127 hactive = <800>;
128 vactive = <480>;
129 hfront-porch = <39>;
130 hback-porch = <39>;
131 hsync-len = <47>;
132 vback-porch = <29>;
133 vfront-porch = <13>;
134 vsync-len = <2>;
135 hsync-active = <1>;
136 vsync-active = <1>;
137 };
138 };
139 };
140
141 sound {
142 compatible = "ti,da830-evm-audio";
143 ti,model = "AM335x-EVM";
144 ti,audio-codec = <&tlv320aic3106>;
145 ti,mcasp-controller = <&mcasp1>;
146 ti,codec-clock-rate = <12000000>;
147 ti,audio-routing =
148 "Headphone Jack", "HPLOUT",
149 "Headphone Jack", "HPROUT",
150 "LINE1L", "Line In",
151 "LINE1R", "Line In";
152 };
153};
154
155&am33xx_pinmux {
156 pinctrl-names = "default";
157 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
158
159 matrix_keypad_s0: matrix_keypad_s0 {
160 pinctrl-single,pins = <
161 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
162 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
163 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
164 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
165 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
166 >;
167 };
168
169 volume_keys_s0: volume_keys_s0 {
170 pinctrl-single,pins = <
171 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
172 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
173 >;
174 };
175
176 i2c0_pins: pinmux_i2c0_pins {
177 pinctrl-single,pins = <
178 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
179 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
180 >;
181 };
182
183 i2c1_pins: pinmux_i2c1_pins {
184 pinctrl-single,pins = <
185 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
186 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
187 >;
188 };
189
190 uart0_pins: pinmux_uart0_pins {
191 pinctrl-single,pins = <
192 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
193 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
194 >;
195 };
196
197 uart1_pins: pinmux_uart1_pins {
198 pinctrl-single,pins = <
199 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
200 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
201 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
202 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
203 >;
204 };
205
206 clkout2_pin: pinmux_clkout2_pin {
207 pinctrl-single,pins = <
208 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
209 >;
210 };
211
212 nandflash_pins_s0: nandflash_pins_s0 {
213 pinctrl-single,pins = <
214 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
215 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
216 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
217 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
218 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
219 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
220 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
221 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
222 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
223 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
224 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
225 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
226 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
227 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
228 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
229 >;
230 };
231
232 ecap0_pins: backlight_pins {
233 pinctrl-single,pins = <
234 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
235 >;
236 };
237
238 cpsw_default: cpsw_default {
239 pinctrl-single,pins = <
240 /* Slave 1 */
241 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
242 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
243 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
244 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
245 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
246 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
247 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
248 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
249 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
250 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
251 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
252 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
253 >;
254 };
255
256 cpsw_sleep: cpsw_sleep {
257 pinctrl-single,pins = <
258 /* Slave 1 reset value */
259 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
260 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
261 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
262 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
263 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
264 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
265 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
266 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
267 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
268 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
269 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
270 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
271 >;
272 };
273
274 davinci_mdio_default: davinci_mdio_default {
275 pinctrl-single,pins = <
276 /* MDIO */
277 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
278 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
279 >;
280 };
281
282 davinci_mdio_sleep: davinci_mdio_sleep {
283 pinctrl-single,pins = <
284 /* MDIO reset value */
285 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
286 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
287 >;
288 };
289
290 mmc1_pins: pinmux_mmc1_pins {
291 pinctrl-single,pins = <
292 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
293 >;
294 };
295
296 mmc3_pins: pinmux_mmc3_pins {
297 pinctrl-single,pins = <
298 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
299 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
300 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
301 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
302 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
303 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
304 >;
305 };
306
307 wlan_pins: pinmux_wlan_pins {
308 pinctrl-single,pins = <
309 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
310 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
311 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
312 >;
313 };
314
315 lcd_pins_s0: lcd_pins_s0 {
316 pinctrl-single,pins = <
317 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
318 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
319 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
320 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
321 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
322 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
323 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
324 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
325 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
326 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
327 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
328 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
329 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
330 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
331 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
332 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
333 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
334 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
335 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
336 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
337 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
338 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
339 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
340 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
341 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
342 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
343 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
344 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
345 >;
346 };
347
348 am335x_evm_audio_pins: am335x_evm_audio_pins {
349 pinctrl-single,pins = <
350 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
351 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
352 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
353 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
354 >;
355 };
356
357 dcan1_pins_default: dcan1_pins_default {
358 pinctrl-single,pins = <
359 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
360 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
361 >;
362 };
363};
364
365&uart0 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart0_pins>;
368
369 status = "okay";
370};
371
372&uart1 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&uart1_pins>;
375
376 status = "okay";
377};
378
379&i2c0 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c0_pins>;
382
383 status = "okay";
384 clock-frequency = <400000>;
385
386 tps: tps@2d {
387 reg = <0x2d>;
388 };
389};
390
391&usb {
392 status = "okay";
393};
394
395&usb_ctrl_mod {
396 status = "okay";
397};
398
399&usb0_phy {
400 status = "okay";
401};
402
403&usb1_phy {
404 status = "okay";
405};
406
407&usb0 {
408 status = "okay";
409};
410
411&usb1 {
412 status = "okay";
413 dr_mode = "host";
414};
415
416&cppi41dma {
417 status = "okay";
418};
419
420&i2c1 {
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c1_pins>;
423
424 status = "okay";
425 clock-frequency = <100000>;
426
427 lis331dlh: lis331dlh@18 {
428 compatible = "st,lis331dlh", "st,lis3lv02d";
429 reg = <0x18>;
430 Vdd-supply = <&lis3_reg>;
431 Vdd_IO-supply = <&lis3_reg>;
432
433 st,click-single-x;
434 st,click-single-y;
435 st,click-single-z;
436 st,click-thresh-x = <10>;
437 st,click-thresh-y = <10>;
438 st,click-thresh-z = <10>;
439 st,irq1-click;
440 st,irq2-click;
441 st,wakeup-x-lo;
442 st,wakeup-x-hi;
443 st,wakeup-y-lo;
444 st,wakeup-y-hi;
445 st,wakeup-z-lo;
446 st,wakeup-z-hi;
447 st,min-limit-x = <120>;
448 st,min-limit-y = <120>;
449 st,min-limit-z = <140>;
450 st,max-limit-x = <550>;
451 st,max-limit-y = <550>;
452 st,max-limit-z = <750>;
453 };
454
455 tsl2550: tsl2550@39 {
456 compatible = "taos,tsl2550";
457 reg = <0x39>;
458 };
459
460 tmp275: tmp275@48 {
461 compatible = "ti,tmp275";
462 reg = <0x48>;
463 };
464
465 tlv320aic3106: tlv320aic3106@1b {
466 compatible = "ti,tlv320aic3106";
467 reg = <0x1b>;
468 status = "okay";
469
470 /* Regulators */
471 AVDD-supply = <&vaux2_reg>;
472 IOVDD-supply = <&vaux2_reg>;
473 DRVDD-supply = <&vaux2_reg>;
474 DVDD-supply = <&vbat>;
475 };
476};
477
478&lcdc {
479 status = "okay";
480};
481
482&elm {
483 status = "okay";
484};
485
486&epwmss0 {
487 status = "okay";
488
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame]489 ecap0: ecap@100 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]490 status = "okay";
491 pinctrl-names = "default";
492 pinctrl-0 = <&ecap0_pins>;
493 };
494};
495
496&gpmc {
497 status = "okay";
498 pinctrl-names = "default";
499 pinctrl-0 = <&nandflash_pins_s0>;
500 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
501 nand@0,0 {
502 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
503 ti,nand-ecc-opt = "bch8";
504 ti,elm-id = <&elm>;
505 nand-bus-width = <8>;
506 gpmc,device-width = <1>;
507 gpmc,sync-clk-ps = <0>;
508 gpmc,cs-on-ns = <0>;
509 gpmc,cs-rd-off-ns = <44>;
510 gpmc,cs-wr-off-ns = <44>;
511 gpmc,adv-on-ns = <6>;
512 gpmc,adv-rd-off-ns = <34>;
513 gpmc,adv-wr-off-ns = <44>;
514 gpmc,we-on-ns = <0>;
515 gpmc,we-off-ns = <40>;
516 gpmc,oe-on-ns = <0>;
517 gpmc,oe-off-ns = <54>;
518 gpmc,access-ns = <64>;
519 gpmc,rd-cycle-ns = <82>;
520 gpmc,wr-cycle-ns = <82>;
521 gpmc,wait-on-read = "true";
522 gpmc,wait-on-write = "true";
523 gpmc,bus-turnaround-ns = <0>;
524 gpmc,cycle2cycle-delay-ns = <0>;
525 gpmc,clk-activation-ns = <0>;
526 gpmc,wait-monitoring-ns = <0>;
527 gpmc,wr-access-ns = <40>;
528 gpmc,wr-data-mux-bus-ns = <0>;
529 /* MTD partition table */
530 /* All SPL-* partitions are sized to minimal length
531 * which can be independently programmable. For
532 * NAND flash this is equal to size of erase-block */
533 #address-cells = <1>;
534 #size-cells = <1>;
535 partition@0 {
536 label = "NAND.SPL";
537 reg = <0x00000000 0x000020000>;
538 };
539 partition@1 {
540 label = "NAND.SPL.backup1";
541 reg = <0x00020000 0x00020000>;
542 };
543 partition@2 {
544 label = "NAND.SPL.backup2";
545 reg = <0x00040000 0x00020000>;
546 };
547 partition@3 {
548 label = "NAND.SPL.backup3";
549 reg = <0x00060000 0x00020000>;
550 };
551 partition@4 {
552 label = "NAND.u-boot-spl-os";
553 reg = <0x00080000 0x00040000>;
554 };
555 partition@5 {
556 label = "NAND.u-boot";
557 reg = <0x000C0000 0x00100000>;
558 };
559 partition@6 {
560 label = "NAND.u-boot-env";
561 reg = <0x001C0000 0x00020000>;
562 };
563 partition@7 {
564 label = "NAND.u-boot-env.backup1";
565 reg = <0x001E0000 0x00020000>;
566 };
567 partition@8 {
568 label = "NAND.kernel";
569 reg = <0x00200000 0x00800000>;
570 };
571 partition@9 {
572 label = "NAND.file-system";
573 reg = <0x00A00000 0x0F600000>;
574 };
575 };
576};
577
578#include "tps65910.dtsi"
579
580&mcasp1 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&am335x_evm_audio_pins>;
583
584 status = "okay";
585
586 op-mode = <0>; /* MCASP_IIS_MODE */
587 tdm-slots = <2>;
588 /* 4 serializers */
589 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
590 0 0 1 2
591 >;
592 tx-num-evt = <32>;
593 rx-num-evt = <32>;
594};
595
596&tps {
597 vcc1-supply = <&vbat>;
598 vcc2-supply = <&vbat>;
599 vcc3-supply = <&vbat>;
600 vcc4-supply = <&vbat>;
601 vcc5-supply = <&vbat>;
602 vcc6-supply = <&vbat>;
603 vcc7-supply = <&vbat>;
604 vccio-supply = <&vbat>;
605
606 regulators {
607 vrtc_reg: regulator@0 {
608 regulator-always-on;
609 };
610
611 vio_reg: regulator@1 {
612 regulator-always-on;
613 };
614
615 vdd1_reg: regulator@2 {
616 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
617 regulator-name = "vdd_mpu";
618 regulator-min-microvolt = <912500>;
619 regulator-max-microvolt = <1312500>;
620 regulator-boot-on;
621 regulator-always-on;
622 };
623
624 vdd2_reg: regulator@3 {
625 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
626 regulator-name = "vdd_core";
627 regulator-min-microvolt = <912500>;
628 regulator-max-microvolt = <1150000>;
629 regulator-boot-on;
630 regulator-always-on;
631 };
632
633 vdd3_reg: regulator@4 {
634 regulator-always-on;
635 };
636
637 vdig1_reg: regulator@5 {
638 regulator-always-on;
639 };
640
641 vdig2_reg: regulator@6 {
642 regulator-always-on;
643 };
644
645 vpll_reg: regulator@7 {
646 regulator-always-on;
647 };
648
649 vdac_reg: regulator@8 {
650 regulator-always-on;
651 };
652
653 vaux1_reg: regulator@9 {
654 regulator-always-on;
655 };
656
657 vaux2_reg: regulator@10 {
658 regulator-always-on;
659 };
660
661 vaux33_reg: regulator@11 {
662 regulator-always-on;
663 };
664
665 vmmc_reg: regulator@12 {
666 regulator-min-microvolt = <1800000>;
667 regulator-max-microvolt = <3300000>;
668 regulator-always-on;
669 };
670 };
671};
672
673&mac {
674 pinctrl-names = "default", "sleep";
675 pinctrl-0 = <&cpsw_default>;
676 pinctrl-1 = <&cpsw_sleep>;
677 status = "okay";
Grygorii Strashko3b3e8a32019-08-31 10:30:34 +0300[diff] [blame]678 slaves = <1>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]679};
680
681&davinci_mdio {
682 pinctrl-names = "default", "sleep";
683 pinctrl-0 = <&davinci_mdio_default>;
684 pinctrl-1 = <&davinci_mdio_sleep>;
685 status = "okay";
Grygorii Strashko3b3e8a32019-08-31 10:30:34 +0300[diff] [blame]686
687 ethphy0: ethernet-phy@0 {
688 reg = <0>;
689 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]690};
691
692&cpsw_emac0 {
Grygorii Strashko3b3e8a32019-08-31 10:30:34 +0300[diff] [blame]693 phy-handle = <&ethphy0>;
694 phy-mode = "rgmii-id";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]695};
696
697&tscadc {
698 status = "okay";
699 tsc {
700 ti,wires = <4>;
701 ti,x-plate-resistance = <200>;
702 ti,coordinate-readouts = <5>;
703 ti,wire-config = <0x00 0x11 0x22 0x33>;
704 ti,charge-delay = <0x400>;
705 };
706
707 adc {
708 ti,adc-channels = <4 5 6 7>;
709 };
710};
711
712&mmc1 {
713 status = "okay";
714 vmmc-supply = <&vmmc_reg>;
715 bus-width = <4>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&mmc1_pins>;
Mugunthan V N2c6485b2016-05-16 11:24:27 +0530[diff] [blame]718 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]719};
720
721&mmc3 {
722 /* these are on the crossbar and are outlined in the
723 xbar-event-map element */
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]724 dmas = <&edma 12 0
725 &edma 13 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]726 dma-names = "tx", "rx";
727 status = "okay";
728 vmmc-supply = <&wlan_en_reg>;
729 bus-width = <4>;
730 pinctrl-names = "default";
731 pinctrl-0 = <&mmc3_pins &wlan_pins>;
732 ti,non-removable;
733 ti,needs-special-hs-handling;
734 cap-power-off-card;
735 keep-power-in-suspend;
736
737 #address-cells = <1>;
738 #size-cells = <0>;
739 wlcore: wlcore@0 {
740 compatible = "ti,wl1835";
741 reg = <2>;
742 interrupt-parent = <&gpio3>;
743 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
744 };
745};
746
747&edma {
748 ti,edma-xbar-event-map = /bits/ 16 <1 12
749 2 13>;
750};
751
752&sham {
753 status = "okay";
754};
755
756&aes {
757 status = "okay";
758};
759
760&dcan1 {
761 status = "disabled"; /* Enable only if Profile 1 is selected */
762 pinctrl-names = "default";
763 pinctrl-0 = <&dcan1_pins_default>;
764};
Dario Binacchi62af4402021-06-02 22:38:03 +0200[diff] [blame]765
766&rtc {
767 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
768 clock-names = "ext-clk", "int-clk";
769};