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Bo Shenf7fa2f32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shenf7fa2f32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen77461a62013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shenf7fa2f32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shenf7fa2f32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shenf7fa2f32012-07-05 17:21:46 +000021
Bo Shenf7fa2f32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
26#define CONFIG_BOARD_EARLY_INIT_F
27#define CONFIG_DISPLAY_CPUINFO
28
Nicolas Ferref9129fe2013-02-20 00:16:24 +000029#define CONFIG_CMD_BOOTZ
Bo Shen49527592014-04-24 11:42:16 +080030
Bo Shenf7fa2f32012-07-05 17:21:46 +000031/* general purpose I/O */
32#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
33#define CONFIG_AT91_GPIO
34
35/* serial console */
36#define CONFIG_ATMEL_USART
37#define CONFIG_USART_BASE ATMEL_BASE_DBGU
38#define CONFIG_USART_ID ATMEL_ID_SYS
39
40/* LCD */
41#define CONFIG_LCD
42#define LCD_BPP LCD_COLOR16
43#define LCD_OUTPUT_BPP 24
44#define CONFIG_LCD_LOGO
Bo Shenf7fa2f32012-07-05 17:21:46 +000045#define CONFIG_LCD_INFO
46#define CONFIG_LCD_INFO_BELOW_LOGO
47#define CONFIG_SYS_WHITE_ON_BLACK
48#define CONFIG_ATMEL_HLCD
49#define CONFIG_ATMEL_LCD_RGB565
50#define CONFIG_SYS_CONSOLE_IS_IN_ENV
51
52#define CONFIG_BOOTDELAY 3
53
54/*
55 * BOOTP options
56 */
57#define CONFIG_BOOTP_BOOTFILESIZE
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_GATEWAY
60#define CONFIG_BOOTP_HOSTNAME
61
Bo Shend51a2a22013-12-10 16:14:02 +080062/* no NOR flash */
63#define CONFIG_SYS_NO_FLASH
64
Bo Shenf7fa2f32012-07-05 17:21:46 +000065/*
66 * Command line configuration.
67 */
Bo Shenf7fa2f32012-07-05 17:21:46 +000068#define CONFIG_CMD_PING
69#define CONFIG_CMD_DHCP
70#define CONFIG_CMD_NAND
Bo Shen1d7442e2012-08-19 20:32:24 +000071#define CONFIG_CMD_SF
Wu, Josh3a49cd72012-09-13 22:22:05 +000072#define CONFIG_CMD_MMC
Richard Genoud419fba02012-11-29 23:18:33 +000073#define CONFIG_CMD_FAT
Richard Genoudb030e732012-11-29 23:18:34 +000074#define CONFIG_CMD_USB
75
76/*
77 * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
78 * NB: in this case, USB 1.1 devices won't be recognized.
79 */
80
Bo Shenf7fa2f32012-07-05 17:21:46 +000081
82/* SDRAM */
83#define CONFIG_NR_DRAM_BANKS 1
84#define CONFIG_SYS_SDRAM_BASE 0x20000000
85#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
86
87#define CONFIG_SYS_INIT_SP_ADDR \
88 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
89
90/* DataFlash */
Bo Shen1d7442e2012-08-19 20:32:24 +000091#ifdef CONFIG_CMD_SF
92#define CONFIG_ATMEL_SPI
Bo Shen1d7442e2012-08-19 20:32:24 +000093#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shenf7fa2f32012-07-05 17:21:46 +000094#endif
95
Bo Shenf7fa2f32012-07-05 17:21:46 +000096/* NAND flash */
97#ifdef CONFIG_CMD_NAND
98#define CONFIG_NAND_ATMEL
99#define CONFIG_SYS_MAX_NAND_DEVICE 1
100#define CONFIG_SYS_NAND_BASE 0x40000000
101#define CONFIG_SYS_NAND_DBW_8 1
102/* our ALE is AD21 */
103#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
104/* our CLE is AD22 */
105#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
106#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
107#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
108
Wu, Joshdf953212012-08-23 00:05:38 +0000109/* PMECC & PMERRLOC */
110#define CONFIG_ATMEL_NAND_HWECC 1
111#define CONFIG_ATMEL_NAND_HW_PMECC 1
112#define CONFIG_PMECC_CAP 2
113#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdf953212012-08-23 00:05:38 +0000114
Bo Shence76f0a2013-06-26 10:48:53 +0800115#define CONFIG_CMD_NAND_TRIMFFS
116
Bo Shenf7fa2f32012-07-05 17:21:46 +0000117#define CONFIG_MTD_DEVICE
118#define CONFIG_CMD_MTDPARTS
119#define CONFIG_MTD_PARTITIONS
120#define CONFIG_RBTREE
121#define CONFIG_LZO
122#define CONFIG_CMD_UBI
123#define CONFIG_CMD_UBIFS
124#endif
125
Wu, Josh3a49cd72012-09-13 22:22:05 +0000126/* MMC */
127#ifdef CONFIG_CMD_MMC
128#define CONFIG_MMC
Wu, Josh3a49cd72012-09-13 22:22:05 +0000129#define CONFIG_GENERIC_MMC
130#define CONFIG_GENERIC_ATMEL_MCI
Richard Genoud419fba02012-11-29 23:18:33 +0000131#endif
132
133/* FAT */
134#ifdef CONFIG_CMD_FAT
Wu, Josh3a49cd72012-09-13 22:22:05 +0000135#define CONFIG_DOS_PARTITION
136#endif
137
Bo Shenf7fa2f32012-07-05 17:21:46 +0000138/* Ethernet */
139#define CONFIG_MACB
140#define CONFIG_RMII
141#define CONFIG_NET_RETRY_COUNT 20
142#define CONFIG_MACB_SEARCH_PHY
143
Richard Genoudb030e732012-11-29 23:18:34 +0000144/* USB */
145#ifdef CONFIG_CMD_USB
146#ifdef CONFIG_USB_EHCI
147#define CONFIG_USB_EHCI_ATMEL
148#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
149#else
Bo Shendcd2f1a2013-10-21 16:14:00 +0800150#define CONFIG_USB_ATMEL
151#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoudb030e732012-11-29 23:18:34 +0000152#define CONFIG_USB_OHCI_NEW
153#define CONFIG_SYS_USB_OHCI_CPU_INIT
154#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
155#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
156#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
157#endif
Richard Genoudb030e732012-11-29 23:18:34 +0000158#define CONFIG_USB_STORAGE
159#endif
160
Bo Shenf7fa2f32012-07-05 17:21:46 +0000161#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
162
163#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
164#define CONFIG_SYS_MEMTEST_END 0x26e00000
165
166#ifdef CONFIG_SYS_USE_NANDFLASH
167/* bootstrap + u-boot + env + linux in nandflash */
168#define CONFIG_ENV_IS_IN_NAND
169#define CONFIG_ENV_OFFSET 0xc0000
170#define CONFIG_ENV_OFFSET_REDUND 0x100000
171#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
172#define CONFIG_BOOTCOMMAND "nand read " \
173 "0x22000000 0x200000 0x300000; " \
174 "bootm 0x22000000"
Wu, Joshb7e31292012-11-02 00:17:27 +0000175#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen1d7442e2012-08-19 20:32:24 +0000176/* bootstrap + u-boot + env + linux in spi flash */
177#define CONFIG_ENV_IS_IN_SPI_FLASH
178#define CONFIG_ENV_OFFSET 0x5000
179#define CONFIG_ENV_SIZE 0x3000
180#define CONFIG_ENV_SECT_SIZE 0x1000
181#define CONFIG_ENV_SPI_MAX_HZ 30000000
182#define CONFIG_BOOTCOMMAND "sf probe 0; " \
183 "sf read 0x22000000 0x100000 0x300000; " \
184 "bootm 0x22000000"
Bo Shen961ffc72012-12-06 21:37:04 +0000185#elif defined(CONFIG_SYS_USE_DATAFLASH)
186/* bootstrap + u-boot + env + linux in data flash */
187#define CONFIG_ENV_IS_IN_SPI_FLASH
188#define CONFIG_ENV_OFFSET 0x4200
189#define CONFIG_ENV_SIZE 0x4200
190#define CONFIG_ENV_SECT_SIZE 0x210
191#define CONFIG_ENV_SPI_MAX_HZ 30000000
192#define CONFIG_BOOTCOMMAND "sf probe 0; " \
193 "sf read 0x22000000 0x84000 0x294000; " \
194 "bootm 0x22000000"
Wu, Joshb7e31292012-11-02 00:17:27 +0000195#else /* CONFIG_SYS_USE_MMC */
196/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh26961772015-01-20 10:33:33 +0800197#define CONFIG_ENV_IS_IN_FAT
198#define CONFIG_FAT_WRITE
199#define FAT_ENV_INTERFACE "mmc"
200#define FAT_ENV_FILE "uboot.env"
201#define FAT_ENV_DEVICE_AND_PART "0"
202#define CONFIG_ENV_SIZE 0x4000
Bo Shenf7fa2f32012-07-05 17:21:46 +0000203#endif
204
Wu, Joshb7e31292012-11-02 00:17:27 +0000205#ifdef CONFIG_SYS_USE_MMC
206#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
207 "mtdparts=atmel_nand:" \
208 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
209 "root=/dev/mmcblk0p2 " \
210 "rw rootfstype=ext4 rootwait"
211#else
Bo Shen0c58cfa2013-02-20 00:16:25 +0000212#define CONFIG_BOOTARGS \
213 "console=ttyS0,115200 earlyprintk " \
214 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
215 "256k(env),256k(env_redundant),256k(spare)," \
216 "512k(dtb),6M(kernel)ro,-(rootfs) " \
217 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Joshb7e31292012-11-02 00:17:27 +0000218#endif
Bo Shenf7fa2f32012-07-05 17:21:46 +0000219
220#define CONFIG_BAUDRATE 115200
221
Bo Shenf7fa2f32012-07-05 17:21:46 +0000222#define CONFIG_SYS_CBSIZE 256
223#define CONFIG_SYS_MAXARGS 16
Bo Shenf7fa2f32012-07-05 17:21:46 +0000224#define CONFIG_SYS_LONGHELP
225#define CONFIG_CMDLINE_EDITING
226#define CONFIG_AUTO_COMPLETE
227#define CONFIG_SYS_HUSH_PARSER
228
229/*
230 * Size of malloc() pool
231 */
232#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
233
Bo Shend85e8912015-03-27 14:23:35 +0800234/* SPL */
235#define CONFIG_SPL_FRAMEWORK
236#define CONFIG_SPL_TEXT_BASE 0x300000
237#define CONFIG_SPL_MAX_SIZE 0x6000
238#define CONFIG_SPL_STACK 0x308000
239
240#define CONFIG_SPL_BSS_START_ADDR 0x20000000
241#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
242#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
243#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
244
245#define CONFIG_SPL_LIBCOMMON_SUPPORT
246#define CONFIG_SPL_LIBGENERIC_SUPPORT
247#define CONFIG_SPL_GPIO_SUPPORT
248#define CONFIG_SPL_SERIAL_SUPPORT
249
250#define CONFIG_SPL_BOARD_INIT
251#define CONFIG_SYS_MONITOR_LEN (512 << 10)
252
253#define CONFIG_SYS_MASTER_CLOCK 132096000
254#define CONFIG_SYS_AT91_PLLA 0x20c73f03
255#define CONFIG_SYS_MCKR 0x1301
256#define CONFIG_SYS_MCKR_CSS 0x1302
257
Bo Shend85e8912015-03-27 14:23:35 +0800258#ifdef CONFIG_SYS_USE_MMC
259#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
260#define CONFIG_SPL_MMC_SUPPORT
261#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
262#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
263#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
264#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
265#define CONFIG_SPL_FAT_SUPPORT
266#define CONFIG_SPL_LIBDISK_SUPPORT
267
268#elif CONFIG_SYS_USE_NANDFLASH
269#define CONFIG_SPL_NAND_SUPPORT
270#define CONFIG_SPL_NAND_DRIVERS
271#define CONFIG_SPL_NAND_BASE
272#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
273#define CONFIG_SYS_NAND_5_ADDR_CYCLE
274#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
275#define CONFIG_SYS_NAND_PAGE_COUNT 64
276#define CONFIG_SYS_NAND_OOBSIZE 64
277#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
278#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
279#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
280
281#elif CONFIG_SYS_USE_SPIFLASH
282#define CONFIG_SPL_SPI_SUPPORT
283#define CONFIG_SPL_SPI_FLASH_SUPPORT
284#define CONFIG_SPL_SPI_LOAD
285#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
286
287#endif
288
Bo Shenf7fa2f32012-07-05 17:21:46 +0000289#endif