| Angelo Dureghello | b5867b1 | 2019-03-13 21:46:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | compatible = "fsl,mcf5271"; |
| 8 | |
| 9 | aliases { |
| 10 | serial0 = &uart0; |
| Angelo Durgehello | 04e5dd5 | 2019-11-15 23:54:12 +0100 | [diff] [blame] | 11 | fec0 = &fec0; |
| Angelo Dureghello | b5867b1 | 2019-03-13 21:46:41 +0100 | [diff] [blame] | 12 | }; |
| 13 | |
| 14 | soc { |
| 15 | compatible = "simple-bus"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | ipsbar: ipsbar@4000000 { |
| 20 | compatible = "simple-bus"; |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <1>; |
| 23 | ranges = <0x00000000 0x40000000 0x40000000>; |
| 24 | reg = <0x40000000 0x40000000>; |
| 25 | |
| 26 | uart0: uart@200 { |
| 27 | compatible = "fsl,mcf-uart"; |
| 28 | reg = <0x200 0x40>; |
| 29 | status = "disabled"; |
| 30 | }; |
| 31 | |
| 32 | uart1: uart@240 { |
| 33 | compatible = "fsl,mcf-uart"; |
| 34 | reg = <0x240 0x40>; |
| 35 | status = "disabled"; |
| 36 | }; |
| 37 | |
| 38 | uart2: uart@280 { |
| 39 | compatible = "fsl,mcf-uart"; |
| 40 | reg = <0x280 0x40>; |
| 41 | status = "disabled"; |
| 42 | }; |
| Angelo Durgehello | 04e5dd5 | 2019-11-15 23:54:12 +0100 | [diff] [blame] | 43 | |
| 44 | fec0: ethernet@1000 { |
| 45 | compatible = "fsl,mcf-fec"; |
| 46 | reg = <0x1000 0x400>; |
| 47 | mii-base = <0>; |
| 48 | max-speed = <100>; |
| 49 | timeout-loop = <50000>; |
| 50 | status = "disabled"; |
| 51 | }; |
| Angelo Dureghello | 96283b8 | 2023-04-05 00:59:27 +0200 | [diff] [blame^] | 52 | |
| 53 | i2c0: i2c@300 { |
| 54 | compatible = "fsl-i2c"; |
| 55 | #address-cells=<1>; |
| 56 | #size-cells=<0>; |
| 57 | cell-index = <0>; |
| 58 | reg = <0x300 0x14>; |
| 59 | clock-frequency = <100000>; |
| 60 | status = "disabled"; |
| 61 | }; |
| Angelo Dureghello | b5867b1 | 2019-03-13 21:46:41 +0100 | [diff] [blame] | 62 | }; |
| 63 | }; |
| 64 | }; |