Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #include <common.h> |
Stefan Roese | c25dd8f | 2007-08-23 11:02:37 +0200 | [diff] [blame] | 22 | #include <command.h> |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 23 | #include <ppc440.h> |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 24 | #include <asm/processor.h> |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 25 | #include <asm/gpio.h> |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 26 | #include <asm/io.h> |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 27 | |
| 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
| 30 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
| 31 | |
Stefan Roese | 3ad6387 | 2007-08-21 16:27:57 +0200 | [diff] [blame] | 32 | ulong flash_get_size(ulong base, int banknum); |
| 33 | int misc_init_r_kbd(void); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 34 | |
| 35 | int board_early_init_f(void) |
| 36 | { |
| 37 | u32 sdr0_pfc1, sdr0_pfc2; |
| 38 | u32 reg; |
| 39 | |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 40 | /* PLB Write pipelining disabled. Denali Core workaround */ |
| 41 | mtdcr(plb0_acr, 0xDE000000); |
| 42 | mtdcr(plb1_acr, 0xDE000000); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 43 | |
| 44 | /*-------------------------------------------------------------------- |
| 45 | * Setup the interrupt controller polarities, triggers, etc. |
| 46 | *-------------------------------------------------------------------*/ |
| 47 | mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ |
| 48 | mtdcr(uic0er, 0x00000000); /* disable all */ |
| 49 | mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ |
Stefan Roese | aedf5bd | 2007-07-24 07:20:09 +0200 | [diff] [blame] | 50 | mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ |
| 51 | mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 52 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
| 53 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
| 54 | |
| 55 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 56 | mtdcr(uic1er, 0x00000000); /* disable all */ |
| 57 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
Stefan Roese | aedf5bd | 2007-07-24 07:20:09 +0200 | [diff] [blame] | 58 | mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ |
| 59 | mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 60 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
| 61 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 62 | |
| 63 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
| 64 | mtdcr(uic2er, 0x00000000); /* disable all */ |
| 65 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ |
| 66 | mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ |
Stefan Roese | aedf5bd | 2007-07-24 07:20:09 +0200 | [diff] [blame] | 67 | mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 68 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
Stefan Roese | aedf5bd | 2007-07-24 07:20:09 +0200 | [diff] [blame] | 69 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 70 | |
| 71 | /* Trace Pins are disabled. SDR0_PFC0 Register */ |
| 72 | mtsdr(SDR0_PFC0, 0x0); |
| 73 | |
| 74 | /* select Ethernet pins */ |
| 75 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
| 76 | /* SMII via ZMII */ |
| 77 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
| 78 | SDR0_PFC1_SELECT_CONFIG_6; |
| 79 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
| 80 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
| 81 | SDR0_PFC2_SELECT_CONFIG_6; |
| 82 | |
| 83 | /* enable SPI (SCP) */ |
| 84 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; |
| 85 | |
| 86 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
| 87 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
| 88 | |
| 89 | mtsdr(SDR0_PFC4, 0x80000000); |
| 90 | |
| 91 | /* PCI arbiter disabled */ |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 92 | /* PCI Host Configuration disbaled */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 93 | mfsdr(sdr_pci0, reg); |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 94 | reg = 0; |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 95 | mtsdr(sdr_pci0, 0x00000000 | reg); |
| 96 | |
| 97 | gpio_write_bit(CFG_GPIO_FLASH_WP, 1); |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | /*---------------------------------------------------------------------------+ |
| 103 | | misc_init_r. |
| 104 | +---------------------------------------------------------------------------*/ |
| 105 | int misc_init_r(void) |
| 106 | { |
| 107 | u32 pbcr; |
| 108 | int size_val = 0; |
| 109 | u32 reg; |
| 110 | unsigned long usb2d0cr = 0; |
| 111 | unsigned long usb2phy0cr, usb2h0cr = 0; |
| 112 | unsigned long sdr0_pfc1; |
| 113 | |
| 114 | /* |
| 115 | * FLASH stuff... |
| 116 | */ |
| 117 | |
| 118 | /* Re-do sizing to get full correct info */ |
| 119 | |
| 120 | /* adjust flash start and offset */ |
| 121 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 122 | gd->bd->bi_flashoffset = 0; |
| 123 | |
| 124 | mfebc(pb0cr, pbcr); |
| 125 | switch (gd->bd->bi_flashsize) { |
| 126 | case 1 << 20: |
| 127 | size_val = 0; |
| 128 | break; |
| 129 | case 2 << 20: |
| 130 | size_val = 1; |
| 131 | break; |
| 132 | case 4 << 20: |
| 133 | size_val = 2; |
| 134 | break; |
| 135 | case 8 << 20: |
| 136 | size_val = 3; |
| 137 | break; |
| 138 | case 16 << 20: |
| 139 | size_val = 4; |
| 140 | break; |
| 141 | case 32 << 20: |
| 142 | size_val = 5; |
| 143 | break; |
| 144 | case 64 << 20: |
| 145 | size_val = 6; |
| 146 | break; |
| 147 | case 128 << 20: |
| 148 | size_val = 7; |
| 149 | break; |
| 150 | } |
| 151 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
| 152 | mtebc(pb0cr, pbcr); |
| 153 | |
| 154 | /* |
| 155 | * Re-check to get correct base address |
| 156 | */ |
| 157 | flash_get_size(gd->bd->bi_flashstart, 0); |
| 158 | |
| 159 | /* Monitor protection ON by default */ |
| 160 | (void)flash_protect(FLAG_PROTECT_SET, |
| 161 | -CFG_MONITOR_LEN, |
| 162 | 0xffffffff, |
Stefan Roese | 9f24a80 | 2007-07-24 09:52:52 +0200 | [diff] [blame] | 163 | &flash_info[1]); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 164 | |
| 165 | /* Env protection ON by default */ |
| 166 | (void)flash_protect(FLAG_PROTECT_SET, |
| 167 | CFG_ENV_ADDR_REDUND, |
| 168 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, |
Stefan Roese | 9f24a80 | 2007-07-24 09:52:52 +0200 | [diff] [blame] | 169 | &flash_info[1]); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 170 | |
| 171 | /* |
| 172 | * USB suff... |
| 173 | */ |
| 174 | /* SDR Setting */ |
| 175 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
| 176 | mfsdr(SDR0_USB0, usb2d0cr); |
| 177 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 178 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
| 179 | |
| 180 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
| 181 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ |
| 182 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
| 183 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ |
| 184 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
| 185 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
| 186 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
| 187 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
| 188 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
| 189 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
| 190 | |
| 191 | /* An 8-bit/60MHz interface is the only possible alternative |
| 192 | when connecting the Device to the PHY */ |
| 193 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
| 194 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ |
| 195 | |
| 196 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
| 197 | mtsdr(SDR0_USB0, usb2d0cr); |
| 198 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 199 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
| 200 | |
| 201 | /* |
| 202 | * Clear resets |
| 203 | */ |
| 204 | udelay (1000); |
| 205 | mtsdr(SDR0_SRST1, 0x00000000); |
| 206 | udelay (1000); |
| 207 | mtsdr(SDR0_SRST0, 0x00000000); |
| 208 | |
| 209 | printf("USB: Host(int phy) Device(ext phy)\n"); |
| 210 | |
| 211 | /* |
| 212 | * Clear PLB4A0_ACR[WRP] |
| 213 | * This fix will make the MAL burst disabling patch for the Linux |
| 214 | * EMAC driver obsolete. |
| 215 | */ |
| 216 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; |
| 217 | mtdcr(plb4_acr, reg); |
| 218 | |
| 219 | /* |
| 220 | * Reset Lime controller |
| 221 | */ |
| 222 | gpio_write_bit(CFG_GPIO_LIME_S, 1); |
| 223 | udelay(500); |
| 224 | gpio_write_bit(CFG_GPIO_LIME_RST, 1); |
| 225 | |
Anatolij Gustschin | b66091d | 2007-07-26 15:08:01 +0200 | [diff] [blame] | 226 | /* Lime memory clock adjusted to 100MHz */ |
| 227 | out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 228 | /* Wait untill time expired. Because of requirements in lime manual */ |
| 229 | udelay(300); |
| 230 | /* Write lime controller memory parameters */ |
| 231 | out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); |
| 232 | |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 233 | /* |
| 234 | * Reset PHY's |
| 235 | */ |
| 236 | gpio_write_bit(CFG_GPIO_PHY0_RST, 0); |
| 237 | gpio_write_bit(CFG_GPIO_PHY1_RST, 0); |
| 238 | udelay(100); |
| 239 | gpio_write_bit(CFG_GPIO_PHY0_RST, 1); |
| 240 | gpio_write_bit(CFG_GPIO_PHY1_RST, 1); |
| 241 | |
Anatolij Gustschin | b66091d | 2007-07-26 15:08:01 +0200 | [diff] [blame] | 242 | /* |
| 243 | * Init display controller |
| 244 | */ |
| 245 | /* Setup dot clock (internal PLL, division rate 1/16) */ |
| 246 | out_be32((void *)0xc1fd0100, 0x00000f00); |
| 247 | |
| 248 | /* Lime L0 init (16 bpp, 640x480) */ |
| 249 | out_be32((void *)0xc1fd0020, 0x801401df); |
| 250 | out_be32((void *)0xc1fd0024, 0x0); |
| 251 | out_be32((void *)0xc1fd0028, 0x0); |
| 252 | out_be32((void *)0xc1fd002c, 0x0); |
| 253 | out_be32((void *)0xc1fd0110, 0x0); |
| 254 | out_be32((void *)0xc1fd0114, 0x0); |
| 255 | out_be32((void *)0xc1fd0118, 0x01df0280); |
| 256 | |
| 257 | /* Display timing init */ |
| 258 | out_be32((void *)0xc1fd0004, 0x031f0000); |
| 259 | out_be32((void *)0xc1fd0008, 0x027f027f); |
| 260 | out_be32((void *)0xc1fd000c, 0x015f028f); |
| 261 | out_be32((void *)0xc1fd0010, 0x020c0000); |
| 262 | out_be32((void *)0xc1fd0014, 0x01df01ea); |
| 263 | out_be32((void *)0xc1fd0018, 0x0); |
| 264 | out_be32((void *)0xc1fd001c, 0x01e00280); |
| 265 | |
| 266 | #if 1 |
| 267 | /* |
| 268 | * Clear framebuffer using Lime's drawing engine |
| 269 | * (draw blue rect. with white border around it) |
| 270 | */ |
| 271 | /* Setup mode and fbbase, xres, fg, bg */ |
| 272 | out_be32((void *)0xc1ff0420, 0x8300); |
| 273 | out_be32((void *)0xc1ff0440, 0x0000); |
| 274 | out_be32((void *)0xc1ff0444, 0x0280); |
| 275 | out_be32((void *)0xc1ff0480, 0x7fff); |
| 276 | out_be32((void *)0xc1ff0484, 0x0000); |
| 277 | /* Reset clipping rectangle */ |
| 278 | out_be32((void *)0xc1ff0454, 0x0000); |
| 279 | out_be32((void *)0xc1ff0458, 0x0280); |
| 280 | out_be32((void *)0xc1ff045c, 0x0000); |
| 281 | out_be32((void *)0xc1ff0460, 0x01e0); |
| 282 | /* Draw white rect. */ |
| 283 | out_be32((void *)0xc1ff04a0, 0x09410000); |
| 284 | out_be32((void *)0xc1ff04a0, 0x00000000); |
| 285 | out_be32((void *)0xc1ff04a0, 0x01e00280); |
| 286 | udelay(2000); |
| 287 | /* Draw blue rect. */ |
| 288 | out_be32((void *)0xc1ff0480, 0x001f); |
| 289 | out_be32((void *)0xc1ff04a0, 0x09410000); |
| 290 | out_be32((void *)0xc1ff04a0, 0x00010001); |
| 291 | out_be32((void *)0xc1ff04a0, 0x01de027e); |
| 292 | #endif |
| 293 | /* Display enable, L0 layer */ |
| 294 | out_be32((void *)0xc1fd0100, 0x80010f00); |
| 295 | |
| 296 | /* TFT-LCD enable - PWM duty, lamp on */ |
| 297 | out_be32((void *)0xc4000024, 0x64); |
| 298 | out_be32((void *)0xc4000020, 0x701); |
| 299 | |
Stefan Roese | 3ad6387 | 2007-08-21 16:27:57 +0200 | [diff] [blame] | 300 | /* |
| 301 | * Init matrix keyboard |
| 302 | */ |
| 303 | misc_init_r_kbd(); |
| 304 | |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | int checkboard(void) |
| 309 | { |
| 310 | char *s = getenv("serial#"); |
| 311 | |
| 312 | printf("Board: lwmon5"); |
| 313 | |
| 314 | if (s != NULL) { |
| 315 | puts(", serial# "); |
| 316 | puts(s); |
| 317 | } |
| 318 | putc('\n'); |
| 319 | |
| 320 | return (0); |
| 321 | } |
| 322 | |
| 323 | #if defined(CFG_DRAM_TEST) |
| 324 | int testdram(void) |
| 325 | { |
| 326 | unsigned long *mem = (unsigned long *)0; |
| 327 | const unsigned long kend = (1024 / sizeof(unsigned long)); |
| 328 | unsigned long k, n; |
| 329 | |
| 330 | mtmsr(0); |
| 331 | |
| 332 | for (k = 0; k < CFG_MBYTES_SDRAM; |
| 333 | ++k, mem += (1024 / sizeof(unsigned long))) { |
| 334 | if ((k & 1023) == 0) { |
| 335 | printf("%3d MB\r", k / 1024); |
| 336 | } |
| 337 | |
| 338 | memset(mem, 0xaaaaaaaa, 1024); |
| 339 | for (n = 0; n < kend; ++n) { |
| 340 | if (mem[n] != 0xaaaaaaaa) { |
| 341 | printf("SDRAM test fails at: %08x\n", |
| 342 | (uint) & mem[n]); |
| 343 | return 1; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | memset(mem, 0x55555555, 1024); |
| 348 | for (n = 0; n < kend; ++n) { |
| 349 | if (mem[n] != 0x55555555) { |
| 350 | printf("SDRAM test fails at: %08x\n", |
| 351 | (uint) & mem[n]); |
| 352 | return 1; |
| 353 | } |
| 354 | } |
| 355 | } |
| 356 | printf("SDRAM test passes\n"); |
| 357 | return 0; |
| 358 | } |
| 359 | #endif |
| 360 | |
| 361 | /************************************************************************* |
| 362 | * pci_pre_init |
| 363 | * |
| 364 | * This routine is called just prior to registering the hose and gives |
| 365 | * the board the opportunity to check things. Returning a value of zero |
| 366 | * indicates that things are bad & PCI initialization should be aborted. |
| 367 | * |
| 368 | * Different boards may wish to customize the pci controller structure |
| 369 | * (add regions, override default access routines, etc) or perform |
| 370 | * certain pre-initialization actions. |
| 371 | * |
| 372 | ************************************************************************/ |
Stefan Roese | 466fff1 | 2007-06-25 15:57:39 +0200 | [diff] [blame] | 373 | #if defined(CONFIG_PCI) |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 374 | int pci_pre_init(struct pci_controller *hose) |
| 375 | { |
| 376 | unsigned long addr; |
| 377 | |
| 378 | /*-------------------------------------------------------------------------+ |
| 379 | | Set priority for all PLB3 devices to 0. |
| 380 | | Set PLB3 arbiter to fair mode. |
| 381 | +-------------------------------------------------------------------------*/ |
| 382 | mfsdr(sdr_amp1, addr); |
| 383 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
| 384 | addr = mfdcr(plb3_acr); |
| 385 | mtdcr(plb3_acr, addr | 0x80000000); |
| 386 | |
| 387 | /*-------------------------------------------------------------------------+ |
| 388 | | Set priority for all PLB4 devices to 0. |
| 389 | +-------------------------------------------------------------------------*/ |
| 390 | mfsdr(sdr_amp0, addr); |
| 391 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
| 392 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
| 393 | mtdcr(plb4_acr, addr); |
| 394 | |
| 395 | /*-------------------------------------------------------------------------+ |
| 396 | | Set Nebula PLB4 arbiter to fair mode. |
| 397 | +-------------------------------------------------------------------------*/ |
| 398 | /* Segment0 */ |
| 399 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
| 400 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
| 401 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
| 402 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
| 403 | mtdcr(plb0_acr, addr); |
| 404 | |
| 405 | /* Segment1 */ |
| 406 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
| 407 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
| 408 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
| 409 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
| 410 | mtdcr(plb1_acr, addr); |
| 411 | |
| 412 | return 1; |
| 413 | } |
Stefan Roese | 466fff1 | 2007-06-25 15:57:39 +0200 | [diff] [blame] | 414 | #endif /* defined(CONFIG_PCI) */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 415 | |
| 416 | /************************************************************************* |
| 417 | * pci_target_init |
| 418 | * |
| 419 | * The bootstrap configuration provides default settings for the pci |
| 420 | * inbound map (PIM). But the bootstrap config choices are limited and |
| 421 | * may not be sufficient for a given board. |
| 422 | * |
| 423 | ************************************************************************/ |
| 424 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
| 425 | void pci_target_init(struct pci_controller *hose) |
| 426 | { |
| 427 | /*--------------------------------------------------------------------------+ |
| 428 | * Set up Direct MMIO registers |
| 429 | *--------------------------------------------------------------------------*/ |
| 430 | /*--------------------------------------------------------------------------+ |
| 431 | | PowerPC440EPX PCI Master configuration. |
| 432 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. |
| 433 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
| 434 | | Use byte reversed out routines to handle endianess. |
| 435 | | Make this region non-prefetchable. |
| 436 | +--------------------------------------------------------------------------*/ |
| 437 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 438 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
| 439 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
| 440 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 441 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 442 | |
| 443 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 444 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
| 445 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
| 446 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 447 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 448 | |
| 449 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
| 450 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
| 451 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
| 452 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
| 453 | |
| 454 | /*--------------------------------------------------------------------------+ |
| 455 | * Set up Configuration registers |
| 456 | *--------------------------------------------------------------------------*/ |
| 457 | |
| 458 | /* Program the board's subsystem id/vendor id */ |
| 459 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
| 460 | CFG_PCI_SUBSYS_VENDORID); |
| 461 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
| 462 | |
| 463 | /* Configure command register as bus master */ |
| 464 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 465 | |
| 466 | /* 240nS PCI clock */ |
| 467 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
| 468 | |
| 469 | /* No error reporting */ |
| 470 | pci_write_config_word(0, PCI_ERREN, 0); |
| 471 | |
| 472 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
| 473 | |
| 474 | } |
| 475 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
| 476 | |
| 477 | /************************************************************************* |
| 478 | * pci_master_init |
| 479 | * |
| 480 | ************************************************************************/ |
| 481 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
| 482 | void pci_master_init(struct pci_controller *hose) |
| 483 | { |
| 484 | unsigned short temp_short; |
| 485 | |
| 486 | /*--------------------------------------------------------------------------+ |
| 487 | | Write the PowerPC440 EP PCI Configuration regs. |
| 488 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
| 489 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). |
| 490 | +--------------------------------------------------------------------------*/ |
| 491 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
| 492 | pci_write_config_word(0, PCI_COMMAND, |
| 493 | temp_short | PCI_COMMAND_MASTER | |
| 494 | PCI_COMMAND_MEMORY); |
| 495 | } |
| 496 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
| 497 | |
| 498 | /************************************************************************* |
| 499 | * is_pci_host |
| 500 | * |
| 501 | * This routine is called to determine if a pci scan should be |
| 502 | * performed. With various hardware environments (especially cPCI and |
| 503 | * PPMC) it's insufficient to depend on the state of the arbiter enable |
| 504 | * bit in the strap register, or generic host/adapter assumptions. |
| 505 | * |
| 506 | * Rather than hard-code a bad assumption in the general 440 code, the |
| 507 | * 440 pci code requires the board to decide at runtime. |
| 508 | * |
| 509 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
| 510 | * |
| 511 | * |
| 512 | ************************************************************************/ |
| 513 | #if defined(CONFIG_PCI) |
| 514 | int is_pci_host(struct pci_controller *hose) |
| 515 | { |
| 516 | /* Cactus is always configured as host. */ |
| 517 | return (1); |
| 518 | } |
| 519 | #endif /* defined(CONFIG_PCI) */ |
| 520 | |
| 521 | void hw_watchdog_reset(void) |
| 522 | { |
| 523 | int val; |
| 524 | |
| 525 | /* |
| 526 | * Toggle watchdog output |
| 527 | */ |
| 528 | val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; |
| 529 | gpio_write_bit(CFG_GPIO_WATCHDOG, val); |
| 530 | } |
Stefan Roese | c25dd8f | 2007-08-23 11:02:37 +0200 | [diff] [blame] | 531 | |
| 532 | int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 533 | { |
| 534 | if (argc < 2) { |
| 535 | printf("Usage:\n%s\n", cmdtp->usage); |
| 536 | return 1; |
| 537 | } |
| 538 | |
| 539 | if ((strcmp(argv[1], "on") == 0)) { |
| 540 | gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); |
| 541 | } else if ((strcmp(argv[1], "off") == 0)) { |
| 542 | gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); |
| 543 | } else { |
| 544 | printf("Usage:\n%s\n", cmdtp->usage); |
| 545 | return 1; |
| 546 | } |
| 547 | |
| 548 | |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | U_BOOT_CMD( |
| 553 | eepromwp, 2, 0, do_eeprom_wp, |
| 554 | "eepromwp- eeprom write protect off/on\n", |
| 555 | "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n" |
| 556 | ); |