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Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09001/*
Yoshihiro Shimoda26235092012-06-26 16:38:06 +00002 * sh_eth.c - Driver for Renesas ethernet controler.
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09003 *
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +09004 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09006 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <config.h>
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090027#include <netdev.h>
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +090028#include <miiphy.h>
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090029#include <asm/errno.h>
30#include <asm/io.h>
31
32#include "sh_eth.h"
33
34#ifndef CONFIG_SH_ETHER_USE_PORT
35# error "Please define CONFIG_SH_ETHER_USE_PORT"
36#endif
37#ifndef CONFIG_SH_ETHER_PHY_ADDR
38# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
39#endif
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +090040#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
41#define flush_cache_wback(addr, len) \
42 dcache_wback_range((u32)addr, (u32)(addr + len - 1))
43#else
44#define flush_cache_wback(...)
45#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090046
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +090047#define TIMEOUT_CNT 1000
48
Joe Hershberger10cbe3b2012-05-22 18:36:19 +000049int sh_eth_send(struct eth_device *dev, void *packet, int len)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090050{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090051 struct sh_eth_dev *eth = dev->priv;
52 int port = eth->port, ret = 0, timeout;
53 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090054
55 if (!packet || len > 0xffff) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090056 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
57 ret = -EINVAL;
58 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090059 }
60
61 /* packet must be a 4 byte boundary */
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +000062 if ((int)packet & 3) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090063 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
64 ret = -EFAULT;
65 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090066 }
67
68 /* Update tx descriptor */
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +090069 flush_cache_wback(packet, len);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090070 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
71 port_info->tx_desc_cur->td1 = len << 16;
72 /* Must preserve the end of descriptor list indication */
73 if (port_info->tx_desc_cur->td0 & TD_TDLE)
74 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
75 else
76 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
77
78 /* Restart the transmitter if disabled */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +000079 if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
80 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090081
82 /* Wait until packet is transmitted */
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +090083 timeout = TIMEOUT_CNT;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090084 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
85 udelay(100);
86
87 if (timeout < 0) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090088 printf(SHETHER_NAME ": transmit timeout\n");
89 ret = -ETIMEDOUT;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090090 goto err;
91 }
92
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090093 port_info->tx_desc_cur++;
94 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
95 port_info->tx_desc_cur = port_info->tx_desc_base;
96
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090097err:
98 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090099}
100
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900101int sh_eth_recv(struct eth_device *dev)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900102{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900103 struct sh_eth_dev *eth = dev->priv;
104 int port = eth->port, len = 0;
105 struct sh_eth_info *port_info = &eth->port_info[port];
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000106 uchar *packet;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900107
108 /* Check if the rx descriptor is ready */
109 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
110 /* Check for errors */
111 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
112 len = port_info->rx_desc_cur->rd1 & 0xffff;
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000113 packet = (uchar *)
114 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900115 NetReceive(packet, len);
116 }
117
118 /* Make current descriptor available again */
119 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
120 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
121 else
122 port_info->rx_desc_cur->rd0 = RD_RACT;
123
124 /* Point to the next descriptor */
125 port_info->rx_desc_cur++;
126 if (port_info->rx_desc_cur >=
127 port_info->rx_desc_base + NUM_RX_DESC)
128 port_info->rx_desc_cur = port_info->rx_desc_base;
129 }
130
131 /* Restart the receiver if disabled */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000132 if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
133 sh_eth_write(eth, EDRRR_R, EDRRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900134
135 return len;
136}
137
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900138static int sh_eth_reset(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900139{
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000140#if defined(SH_ETH_TYPE_GETHER)
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900141 int ret = 0, i;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900142
143 /* Start e-dmac transmitter and receiver */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000144 sh_eth_write(eth, EDSR_ENALL, EDSR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900145
146 /* Perform a software reset and wait for it to complete */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000147 sh_eth_write(eth, EDMR_SRST, EDMR);
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +0900148 for (i = 0; i < TIMEOUT_CNT ; i++) {
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000149 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900150 break;
151 udelay(1000);
152 }
153
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +0900154 if (i == TIMEOUT_CNT) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900155 printf(SHETHER_NAME ": Software reset timeout\n");
156 ret = -EIO;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900157 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900158
159 return ret;
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900160#else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000161 sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900162 udelay(3000);
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000163 sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900164
165 return 0;
166#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900167}
168
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900169static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900170{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900171 int port = eth->port, i, ret = 0;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900172 u32 tmp_addr;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900173 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900174 struct tx_desc_s *cur_tx_desc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900175
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900176 /*
177 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
178 */
179 port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900180 sizeof(struct tx_desc_s) +
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900181 TX_DESC_SIZE - 1);
182 if (!port_info->tx_desc_malloc) {
183 printf(SHETHER_NAME ": malloc failed\n");
184 ret = -ENOMEM;
185 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900186 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900187
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900188 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
189 ~(TX_DESC_SIZE - 1));
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +0900190 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900191 /* Make sure we use a P2 address (non-cacheable) */
192 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900193 port_info->tx_desc_cur = port_info->tx_desc_base;
194
195 /* Initialize all descriptors */
196 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
197 cur_tx_desc++, i++) {
198 cur_tx_desc->td0 = 0x00;
199 cur_tx_desc->td1 = 0x00;
200 cur_tx_desc->td2 = 0x00;
201 }
202
203 /* Mark the end of the descriptors */
204 cur_tx_desc--;
205 cur_tx_desc->td0 |= TD_TDLE;
206
207 /* Point the controller to the tx descriptor list. Must use physical
208 addresses */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000209 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000210#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000211 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
212 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
213 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900214#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900215
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900216err:
217 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900218}
219
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900220static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900221{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900222 int port = eth->port, i , ret = 0;
223 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900224 struct rx_desc_s *cur_rx_desc;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900225 u32 tmp_addr;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900226 u8 *rx_buf;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900227
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900228 /*
229 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
230 */
231 port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900232 sizeof(struct rx_desc_s) +
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900233 RX_DESC_SIZE - 1);
234 if (!port_info->rx_desc_malloc) {
235 printf(SHETHER_NAME ": malloc failed\n");
236 ret = -ENOMEM;
237 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900238 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900239
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900240 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
241 ~(RX_DESC_SIZE - 1));
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +0900242 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900243 /* Make sure we use a P2 address (non-cacheable) */
244 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
245
246 port_info->rx_desc_cur = port_info->rx_desc_base;
247
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900248 /*
249 * Allocate rx data buffers. They must be 32 bytes aligned and in
250 * P2 area
251 */
252 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
253 if (!port_info->rx_buf_malloc) {
254 printf(SHETHER_NAME ": malloc failed\n");
255 ret = -ENOMEM;
256 goto err_buf_malloc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900257 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900258
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900259 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
260 ~(32 - 1));
261 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
262
263 /* Initialize all descriptors */
264 for (cur_rx_desc = port_info->rx_desc_base,
265 rx_buf = port_info->rx_buf_base, i = 0;
266 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
267 cur_rx_desc->rd0 = RD_RACT;
268 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
269 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
270 }
271
272 /* Mark the end of the descriptors */
273 cur_rx_desc--;
274 cur_rx_desc->rd0 |= RD_RDLE;
275
276 /* Point the controller to the rx descriptor list */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000277 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000278#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000279 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
280 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
281 sh_eth_write(eth, RDFFR_RDLF, RDFFR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900282#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900283
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900284 return ret;
285
286err_buf_malloc:
287 free(port_info->rx_desc_malloc);
288 port_info->rx_desc_malloc = NULL;
289
290err:
291 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900292}
293
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900294static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900295{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900296 int port = eth->port;
297 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900298
299 if (port_info->tx_desc_malloc) {
300 free(port_info->tx_desc_malloc);
301 port_info->tx_desc_malloc = NULL;
302 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900303}
304
305static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
306{
307 int port = eth->port;
308 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900309
310 if (port_info->rx_desc_malloc) {
311 free(port_info->rx_desc_malloc);
312 port_info->rx_desc_malloc = NULL;
313 }
314
315 if (port_info->rx_buf_malloc) {
316 free(port_info->rx_buf_malloc);
317 port_info->rx_buf_malloc = NULL;
318 }
319}
320
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900321static int sh_eth_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900322{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900323 int ret = 0;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900324
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900325 ret = sh_eth_tx_desc_init(eth);
326 if (ret)
327 goto err_tx_init;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900328
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900329 ret = sh_eth_rx_desc_init(eth);
330 if (ret)
331 goto err_rx_init;
332
333 return ret;
334err_rx_init:
335 sh_eth_tx_desc_free(eth);
336
337err_tx_init:
338 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900339}
340
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900341static int sh_eth_phy_config(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900342{
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900343 int port = eth->port, ret = 0;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900344 struct sh_eth_info *port_info = &eth->port_info[port];
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900345 struct eth_device *dev = port_info->dev;
346 struct phy_device *phydev;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900347
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000348 phydev = phy_connect(
349 miiphy_get_dev_by_name(dev->name),
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000350 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900351 port_info->phydev = phydev;
352 phy_config(phydev);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900353
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900354 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900355}
356
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900357static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900358{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900359 int port = eth->port, ret = 0;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900360 u32 val;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900361 struct sh_eth_info *port_info = &eth->port_info[port];
Mike Frysingerc527ce92009-02-11 19:14:09 -0500362 struct eth_device *dev = port_info->dev;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900363 struct phy_device *phy;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900364
365 /* Configure e-dmac registers */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000366 sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
367 EDMR);
368 sh_eth_write(eth, 0, EESIPR);
369 sh_eth_write(eth, 0, TRSCER);
370 sh_eth_write(eth, 0, TFTR);
371 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
372 sh_eth_write(eth, RMCR_RST, RMCR);
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000373#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000374 sh_eth_write(eth, 0, RPADIR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900375#endif
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000376 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900377
378 /* Configure e-mac registers */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000379 sh_eth_write(eth, 0, ECSIPR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900380
381 /* Set Mac address */
Mike Frysingerc527ce92009-02-11 19:14:09 -0500382 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
383 dev->enetaddr[2] << 8 | dev->enetaddr[3];
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000384 sh_eth_write(eth, val, MAHR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900385
Mike Frysingerc527ce92009-02-11 19:14:09 -0500386 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000387 sh_eth_write(eth, val, MALR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900388
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000389 sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000390#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000391 sh_eth_write(eth, 0, PIPR);
392 sh_eth_write(eth, APR_AP, APR);
393 sh_eth_write(eth, MPR_MP, MPR);
394 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900395#endif
396
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000397#if defined(CONFIG_CPU_SH7734)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000398 sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000399#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900400 /* Configure phy */
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900401 ret = sh_eth_phy_config(eth);
402 if (ret) {
Nobuhiro Iwamatsu88a4c2e2009-06-25 16:33:04 +0900403 printf(SHETHER_NAME ": phy config timeout\n");
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900404 goto err_phy_cfg;
405 }
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900406 phy = port_info->phydev;
Timur Tabi11af8d62012-07-09 08:52:43 +0000407 ret = phy_startup(phy);
408 if (ret) {
409 printf(SHETHER_NAME ": phy startup failure\n");
410 return ret;
411 }
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900412
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900413 val = 0;
414
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900415 /* Set the transfer speed */
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900416 if (phy->speed == 100) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900417 printf(SHETHER_NAME ": 100Base/");
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000418#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000419 sh_eth_write(eth, GECMR_100B, GECMR);
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900420#elif defined(CONFIG_CPU_SH7757)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000421 sh_eth_write(eth, 1, RTRATE);
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900422#elif defined(CONFIG_CPU_SH7724)
423 val = ECMR_RTM;
424#endif
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900425 } else if (phy->speed == 10) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900426 printf(SHETHER_NAME ": 10Base/");
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000427#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000428 sh_eth_write(eth, GECMR_10B, GECMR);
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900429#elif defined(CONFIG_CPU_SH7757)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000430 sh_eth_write(eth, 0, RTRATE);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900431#endif
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900432 }
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000433#if defined(SH_ETH_TYPE_GETHER)
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000434 else if (phy->speed == 1000) {
435 printf(SHETHER_NAME ": 1000Base/");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000436 sh_eth_write(eth, GECMR_1000B, GECMR);
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000437 }
438#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900439
440 /* Check if full duplex mode is supported by the phy */
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900441 if (phy->duplex) {
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900442 printf("Full\n");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000443 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
444 ECMR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900445 } else {
446 printf("Half\n");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000447 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900448 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900449
450 return ret;
451
452err_phy_cfg:
453 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900454}
455
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900456static void sh_eth_start(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900457{
458 /*
459 * Enable the e-dmac receiver only. The transmitter will be enabled when
460 * we have something to transmit
461 */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000462 sh_eth_write(eth, EDRRR_R, EDRRR);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900463}
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900464
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900465static void sh_eth_stop(struct sh_eth_dev *eth)
466{
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000467 sh_eth_write(eth, ~EDRRR_R, EDRRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900468}
469
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900470int sh_eth_init(struct eth_device *dev, bd_t *bd)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900471{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900472 int ret = 0;
473 struct sh_eth_dev *eth = dev->priv;
474
475 ret = sh_eth_reset(eth);
476 if (ret)
477 goto err;
478
479 ret = sh_eth_desc_init(eth);
480 if (ret)
481 goto err;
482
483 ret = sh_eth_config(eth, bd);
484 if (ret)
485 goto err_config;
486
487 sh_eth_start(eth);
488
489 return ret;
490
491err_config:
492 sh_eth_tx_desc_free(eth);
493 sh_eth_rx_desc_free(eth);
494
495err:
496 return ret;
497}
498
499void sh_eth_halt(struct eth_device *dev)
500{
501 struct sh_eth_dev *eth = dev->priv;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900502 sh_eth_stop(eth);
503}
504
505int sh_eth_initialize(bd_t *bd)
506{
507 int ret = 0;
508 struct sh_eth_dev *eth = NULL;
509 struct eth_device *dev = NULL;
510
511 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
512 if (!eth) {
513 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
514 ret = -ENOMEM;
515 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900516 }
517
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900518 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
519 if (!dev) {
520 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
521 ret = -ENOMEM;
522 goto err;
523 }
524 memset(dev, 0, sizeof(struct eth_device));
525 memset(eth, 0, sizeof(struct sh_eth_dev));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900526
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900527 eth->port = CONFIG_SH_ETHER_USE_PORT;
528 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
529
530 dev->priv = (void *)eth;
531 dev->iobase = 0;
532 dev->init = sh_eth_init;
533 dev->halt = sh_eth_halt;
534 dev->send = sh_eth_send;
535 dev->recv = sh_eth_recv;
536 eth->port_info[eth->port].dev = dev;
537
538 sprintf(dev->name, SHETHER_NAME);
539
540 /* Register Device to EtherNet subsystem */
541 eth_register(dev);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900542
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900543 bb_miiphy_buses[0].priv = eth;
544 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
545
Mike Frysingerc527ce92009-02-11 19:14:09 -0500546 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
547 puts("Please set MAC address\n");
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900548
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900549 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900550
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900551err:
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900552 if (dev)
553 free(dev);
554
555 if (eth)
556 free(eth);
557
558 printf(SHETHER_NAME ": Failed\n");
559 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900560}
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900561
562/******* for bb_miiphy *******/
563static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
564{
565 return 0;
566}
567
568static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
569{
570 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900571
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000572 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900573
574 return 0;
575}
576
577static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
578{
579 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900580
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000581 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900582
583 return 0;
584}
585
586static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
587{
588 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900589
590 if (v)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000591 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900592 else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000593 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900594
595 return 0;
596}
597
598static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
599{
600 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900601
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000602 *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900603
604 return 0;
605}
606
607static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
608{
609 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900610
611 if (v)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000612 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900613 else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000614 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900615
616 return 0;
617}
618
619static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
620{
621 udelay(10);
622
623 return 0;
624}
625
626struct bb_miiphy_bus bb_miiphy_buses[] = {
627 {
628 .name = "sh_eth",
629 .init = sh_eth_bb_init,
630 .mdio_active = sh_eth_bb_mdio_active,
631 .mdio_tristate = sh_eth_bb_mdio_tristate,
632 .set_mdio = sh_eth_bb_set_mdio,
633 .get_mdio = sh_eth_bb_get_mdio,
634 .set_mdc = sh_eth_bb_set_mdc,
635 .delay = sh_eth_bb_delay,
636 }
637};
638int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);