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Mike Frysingerbe853bf2008-10-06 04:16:47 -04001/*
Scott Jiangfea9b692014-11-13 15:30:53 +08002 * i2c.c - driver for ADI TWI/I2C
Mike Frysingerbe853bf2008-10-06 04:16:47 -04003 *
Scott Jiangfea9b692014-11-13 15:30:53 +08004 * Copyright (c) 2006-2014 Analog Devices Inc.
Mike Frysingerbe853bf2008-10-06 04:16:47 -04005 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
Simon Glass24b852a2015-11-08 23:47:45 -070010#include <console.h>
Mike Frysingerbe853bf2008-10-06 04:16:47 -040011#include <i2c.h>
12
Sonic Zhangd6a320d2014-01-28 13:53:34 +080013#include <asm/clock.h>
Scott Jiangfea9b692014-11-13 15:30:53 +080014#include <asm/twi.h>
Scott Jianga6be70f2014-11-13 15:30:54 +080015#include <asm/io.h>
Mike Frysingerbe853bf2008-10-06 04:16:47 -040016
Scott Jiangc4697032014-11-13 15:30:55 +080017static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
18
Mike Frysingerb5cebb42010-05-05 03:20:30 -040019/* Every register is 32bit aligned, but only 16bits in size */
20#define ureg(name) u16 name; u16 __pad_##name;
21struct twi_regs {
22 ureg(clkdiv);
23 ureg(control);
24 ureg(slave_ctl);
25 ureg(slave_stat);
26 ureg(slave_addr);
27 ureg(master_ctl);
28 ureg(master_stat);
29 ureg(master_addr);
30 ureg(int_stat);
31 ureg(int_mask);
32 ureg(fifo_ctl);
33 ureg(fifo_stat);
34 char __pad[0x50];
35 ureg(xmt_data8);
36 ureg(xmt_data16);
37 ureg(rcv_data8);
38 ureg(rcv_data16);
39};
40#undef ureg
41
Mike Frysingerb5cebb42010-05-05 03:20:30 -040042#ifdef TWI_CLKDIV
43#define TWI0_CLKDIV TWI_CLKDIV
Scott Jiangc4697032014-11-13 15:30:55 +080044# ifdef CONFIG_SYS_MAX_I2C_BUS
45# undef CONFIG_SYS_MAX_I2C_BUS
46# endif
47#define CONFIG_SYS_MAX_I2C_BUS 1
Mike Frysingerbe853bf2008-10-06 04:16:47 -040048#endif
Mike Frysinger08a1c622009-10-14 19:27:27 -040049
50/*
51 * The way speed is changed into duty often results in integer truncation
52 * with 50% duty, so we'll force rounding up to the next duty by adding 1
53 * to the max. In practice this will get us a speed of something like
54 * 385 KHz. The other limit is easy to handle as it is only 8 bits.
55 */
56#define I2C_SPEED_MAX 400000
57#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
58#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
59#define I2C_DUTY_MIN 0xff /* 8 bit limited */
60#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
61/* Note: duty is inverse of speed, so the comparisons below are correct */
62#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
Scott Jiangc4697032014-11-13 15:30:55 +080063# error "The I2C hardware can only operate 20KHz - 400KHz"
Mike Frysingerbe853bf2008-10-06 04:16:47 -040064#endif
65
66/* All transfers are described by this data structure */
Simon Glassfffff722015-02-05 21:41:33 -070067struct adi_i2c_msg {
Mike Frysingerbe853bf2008-10-06 04:16:47 -040068 u8 flags;
69#define I2C_M_COMBO 0x4
70#define I2C_M_STOP 0x2
71#define I2C_M_READ 0x1
72 int len; /* msg length */
73 u8 *buf; /* pointer to msg data */
74 int alen; /* addr length */
75 u8 *abuf; /* addr buffer */
76};
77
Mike Frysinger3814ea42009-10-14 19:27:26 -040078/* Allow msec timeout per ~byte transfer */
79#define I2C_TIMEOUT 10
80
Mike Frysingerbe853bf2008-10-06 04:16:47 -040081/**
82 * wait_for_completion - manage the actual i2c transfer
83 * @msg: the i2c msg
84 */
Simon Glassfffff722015-02-05 21:41:33 -070085static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
Mike Frysingerbe853bf2008-10-06 04:16:47 -040086{
Scott Jianga6be70f2014-11-13 15:30:54 +080087 u16 int_stat, ctl;
Mike Frysinger3814ea42009-10-14 19:27:26 -040088 ulong timebase = get_timer(0);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040089
Mike Frysinger3814ea42009-10-14 19:27:26 -040090 do {
Scott Jianga6be70f2014-11-13 15:30:54 +080091 int_stat = readw(&twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040092
93 if (int_stat & XMTSERV) {
Scott Jianga6be70f2014-11-13 15:30:54 +080094 writew(XMTSERV, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040095 if (msg->alen) {
Scott Jianga6be70f2014-11-13 15:30:54 +080096 writew(*(msg->abuf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040097 --msg->alen;
98 } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +080099 writew(*(msg->buf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400100 --msg->len;
101 } else {
Scott Jianga6be70f2014-11-13 15:30:54 +0800102 ctl = readw(&twi->master_ctl);
103 if (msg->flags & I2C_M_COMBO)
104 writew(ctl | RSTART | MDIR,
105 &twi->master_ctl);
106 else
107 writew(ctl | STOP, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400108 }
109 }
110 if (int_stat & RCVSERV) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800111 writew(RCVSERV, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400112 if (msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800113 *(msg->buf++) = readw(&twi->rcv_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400114 --msg->len;
115 } else if (msg->flags & I2C_M_STOP) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800116 ctl = readw(&twi->master_ctl);
117 writew(ctl | STOP, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400118 }
119 }
120 if (int_stat & MERR) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800121 writew(MERR, &twi->int_stat);
Mike Frysinger3814ea42009-10-14 19:27:26 -0400122 return msg->len;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400123 }
124 if (int_stat & MCOMP) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800125 writew(MCOMP, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400126 if (msg->flags & I2C_M_COMBO && msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800127 ctl = readw(&twi->master_ctl);
128 ctl = (ctl & ~RSTART) |
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400129 (min(msg->len, 0xff) << 6) | MEN | MDIR;
Scott Jianga6be70f2014-11-13 15:30:54 +0800130 writew(ctl, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400131 } else
132 break;
133 }
Mike Frysinger3814ea42009-10-14 19:27:26 -0400134
135 /* If we were able to do something, reset timeout */
136 if (int_stat)
137 timebase = get_timer(0);
138
139 } while (get_timer(timebase) < I2C_TIMEOUT);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400140
141 return msg->len;
142}
143
Scott Jiangc4697032014-11-13 15:30:55 +0800144static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
145 int alen, uint8_t *buffer, int len, uint8_t flags)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400146{
Scott Jiangc4697032014-11-13 15:30:55 +0800147 struct twi_regs *twi = i2c_get_base(adap);
Scott Jianga6be70f2014-11-13 15:30:54 +0800148 int ret;
149 u16 ctl;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400150 uchar addr_buffer[] = {
151 (addr >> 0),
152 (addr >> 8),
153 (addr >> 16),
154 };
Simon Glassfffff722015-02-05 21:41:33 -0700155 struct adi_i2c_msg msg = {
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400156 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
157 .buf = buffer,
158 .len = len,
159 .abuf = addr_buffer,
160 .alen = alen,
161 };
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400162
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400163 /* wait for things to settle */
Scott Jianga6be70f2014-11-13 15:30:54 +0800164 while (readw(&twi->master_stat) & BUSBUSY)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400165 if (ctrlc())
166 return 1;
167
168 /* Set Transmit device address */
Scott Jianga6be70f2014-11-13 15:30:54 +0800169 writew(chip, &twi->master_addr);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400170
171 /* Clear the FIFO before starting things */
Scott Jianga6be70f2014-11-13 15:30:54 +0800172 writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
173 writew(0, &twi->fifo_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400174
175 /* prime the pump */
176 if (msg.alen) {
Peter Meerwald98ab14e2009-06-29 15:48:33 -0400177 len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
Scott Jianga6be70f2014-11-13 15:30:54 +0800178 writew(*(msg.abuf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400179 --msg.alen;
180 } else if (!(msg.flags & I2C_M_READ) && msg.len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800181 writew(*(msg.buf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400182 --msg.len;
183 }
184
185 /* clear int stat */
Scott Jianga6be70f2014-11-13 15:30:54 +0800186 writew(-1, &twi->master_stat);
187 writew(-1, &twi->int_stat);
188 writew(0, &twi->int_mask);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400189
190 /* Master enable */
Scott Jianga6be70f2014-11-13 15:30:54 +0800191 ctl = readw(&twi->master_ctl);
192 ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
193 ((msg.flags & I2C_M_READ) ? MDIR : 0);
194 writew(ctl, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400195
196 /* process the rest */
Scott Jiangc4697032014-11-13 15:30:55 +0800197 ret = wait_for_completion(twi, &msg);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400198
199 if (ret) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800200 ctl = readw(&twi->master_ctl) & ~MEN;
201 writew(ctl, &twi->master_ctl);
202 ctl = readw(&twi->control) & ~TWI_ENA;
203 writew(ctl, &twi->control);
204 ctl = readw(&twi->control) | TWI_ENA;
205 writew(ctl, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400206 }
207
208 return ret;
209}
210
Scott Jiangc4697032014-11-13 15:30:55 +0800211static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
Mike Frysinger08a1c622009-10-14 19:27:27 -0400212{
Scott Jiangc4697032014-11-13 15:30:55 +0800213 struct twi_regs *twi = i2c_get_base(adap);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400214 u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
215
216 /* Set TWI interface clock */
217 if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
218 return -1;
Scott Jianga6be70f2014-11-13 15:30:54 +0800219 clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
220 writew(clkdiv, &twi->clkdiv);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400221
222 /* Don't turn it on */
Scott Jianga6be70f2014-11-13 15:30:54 +0800223 writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400224
225 return 0;
226}
227
Scott Jiangc4697032014-11-13 15:30:55 +0800228static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Mike Frysinger08a1c622009-10-14 19:27:27 -0400229{
Scott Jiangc4697032014-11-13 15:30:55 +0800230 struct twi_regs *twi = i2c_get_base(adap);
231 u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400232
233 /* Set TWI internal clock as 10MHz */
Scott Jianga6be70f2014-11-13 15:30:54 +0800234 writew(prescale, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400235
236 /* Set TWI interface clock as specified */
Mike Frysinger08a1c622009-10-14 19:27:27 -0400237 i2c_set_bus_speed(speed);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400238
Mike Frysinger08a1c622009-10-14 19:27:27 -0400239 /* Enable it */
Scott Jianga6be70f2014-11-13 15:30:54 +0800240 writew(TWI_ENA | prescale, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400241}
242
Scott Jiangc4697032014-11-13 15:30:55 +0800243static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
244 uint addr, int alen, uint8_t *buffer, int len)
245{
246 return i2c_transfer(adap, chip, addr, alen, buffer,
247 len, alen ? I2C_M_COMBO : I2C_M_READ);
248}
249
250static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
251 uint addr, int alen, uint8_t *buffer, int len)
252{
253 return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
254}
255
256static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400257{
258 u8 byte;
Scott Jiangc4697032014-11-13 15:30:55 +0800259 return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400260}
261
Scott Jiangc4697032014-11-13 15:30:55 +0800262static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400263{
Scott Jiangc4697032014-11-13 15:30:55 +0800264 switch (adap->hwadapnr) {
265#if CONFIG_SYS_MAX_I2C_BUS > 2
266 case 2:
267 return (struct twi_regs *)TWI2_CLKDIV;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400268#endif
269#if CONFIG_SYS_MAX_I2C_BUS > 1
Scott Jianga6be70f2014-11-13 15:30:54 +0800270 case 1:
Scott Jiangc4697032014-11-13 15:30:55 +0800271 return (struct twi_regs *)TWI1_CLKDIV;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400272#endif
Scott Jiangc4697032014-11-13 15:30:55 +0800273 case 0:
274 return (struct twi_regs *)TWI0_CLKDIV;
275
276 default:
277 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400278 }
Scott Jiangc4697032014-11-13 15:30:55 +0800279
280 return NULL;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400281}
282
Scott Jiangc4697032014-11-13 15:30:55 +0800283U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
284 adi_i2c_read, adi_i2c_write,
285 adi_i2c_setspeed,
286 CONFIG_SYS_I2C_SPEED,
287 0,
288 0)
289
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400290#if CONFIG_SYS_MAX_I2C_BUS > 1
Scott Jiangc4697032014-11-13 15:30:55 +0800291U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
292 adi_i2c_read, adi_i2c_write,
293 adi_i2c_setspeed,
294 CONFIG_SYS_I2C_SPEED,
295 0,
296 1)
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400297#endif
Scott Jiangc4697032014-11-13 15:30:55 +0800298
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400299#if CONFIG_SYS_MAX_I2C_BUS > 2
Scott Jiangc4697032014-11-13 15:30:55 +0800300U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
301 adi_i2c_read, adi_i2c_write,
302 adi_i2c_setspeed,
303 CONFIG_SYS_I2C_SPEED,
304 0,
305 2)
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400306#endif