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Andy Fleming9082eea2011-04-07 21:56:05 -05001/*
2 * Micrel PHY drivers
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05005 *
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * author Andy Fleming
David Andrey62d7dba2013-02-06 22:18:37 +01008 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
Andy Fleming9082eea2011-04-07 21:56:05 -05009 */
Troy Kisky8682aba2012-02-07 14:08:48 +000010#include <config.h>
11#include <common.h>
Marek Vasut22854bd2015-12-05 17:41:58 +010012#include <dm.h>
13#include <errno.h>
14#include <fdtdec.h>
Troy Kisky8682aba2012-02-07 14:08:48 +000015#include <micrel.h>
Andy Fleming9082eea2011-04-07 21:56:05 -050016#include <phy.h>
17
Marek Vasut22854bd2015-12-05 17:41:58 +010018DECLARE_GLOBAL_DATA_PTR;
19
Andy Fleming9082eea2011-04-07 21:56:05 -050020static struct phy_driver KSZ804_driver = {
21 .name = "Micrel KSZ804",
22 .uid = 0x221510,
23 .mask = 0xfffff0,
24 .features = PHY_BASIC_FEATURES,
25 .config = &genphy_config,
26 .startup = &genphy_startup,
27 .shutdown = &genphy_shutdown,
28};
29
Alexandre Messier79e3efd2016-01-22 14:06:33 -050030#define MII_KSZPHY_OMSO 0x16
31#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
32
33static int ksz_genconfig_bcastoff(struct phy_device *phydev)
34{
35 int ret;
36
37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
38 if (ret < 0)
39 return ret;
40
41 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
42 ret | KSZPHY_OMSO_B_CAST_OFF);
43 if (ret < 0)
44 return ret;
45
46 return genphy_config(phydev);
47}
48
Sylvain Lemieux6617f872015-09-09 16:29:51 -040049static struct phy_driver KSZ8031_driver = {
50 .name = "Micrel KSZ8021/KSZ8031",
51 .uid = 0x221550,
52 .mask = 0xfffff0,
53 .features = PHY_BASIC_FEATURES,
Alexandre Messier79e3efd2016-01-22 14:06:33 -050054 .config = &ksz_genconfig_bcastoff,
Sylvain Lemieux6617f872015-09-09 16:29:51 -040055 .startup = &genphy_startup,
56 .shutdown = &genphy_shutdown,
57};
58
Sylvain Rochet4f485152015-10-07 22:54:22 +020059/**
60 * KSZ8051
61 */
62#define MII_KSZ8051_PHY_OMSO 0x16
63#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5)
64
65static int ksz8051_config(struct phy_device *phydev)
66{
67 unsigned val;
68
69 /* Disable NAND-tree */
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
71 val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
72 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
73
74 return genphy_config(phydev);
75}
76
77static struct phy_driver KSZ8051_driver = {
78 .name = "Micrel KSZ8051",
79 .uid = 0x221550,
80 .mask = 0xfffff0,
81 .features = PHY_BASIC_FEATURES,
82 .config = &ksz8051_config,
83 .startup = &genphy_startup,
84 .shutdown = &genphy_shutdown,
85};
86
Luca Elleroc6a40f62015-03-24 11:32:24 +010087static struct phy_driver KSZ8081_driver = {
88 .name = "Micrel KSZ8081",
89 .uid = 0x221560,
90 .mask = 0xfffff0,
91 .features = PHY_BASIC_FEATURES,
Alexandre Messier79e3efd2016-01-22 14:06:33 -050092 .config = &ksz_genconfig_bcastoff,
Luca Elleroc6a40f62015-03-24 11:32:24 +010093 .startup = &genphy_startup,
94 .shutdown = &genphy_shutdown,
95};
96
Philippe De Muyterb7a5b082014-02-19 17:21:59 +010097/**
98 * KSZ8895
99 */
100
101static unsigned short smireg_to_phy(unsigned short reg)
102{
103 return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
104}
105
106static unsigned short smireg_to_reg(unsigned short reg)
107{
108 return reg & 0x1F;
109}
110
111static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
112{
113 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
114 smireg_to_reg(smireg), val);
115}
116
117#if 0
118static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
119{
120 return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
121 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
122}
123#endif
124
125int ksz8895_config(struct phy_device *phydev)
126{
127 /* we are connected directly to the switch without
128 * dedicated PHY. SCONF1 == 001 */
129 phydev->link = 1;
130 phydev->duplex = DUPLEX_FULL;
131 phydev->speed = SPEED_100;
132
133 /* Force the switch to start */
134 ksz8895_write_smireg(phydev, 1, 1);
135
136 return 0;
137}
138
139static int ksz8895_startup(struct phy_device *phydev)
140{
141 return 0;
142}
143
144static struct phy_driver ksz8895_driver = {
145 .name = "Micrel KSZ8895/KSZ8864",
146 .uid = 0x221450,
147 .mask = 0xffffe1,
148 .features = PHY_BASIC_FEATURES,
149 .config = &ksz8895_config,
150 .startup = &ksz8895_startup,
151 .shutdown = &genphy_shutdown,
152};
153
Troy Kiskycc5f5522012-06-28 08:00:28 +0000154#ifndef CONFIG_PHY_MICREL_KSZ9021
155/*
156 * I can't believe Micrel used the exact same part number
Pavel Machek58ec63d2014-09-09 14:26:51 +0200157 * for the KSZ9021. Shame Micrel, Shame!
Troy Kiskycc5f5522012-06-28 08:00:28 +0000158 */
Vladimir Zapolskiyfcc0c752011-12-06 02:47:57 +0000159static struct phy_driver KS8721_driver = {
160 .name = "Micrel KS8721BL",
161 .uid = 0x221610,
162 .mask = 0xfffff0,
163 .features = PHY_BASIC_FEATURES,
164 .config = &genphy_config,
165 .startup = &genphy_startup,
166 .shutdown = &genphy_shutdown,
167};
Troy Kiskycc5f5522012-06-28 08:00:28 +0000168#endif
Vladimir Zapolskiyfcc0c752011-12-06 02:47:57 +0000169
David Andrey62d7dba2013-02-06 22:18:37 +0100170
Pavel Machek58ec63d2014-09-09 14:26:51 +0200171/*
David Andrey62d7dba2013-02-06 22:18:37 +0100172 * KSZ9021 - KSZ9031 common
173 */
174
175#define MII_KSZ90xx_PHY_CTL 0x1f
176#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
177#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
178#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
179#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
180
181static int ksz90xx_startup(struct phy_device *phydev)
182{
183 unsigned phy_ctl;
Michal Simekb733c272016-05-18 12:46:12 +0200184 int ret;
185
186 ret = genphy_update_link(phydev);
187 if (ret)
188 return ret;
189
David Andrey62d7dba2013-02-06 22:18:37 +0100190 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
191
192 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
193 phydev->duplex = DUPLEX_FULL;
194 else
195 phydev->duplex = DUPLEX_HALF;
196
197 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
198 phydev->speed = SPEED_1000;
199 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
200 phydev->speed = SPEED_100;
201 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
202 phydev->speed = SPEED_10;
203 return 0;
204}
David Andrey62d7dba2013-02-06 22:18:37 +0100205
Marek Vasut22854bd2015-12-05 17:41:58 +0100206/* Common OF config bits for KSZ9021 and KSZ9031 */
207#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
208#ifdef CONFIG_DM_ETH
209struct ksz90x1_reg_field {
210 const char *name;
211 const u8 size; /* Size of the bitfield, in bits */
212 const u8 off; /* Offset from bit 0 */
213 const u8 dflt; /* Default value */
214};
215
216struct ksz90x1_ofcfg {
217 const u16 reg;
218 const u16 devad;
219 const struct ksz90x1_reg_field *grp;
220 const u16 grpsz;
221};
222
223static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
224 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
225 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
226};
227
228static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
229 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
230 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
231};
232
233static int ksz90x1_of_config_group(struct phy_device *phydev,
234 struct ksz90x1_ofcfg *ofcfg)
235{
236 struct udevice *dev = phydev->dev;
237 struct phy_driver *drv = phydev->drv;
Dinh Nguyenff7bd212016-01-27 15:46:00 -0600238 const int ps_to_regval = 60;
Marek Vasut22854bd2015-12-05 17:41:58 +0100239 int val[4];
240 int i, changed = 0, offset, max;
241 u16 regval = 0;
242
243 if (!drv || !drv->writeext)
244 return -EOPNOTSUPP;
245
246 for (i = 0; i < ofcfg->grpsz; i++) {
247 val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
248 ofcfg->grp[i].name, -1);
249 offset = ofcfg->grp[i].off;
250 if (val[i] == -1) {
251 /* Default register value for KSZ9021 */
252 regval |= ofcfg->grp[i].dflt << offset;
253 } else {
254 changed = 1; /* Value was changed in OF */
255 /* Calculate the register value and fix corner cases */
256 if (val[i] > ps_to_regval * 0xf) {
257 max = (1 << ofcfg->grp[i].size) - 1;
258 regval |= max << offset;
259 } else {
260 regval |= (val[i] / ps_to_regval) << offset;
261 }
262 }
263 }
264
265 if (!changed)
266 return 0;
267
268 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
269}
270#endif
271#endif
272
Pavel Machek58ec63d2014-09-09 14:26:51 +0200273#ifdef CONFIG_PHY_MICREL_KSZ9021
David Andrey62d7dba2013-02-06 22:18:37 +0100274/*
275 * KSZ9021
276 */
277
278/* PHY Registers */
Troy Kisky8682aba2012-02-07 14:08:48 +0000279#define MII_KSZ9021_EXTENDED_CTRL 0x0b
280#define MII_KSZ9021_EXTENDED_DATAW 0x0c
281#define MII_KSZ9021_EXTENDED_DATAR 0x0d
Troy Kisky8682aba2012-02-07 14:08:48 +0000282
283#define CTRL1000_PREFER_MASTER (1 << 10)
284#define CTRL1000_CONFIG_MASTER (1 << 11)
285#define CTRL1000_MANUAL_CONFIG (1 << 12)
286
Mugunthan V N347348f2016-02-02 15:51:32 +0530287#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
288 defined(CONFIG_PHY_MICREL_KSZ9031))
Marek Vasut22854bd2015-12-05 17:41:58 +0100289static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
290 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
291 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
292};
293
294static int ksz9021_of_config(struct phy_device *phydev)
295{
296 struct ksz90x1_ofcfg ofcfg[] = {
297 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
298 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
299 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
300 };
301 int i, ret = 0;
302
303 for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
304 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
305 if (ret)
306 return ret;
307
308 return 0;
309}
310#else
311static int ksz9021_of_config(struct phy_device *phydev)
312{
313 return 0;
314}
315#endif
316
Troy Kisky8682aba2012-02-07 14:08:48 +0000317int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
318{
319 /* extended registers */
320 phy_write(phydev, MDIO_DEVAD_NONE,
321 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
322 return phy_write(phydev, MDIO_DEVAD_NONE,
323 MII_KSZ9021_EXTENDED_DATAW, val);
324}
325
326int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
327{
328 /* extended registers */
329 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
330 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
331}
332
Stefano Babic9ced16f2013-09-02 15:42:31 +0200333
334static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
335 int regnum)
336{
337 return ksz9021_phy_extended_read(phydev, regnum);
338}
339
340static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
341 int devaddr, int regnum, u16 val)
342{
343 return ksz9021_phy_extended_write(phydev, regnum, val);
344}
345
Troy Kisky8682aba2012-02-07 14:08:48 +0000346/* Micrel ksz9021 */
347static int ksz9021_config(struct phy_device *phydev)
348{
349 unsigned ctrl1000 = 0;
350 const unsigned master = CTRL1000_PREFER_MASTER |
351 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
352 unsigned features = phydev->drv->features;
Marek Vasut22854bd2015-12-05 17:41:58 +0100353 int ret;
354
355 ret = ksz9021_of_config(phydev);
356 if (ret)
357 return ret;
Troy Kisky8682aba2012-02-07 14:08:48 +0000358
359 if (getenv("disable_giga"))
360 features &= ~(SUPPORTED_1000baseT_Half |
361 SUPPORTED_1000baseT_Full);
362 /* force master mode for 1000BaseT due to chip errata */
363 if (features & SUPPORTED_1000baseT_Half)
364 ctrl1000 |= ADVERTISE_1000HALF | master;
365 if (features & SUPPORTED_1000baseT_Full)
366 ctrl1000 |= ADVERTISE_1000FULL | master;
367 phydev->advertising = phydev->supported = features;
368 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
369 genphy_config_aneg(phydev);
370 genphy_restart_aneg(phydev);
371 return 0;
372}
373
Troy Kisky8682aba2012-02-07 14:08:48 +0000374static struct phy_driver ksz9021_driver = {
375 .name = "Micrel ksz9021",
376 .uid = 0x221610,
377 .mask = 0xfffff0,
378 .features = PHY_GBIT_FEATURES,
379 .config = &ksz9021_config,
David Andrey62d7dba2013-02-06 22:18:37 +0100380 .startup = &ksz90xx_startup,
Troy Kisky8682aba2012-02-07 14:08:48 +0000381 .shutdown = &genphy_shutdown,
Stefano Babic9ced16f2013-09-02 15:42:31 +0200382 .writeext = &ksz9021_phy_extwrite,
383 .readext = &ksz9021_phy_extread,
Troy Kisky8682aba2012-02-07 14:08:48 +0000384};
Troy Kiskycc5f5522012-06-28 08:00:28 +0000385#endif
Troy Kisky8682aba2012-02-07 14:08:48 +0000386
SARTRE Leo42a7cb52013-04-30 16:57:25 +0200387/**
David Andrey62d7dba2013-02-06 22:18:37 +0100388 * KSZ9031
389 */
SARTRE Leo42a7cb52013-04-30 16:57:25 +0200390/* PHY Registers */
391#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
392#define MII_KSZ9031_MMD_REG_DATA 0x0e
393
Mugunthan V N347348f2016-02-02 15:51:32 +0530394#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \
395 defined(CONFIG_PHY_MICREL_KSZ9031))
Marek Vasut22854bd2015-12-05 17:41:58 +0100396static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
397 { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
398static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
399 { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
400
401static int ksz9031_of_config(struct phy_device *phydev)
402{
403 struct ksz90x1_ofcfg ofcfg[] = {
404 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
405 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
406 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
407 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
408 };
409 int i, ret = 0;
410
411 for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
412 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
413 if (ret)
414 return ret;
415
416 return 0;
417}
418#else
419static int ksz9031_of_config(struct phy_device *phydev)
420{
421 return 0;
422}
423#endif
424
SARTRE Leo42a7cb52013-04-30 16:57:25 +0200425/* Accessors to extended registers*/
426int ksz9031_phy_extended_write(struct phy_device *phydev,
427 int devaddr, int regnum, u16 mode, u16 val)
428{
429 /*select register addr for mmd*/
430 phy_write(phydev, MDIO_DEVAD_NONE,
431 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
432 /*select register for mmd*/
433 phy_write(phydev, MDIO_DEVAD_NONE,
434 MII_KSZ9031_MMD_REG_DATA, regnum);
435 /*setup mode*/
436 phy_write(phydev, MDIO_DEVAD_NONE,
437 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
438 /*write the value*/
439 return phy_write(phydev, MDIO_DEVAD_NONE,
440 MII_KSZ9031_MMD_REG_DATA, val);
441}
442
443int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
444 int regnum, u16 mode)
445{
446 phy_write(phydev, MDIO_DEVAD_NONE,
447 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
448 phy_write(phydev, MDIO_DEVAD_NONE,
449 MII_KSZ9031_MMD_REG_DATA, regnum);
450 phy_write(phydev, MDIO_DEVAD_NONE,
451 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
452 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
453}
454
Stefano Babic9ced16f2013-09-02 15:42:31 +0200455static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
456 int regnum)
457{
458 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
459 MII_KSZ9031_MOD_DATA_NO_POST_INC);
460};
461
462static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
463 int devaddr, int regnum, u16 val)
464{
465 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
466 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
467};
468
Marek Vasut22854bd2015-12-05 17:41:58 +0100469static int ksz9031_config(struct phy_device *phydev)
470{
471 int ret;
472 ret = ksz9031_of_config(phydev);
473 if (ret)
474 return ret;
475 return genphy_config(phydev);
476}
Stefano Babic9ced16f2013-09-02 15:42:31 +0200477
David Andrey62d7dba2013-02-06 22:18:37 +0100478static struct phy_driver ksz9031_driver = {
479 .name = "Micrel ksz9031",
480 .uid = 0x221620,
Stefano Babice8194d52013-09-02 15:42:29 +0200481 .mask = 0xfffff0,
David Andrey62d7dba2013-02-06 22:18:37 +0100482 .features = PHY_GBIT_FEATURES,
Marek Vasut22854bd2015-12-05 17:41:58 +0100483 .config = &ksz9031_config,
David Andrey62d7dba2013-02-06 22:18:37 +0100484 .startup = &ksz90xx_startup,
485 .shutdown = &genphy_shutdown,
Stefano Babic9ced16f2013-09-02 15:42:31 +0200486 .writeext = &ksz9031_phy_extwrite,
487 .readext = &ksz9031_phy_extread,
David Andrey62d7dba2013-02-06 22:18:37 +0100488};
489
Alexey Firago79887742016-05-26 16:28:44 +0300490int ksz886x_config(struct phy_device *phydev)
491{
492 /* we are connected directly to the switch without
493 * dedicated PHY. */
494 phydev->link = 1;
495 phydev->duplex = DUPLEX_FULL;
496 phydev->speed = SPEED_100;
497 return 0;
498}
499
500static int ksz886x_startup(struct phy_device *phydev)
501{
502 return 0;
503}
504
505static struct phy_driver ksz886x_driver = {
506 .name = "Micrel KSZ886x Switch",
507 .uid = 0x00221430,
508 .mask = 0xfffff0,
509 .features = PHY_BASIC_FEATURES,
510 .config = &ksz886x_config,
511 .startup = &ksz886x_startup,
512 .shutdown = &genphy_shutdown,
513};
514
Andy Fleming9082eea2011-04-07 21:56:05 -0500515int phy_micrel_init(void)
516{
517 phy_register(&KSZ804_driver);
Sylvain Lemieux6617f872015-09-09 16:29:51 -0400518 phy_register(&KSZ8031_driver);
Sylvain Rochet4f485152015-10-07 22:54:22 +0200519 phy_register(&KSZ8051_driver);
Luca Elleroc6a40f62015-03-24 11:32:24 +0100520 phy_register(&KSZ8081_driver);
Troy Kiskycc5f5522012-06-28 08:00:28 +0000521#ifdef CONFIG_PHY_MICREL_KSZ9021
Troy Kisky8682aba2012-02-07 14:08:48 +0000522 phy_register(&ksz9021_driver);
Troy Kiskycc5f5522012-06-28 08:00:28 +0000523#else
524 phy_register(&KS8721_driver);
525#endif
David Andrey62d7dba2013-02-06 22:18:37 +0100526 phy_register(&ksz9031_driver);
Philippe De Muyterb7a5b082014-02-19 17:21:59 +0100527 phy_register(&ksz8895_driver);
Alexey Firago79887742016-05-26 16:28:44 +0300528 phy_register(&ksz886x_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500529 return 0;
530}