blob: 69ef19cc85afdb7a90fd6287b8059741509c4cbe [file] [log] [blame]
Joseph Chen2a950e32021-06-02 15:58:25 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/armv8/mmu.h>
9#include <asm/io.h>
Chris Morgan0d61f8e2023-02-13 16:27:38 -060010#include <asm/arch-rockchip/bootrom.h>
Joseph Chen2a950e32021-06-02 15:58:25 +080011#include <asm/arch-rockchip/grf_rk3568.h>
12#include <asm/arch-rockchip/hardware.h>
13#include <dt-bindings/clock/rk3568-cru.h>
14
Nico Chengef7f4302021-10-26 10:42:21 +080015#define PMUGRF_BASE 0xfdc20000
16#define GRF_BASE 0xfdc60000
17#define GRF_GPIO1B_DS_2 0x218
18#define GRF_GPIO1B_DS_3 0x21c
19#define GRF_GPIO1C_DS_0 0x220
20#define GRF_GPIO1C_DS_1 0x224
21#define GRF_GPIO1C_DS_2 0x228
22#define GRF_GPIO1C_DS_3 0x22c
23#define SGRF_BASE 0xFDD18000
24#define SGRF_SOC_CON4 0x10
25#define EMMC_HPROT_SECURE_CTRL 0x03
26#define SDMMC0_HPROT_SECURE_CTRL 0x01
Chris Morgan95ef2aa2023-02-13 16:27:39 -060027
28#define PMU_BASE_ADDR 0xfdd90000
29#define PMU_NOC_AUTO_CON0 (0x70)
30#define PMU_NOC_AUTO_CON1 (0x74)
31#define EDP_PHY_GRF_BASE 0xfdcb0000
32#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
33#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
34#define CPU_GRF_BASE 0xfdc30000
35#define GRF_CORE_PVTPLL_CON0 (0x10)
36
Joseph Chen2a950e32021-06-02 15:58:25 +080037/* PMU_GRF_GPIO0D_IOMUX_L */
38enum {
39 GPIO0D1_SHIFT = 4,
40 GPIO0D1_MASK = GENMASK(6, 4),
41 GPIO0D1_GPIO = 0,
42 GPIO0D1_UART2_TXM0,
43
44 GPIO0D0_SHIFT = 0,
45 GPIO0D0_MASK = GENMASK(2, 0),
46 GPIO0D0_GPIO = 0,
47 GPIO0D0_UART2_RXM0,
48};
49
50/* GRF_IOFUNC_SEL3 */
51enum {
52 UART2_IO_SEL_SHIFT = 10,
53 UART2_IO_SEL_MASK = GENMASK(11, 10),
54 UART2_IO_SEL_M0 = 0,
55};
56
57static struct mm_region rk3568_mem_map[] = {
58 {
59 .virt = 0x0UL,
60 .phys = 0x0UL,
61 .size = 0xf0000000UL,
62 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
63 PTE_BLOCK_INNER_SHARE
64 }, {
65 .virt = 0xf0000000UL,
66 .phys = 0xf0000000UL,
67 .size = 0x10000000UL,
68 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
69 PTE_BLOCK_NON_SHARE |
70 PTE_BLOCK_PXN | PTE_BLOCK_UXN
71 }, {
72 .virt = 0x300000000,
73 .phys = 0x300000000,
74 .size = 0x0c0c00000,
75 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
76 PTE_BLOCK_NON_SHARE |
77 PTE_BLOCK_PXN | PTE_BLOCK_UXN
78 }, {
79 /* List terminator */
80 0,
81 }
82};
83
Chris Morgan0d61f8e2023-02-13 16:27:38 -060084const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
Jonas Karlman42f67fb2023-03-14 00:38:23 +000085 [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000",
Chris Morgan0d61f8e2023-02-13 16:27:38 -060086 [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
87 [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
88};
89
Joseph Chen2a950e32021-06-02 15:58:25 +080090struct mm_region *mem_map = rk3568_mem_map;
91
92void board_debug_uart_init(void)
93{
94 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
95 static struct rk3568_grf * const grf = (void *)GRF_BASE;
96
97 /* UART2 M0 */
98 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
99 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
100
101 /* Switch iomux */
102 rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
103 GPIO0D1_MASK | GPIO0D0_MASK,
104 GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
105 GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
106}
107
108int arch_cpu_init(void)
109{
Nico Chengef7f4302021-10-26 10:42:21 +0800110#ifdef CONFIG_SPL_BUILD
Chris Morgan95ef2aa2023-02-13 16:27:39 -0600111 /*
112 * When perform idle operation, corresponding clock can
113 * be opened or gated automatically.
114 */
115 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
116 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
117
118 /* Disable eDP phy by default */
119 writel(0x00070007, EDP_PHY_GRF_CON10);
120 writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
121
122 /* Set core pvtpll ring length */
123 writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
124
Nico Chengef7f4302021-10-26 10:42:21 +0800125 /* Set the emmc sdmmc0 to secure */
126 rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
127 | SDMMC0_HPROT_SECURE_CTRL << 4));
128 /* set the emmc driver strength to level 2 */
129 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
130 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
131 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
132 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
133 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
134 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
135#endif
Joseph Chen2a950e32021-06-02 15:58:25 +0800136 return 0;
137}