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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala9490a7f2008-07-25 13:31:05 -05002/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00003 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05004 */
5
6/*
7 * mpc8536ds board configuration file
8 *
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Kumar Galac7e1a432010-05-21 04:14:49 -050013#include "../board/freescale/common/ics307_clk.h"
14
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020015#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080016#define CONFIG_RAMBOOT_SDCARD 1
Kumar Gala7a577fd2011-01-12 02:48:53 -060017#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080018#endif
19
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020020#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080021#define CONFIG_RAMBOOT_SPIFLASH 1
Kumar Gala7a577fd2011-01-12 02:48:53 -060022#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#endif
24
Kumar Gala7a577fd2011-01-12 02:48:53 -060025#ifndef CONFIG_RESET_VECTOR_ADDRESS
26#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
27#endif
28
Haiying Wang96196a12010-11-10 15:37:13 -050029#ifndef CONFIG_SYS_MONITOR_BASE
30#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
31#endif
32
Kumar Gala9490a7f2008-07-25 13:31:05 -050033#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040034#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
35#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
36#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Kumar Gala9490a7f2008-07-25 13:31:05 -050037#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000038#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala0151cba2008-10-21 11:33:58 -050039#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050040
Kumar Gala9490a7f2008-07-25 13:31:05 -050041
Kumar Gala9490a7f2008-07-25 13:31:05 -050042#define CONFIG_ENV_OVERWRITE
43
Kumar Galac7e1a432010-05-21 04:14:49 -050044#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
45#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050046#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050047
48/*
49 * These can be toggled for performance analysis, otherwise use default.
50 */
51#define CONFIG_L2_CACHE /* toggle L2 cache */
52#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -050053
54#define CONFIG_ENABLE_36BIT_PHYS 1
55
Kumar Gala337f9fd2009-07-30 15:54:07 -050056#ifdef CONFIG_PHYS_64BIT
57#define CONFIG_ADDR_MAP 1
58#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
59#endif
60
Mingkai Hu07355702009-09-23 15:19:32 +080061#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
62#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -050063
64/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080065 * Config the L2 Cache as L2 SRAM
66 */
67#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
68#ifdef CONFIG_PHYS_64BIT
69#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
70#else
71#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
72#endif
73#define CONFIG_SYS_L2_SIZE (512 << 10)
74#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
75
Timur Tabie46fedf2011-08-04 18:03:41 -050076#define CONFIG_SYS_CCSRBAR 0xffe00000
77#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -050078
Kumar Gala8d22ddc2011-11-09 09:10:49 -060079#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050080#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080081#endif
82
Kumar Gala9490a7f2008-07-25 13:31:05 -050083/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -050084#define CONFIG_VERY_BIG_RAM
Kumar Gala9490a7f2008-07-25 13:31:05 -050085#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
86#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -050087
Dave Liu9b0ad1b2008-10-28 17:53:38 +080088#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -050089#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -050093
Kumar Gala9490a7f2008-07-25 13:31:05 -050094#define CONFIG_DIMM_SLOTS_PER_CTLR 1
95#define CONFIG_CHIP_SELECTS_PER_CTRL 2
96
97/* I2C addresses of SPD EEPROMs */
98#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500100
101/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800102#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800104#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_DDR_TIMING_3 0x00000000
106#define CONFIG_SYS_DDR_TIMING_0 0x00260802
107#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
108#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
109#define CONFIG_SYS_DDR_MODE_1 0x00480432
110#define CONFIG_SYS_DDR_MODE_2 0x00000000
111#define CONFIG_SYS_DDR_INTERVAL 0x06180100
112#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
113#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
114#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
115#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800116#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
120#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
121#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500122
Kumar Gala9490a7f2008-07-25 13:31:05 -0500123/* Make sure required options are set */
124#ifndef CONFIG_SPD_EEPROM
125#error ("CONFIG_SPD_EEPROM is required")
126#endif
127
128#undef CONFIG_CLOCKS_IN_MHZ
129
Kumar Gala9490a7f2008-07-25 13:31:05 -0500130/*
131 * Memory map -- xxx -this is wrong, needs updating
132 *
133 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
134 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
135 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
136 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
137 *
138 * Localbus cacheable (TBD)
139 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
140 *
141 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500142 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500143 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500144 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500145 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
146 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
147 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
148 */
149
150/*
151 * Local Bus Definitions
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
156#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600157#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500158#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500159
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800160#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800162#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500163
Mingkai Hu07355702009-09-23 15:19:32 +0800164#define CONFIG_SYS_BR1_PRELIM \
165 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
166 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600167#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500168
Mingkai Hu07355702009-09-23 15:19:32 +0800169#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
170 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500172#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
173
Mingkai Hu07355702009-09-23 15:19:32 +0800174#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
175#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800177#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
178#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500179
Masahiro Yamada02344462014-06-04 10:26:50 +0900180#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800181#define CONFIG_SYS_RAMBOOT
182#else
183#undef CONFIG_SYS_RAMBOOT
184#endif
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_EMPTY_INFO
187#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500188
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000189#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500190#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
191#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500192#ifdef CONFIG_PHYS_64BIT
193#define PIXIS_BASE_PHYS 0xfffdf0000ull
194#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600195#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500196#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500197
Kumar Gala52b565f2008-12-02 14:19:33 -0600198#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800199#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500200
201#define PIXIS_ID 0x0 /* Board ID at offset 0 */
202#define PIXIS_VER 0x1 /* Board version at offset 1 */
203#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
204#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
205#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
206#define PIXIS_PWR 0x5 /* PIXIS Power status register */
207#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
208#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
209#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
210#define PIXIS_VCTL 0x10 /* VELA Control Register */
211#define PIXIS_VSTAT 0x11 /* VELA Status Register */
212#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
213#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
214#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
215#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500216#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
217#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
218#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
219#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
220#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
221#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
222#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500223#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
224#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
225#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
226#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
227#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
228#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
229#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
230#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
231#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
232#define PIXIS_VWATCH 0x24 /* Watchdog Register */
233#define PIXIS_LED 0x25 /* LED Register */
234
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800235#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
236
Kumar Gala9490a7f2008-07-25 13:31:05 -0500237/* old pixis referenced names */
238#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
239#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600240#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_INIT_RAM_LOCK 1
243#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200244#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500245
Mingkai Hu07355702009-09-23 15:19:32 +0800246#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200247 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500249
Mingkai Hu07355702009-09-23 15:19:32 +0800250#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
251#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500252
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800253#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500254#define CONFIG_SYS_NAND_BASE 0xffa00000
255#ifdef CONFIG_PHYS_64BIT
256#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
257#else
258#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
259#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800260#else
261#define CONFIG_SYS_NAND_BASE 0xfff00000
262#ifdef CONFIG_PHYS_64BIT
263#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
264#else
265#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
266#endif
267#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500268#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
269 CONFIG_SYS_NAND_BASE + 0x40000, \
270 CONFIG_SYS_NAND_BASE + 0x80000, \
271 CONFIG_SYS_NAND_BASE + 0xC0000}
272#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500273#define CONFIG_NAND_FSL_ELBC 1
274#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
275
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800276/* NAND boot: 4K NAND loader config */
277#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
Haijun.Zhangc6e8f492014-02-13 09:03:02 +0800278#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800279#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
280#define CONFIG_SYS_NAND_U_BOOT_START \
281 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
282#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
283#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
284#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
285
Jason Jinc57fc282008-10-31 05:07:04 -0500286/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500287#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800288 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
289 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
290 | BR_PS_8 /* Port Size = 8 bit */ \
291 | BR_MS_FCM /* MSEL = FCM */ \
292 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500293#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800294 | OR_FCM_PGS /* Large Page*/ \
295 | OR_FCM_CSCT \
296 | OR_FCM_CST \
297 | OR_FCM_CHT \
298 | OR_FCM_SCY_1 \
299 | OR_FCM_TRLX \
300 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500301
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800302#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
303#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500304#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
305#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500306
Mingkai Hu07355702009-09-23 15:19:32 +0800307#define CONFIG_SYS_BR4_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000308 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8 bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
312 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500313#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800314#define CONFIG_SYS_BR5_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000315 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800316 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
317 | BR_PS_8 /* Port Size = 8 bit */ \
318 | BR_MS_FCM /* MSEL = FCM */ \
319 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500320#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500321
Mingkai Hu07355702009-09-23 15:19:32 +0800322#define CONFIG_SYS_BR6_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000323 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
325 | BR_PS_8 /* Port Size = 8 bit */ \
326 | BR_MS_FCM /* MSEL = FCM */ \
327 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500328#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500329
Kumar Gala9490a7f2008-07-25 13:31:05 -0500330/* Serial Port - controlled on board with jumper J8
331 * open - index 2
332 * shorted - index 1
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_NS16550_SERIAL
335#define CONFIG_SYS_NS16550_REG_SIZE 1
336#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500337#ifdef CONFIG_NAND_SPL
338#define CONFIG_NS16550_MIN_FUNCTIONS
339#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
343
Mingkai Hu07355702009-09-23 15:19:32 +0800344#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
345#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500346
Kumar Gala9490a7f2008-07-25 13:31:05 -0500347/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500348 * I2C
349 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200350#define CONFIG_SYS_I2C
351#define CONFIG_SYS_I2C_FSL
352#define CONFIG_SYS_FSL_I2C_SPEED 400000
353#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
354#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
355#define CONFIG_SYS_FSL_I2C2_SPEED 400000
356#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
357#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
358#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Kumar Gala9490a7f2008-07-25 13:31:05 -0500359
360/*
361 * I2C2 EEPROM
362 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200363#define CONFIG_ID_EEPROM
364#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500366#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
368#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
369#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500370
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700371/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500372 * General PCI
373 * Memory space is mapped 1-1, but I/O space must start from 0.
374 */
375
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600376#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500377#ifdef CONFIG_PHYS_64BIT
378#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
379#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
380#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600381#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
382#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500383#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500385#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
386#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
387#ifdef CONFIG_PHYS_64BIT
388#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
389#else
390#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
391#endif
392#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500393
394/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600395#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600396#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500397#ifdef CONFIG_PHYS_64BIT
398#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
399#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
400#else
Kumar Gala10795f42008-12-02 16:08:36 -0600401#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600402#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500403#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600405#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500406#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
407#ifdef CONFIG_PHYS_64BIT
408#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
409#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500411#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500413
414/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600415#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600416#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500417#ifdef CONFIG_PHYS_64BIT
418#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
419#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
420#else
Kumar Gala10795f42008-12-02 16:08:36 -0600421#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600422#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500423#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600425#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500426#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
427#ifdef CONFIG_PHYS_64BIT
428#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
429#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500431#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500433
434/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600435#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600436#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500437#ifdef CONFIG_PHYS_64BIT
438#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
439#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
440#else
Kumar Gala10795f42008-12-02 16:08:36 -0600441#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600442#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500443#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600445#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500446#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
447#ifdef CONFIG_PHYS_64BIT
448#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
449#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500451#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500453
454#if defined(CONFIG_PCI)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500455/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600456#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500457
458/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600459/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500460
461/* video */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500462
463#if defined(CONFIG_VIDEO)
464#define CONFIG_BIOSEMU
Kumar Gala9490a7f2008-07-25 13:31:05 -0500465#define CONFIG_ATI_RADEON_FB
466#define CONFIG_VIDEO_LOGO
Kumar Galaaca5f012008-12-02 16:08:40 -0600467#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500468#endif
469
470#undef CONFIG_EEPRO100
471#undef CONFIG_TULIP
Kumar Gala9490a7f2008-07-25 13:31:05 -0500472
Kumar Gala9490a7f2008-07-25 13:31:05 -0500473#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600474 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
475 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500476 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
477#endif
478
479#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
480
481#endif /* CONFIG_PCI */
482
483/* SATA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500485#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
487#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500488#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
490#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500491
492#ifdef CONFIG_FSL_SATA
493#define CONFIG_LBA48
Kumar Gala9490a7f2008-07-25 13:31:05 -0500494#endif
495
496#if defined(CONFIG_TSEC_ENET)
497
Kumar Gala9490a7f2008-07-25 13:31:05 -0500498#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
499#define CONFIG_TSEC1 1
500#define CONFIG_TSEC1_NAME "eTSEC1"
501#define CONFIG_TSEC3 1
502#define CONFIG_TSEC3_NAME "eTSEC3"
503
Jason Jin2e26d832008-10-10 11:41:00 +0800504#define CONFIG_FSL_SGMII_RISER 1
505#define SGMII_RISER_PHY_OFFSET 0x1c
506
Kumar Gala9490a7f2008-07-25 13:31:05 -0500507#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
508#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
509
510#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
511#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512
513#define TSEC1_PHYIDX 0
514#define TSEC3_PHYIDX 0
515
516#define CONFIG_ETHPRIME "eTSEC1"
517
Kumar Gala9490a7f2008-07-25 13:31:05 -0500518#endif /* CONFIG_TSEC_ENET */
519
520/*
521 * Environment
522 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800523
524#if defined(CONFIG_SYS_RAMBOOT)
Masahiro Yamada02344462014-06-04 10:26:50 +0900525#if defined(CONFIG_RAMBOOT_SPIFLASH)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700526#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
527#define CONFIG_ENV_OFFSET 0xF0000
528#define CONFIG_ENV_SECT_SIZE 0x10000
529#elif defined(CONFIG_RAMBOOT_SDCARD)
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000530#define CONFIG_FSL_FIXED_MMC_LOCATION
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700531#define CONFIG_ENV_SIZE 0x2000
532#define CONFIG_SYS_MMC_ENV_DEV 0
533#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800534 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
535 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500536#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800537#else
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800538 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800539 #define CONFIG_ENV_SIZE 0x2000
540 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
541#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500542
543#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500545
Kumar Gala9490a7f2008-07-25 13:31:05 -0500546#undef CONFIG_WATCHDOG /* watchdog disabled */
547
Andy Fleming80522dc2008-10-30 16:51:33 -0500548#ifdef CONFIG_MMC
Andy Fleming80522dc2008-10-30 16:51:33 -0500549#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Fanzc1116ebb2011-10-03 12:18:42 -0700550#endif
551
552/*
553 * USB
554 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000555#define CONFIG_HAS_FSL_MPH_USB
556#ifdef CONFIG_HAS_FSL_MPH_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400557#ifdef CONFIG_USB_EHCI_HCD
Fanzc1116ebb2011-10-03 12:18:42 -0700558#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
559#define CONFIG_USB_EHCI_FSL
Fanzc1116ebb2011-10-03 12:18:42 -0700560#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000561#endif
Fanzc1116ebb2011-10-03 12:18:42 -0700562
Kumar Gala9490a7f2008-07-25 13:31:05 -0500563/*
564 * Miscellaneous configurable options
565 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500567
568/*
569 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500570 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500571 * the maximum mapped by the Linux kernel during initialization.
572 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500573#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
574#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500575
Kumar Gala9490a7f2008-07-25 13:31:05 -0500576#if defined(CONFIG_CMD_KGDB)
577#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500578#endif
579
580/*
581 * Environment Configuration
582 */
583
584/* The mac addresses for all ethernet interface */
585#if defined(CONFIG_TSEC_ENET)
586#define CONFIG_HAS_ETH0
Kumar Gala9490a7f2008-07-25 13:31:05 -0500587#define CONFIG_HAS_ETH1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500588#define CONFIG_HAS_ETH2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500589#define CONFIG_HAS_ETH3
Kumar Gala9490a7f2008-07-25 13:31:05 -0500590#endif
591
592#define CONFIG_IPADDR 192.168.1.254
593
Mario Six5bc05432018-03-28 14:38:20 +0200594#define CONFIG_HOSTNAME "unknown"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000595#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000596#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800597#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500598
599#define CONFIG_SERVERIP 192.168.1.1
600#define CONFIG_GATEWAYIP 192.168.1.1
601#define CONFIG_NETMASK 255.255.255.0
602
603/* default location for tftp and bootm */
604#define CONFIG_LOADADDR 1000000
605
Kumar Gala9490a7f2008-07-25 13:31:05 -0500606#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200607"netdev=eth0\0" \
608"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
609"tftpflash=tftpboot $loadaddr $uboot; " \
610 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
611 " +$filesize; " \
612 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
613 " +$filesize; " \
614 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
615 " $filesize; " \
616 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
617 " +$filesize; " \
618 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
619 " $filesize\0" \
620"consoledev=ttyS0\0" \
621"ramdiskaddr=2000000\0" \
622"ramdiskfile=8536ds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500623"fdtaddr=1e00000\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200624"fdtfile=8536ds/mpc8536ds.dtb\0" \
625"bdev=sda3\0" \
626"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500627
628#define CONFIG_HDBOOT \
629 "setenv bootargs root=/dev/$bdev rw " \
630 "console=$consoledev,$baudrate $othbootargs;" \
631 "tftp $loadaddr $bootfile;" \
632 "tftp $fdtaddr $fdtfile;" \
633 "bootm $loadaddr - $fdtaddr"
634
635#define CONFIG_NFSBOOTCOMMAND \
636 "setenv bootargs root=/dev/nfs rw " \
637 "nfsroot=$serverip:$rootpath " \
638 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "tftp $loadaddr $bootfile;" \
641 "tftp $fdtaddr $fdtfile;" \
642 "bootm $loadaddr - $fdtaddr"
643
644#define CONFIG_RAMBOOTCOMMAND \
645 "setenv bootargs root=/dev/ram rw " \
646 "console=$consoledev,$baudrate $othbootargs;" \
647 "tftp $ramdiskaddr $ramdiskfile;" \
648 "tftp $loadaddr $bootfile;" \
649 "tftp $fdtaddr $fdtfile;" \
650 "bootm $loadaddr $ramdiskaddr $fdtaddr"
651
652#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
653
654#endif /* __CONFIG_H */