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Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Jon Smirlc9969942009-06-14 18:21:28 -040024#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
28/*
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
31 * 0xFF000000 boot low
32 * 0x00100000 boot from RAM (for testing only)
33 */
34#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36#endif
37
Jon Smirlc9969942009-06-14 18:21:28 -040038#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040039
40/*-----------------------------------------------------------------------------
41Serial console configuration
42-----------------------------------------------------------------------------*/
43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
50/*
51 * Command line configuration.
52 */
Jon Smirlc9969942009-06-14 18:21:28 -040053#define CONFIG_CMD_DATE
Jon Smirlc9969942009-06-14 18:21:28 -040054#define CONFIG_CMD_EEPROM
Jon Smirlc9969942009-06-14 18:21:28 -040055#define CONFIG_CMD_JFFS2
Jon Smirlc9969942009-06-14 18:21:28 -040056#define CONFIG_CMD_PCI
57
58#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
59
Wolfgang Denk14d0a022010-10-07 21:51:12 +020060#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040061#define CONFIG_SYS_LOWBOOT 1
62#endif
63/* RAMBOOT will be defined automatically in memory section */
64
65#define CONFIG_JFFS2_CMDLINE
66#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
67#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
68 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
69
70/*-----------------------------------------------------------------------------
71Autobooting
72-----------------------------------------------------------------------------*/
Jon Smirlc9969942009-06-14 18:21:28 -040073#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
74 /* even with bootdelay=0 */
75#undef CONFIG_BOOTARGS
76
Jon Smirlc9969942009-06-14 18:21:28 -040077#define CONFIG_PREBOOT "echo;" \
78 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
79 "mount root filesystem over NFS;" \
80 "echo"
81
82#define CONFIG_EXTRA_ENV_SETTINGS \
83 "netdev=eth0\0" \
84 "uimage=uImage-pcm030\0" \
85 "oftree=oftree-pcm030.dtb\0" \
86 "jffs2=root-pcm030.jffs2\0" \
87 "uboot=u-boot-pcm030.bin\0" \
88 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
89 " $(mtdparts) rw\0" \
90 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
91 " rootfstype=jffs2\0" \
92 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
93 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
94 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
95 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
96 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
97 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
98 "0xfff40000\0" \
99 " cp.b 0x400000 0xff040000 $(filesize)\0" \
100 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
101 "cp.b 0x400000 0xff200000 $(filesize)\0" \
102 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
103 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
104 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
105 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
106 "unlock=yes\0" \
107 ""
108
109#define CONFIG_BOOTCOMMAND "run bcmd_flash"
110
111/*--------------------------------------------------------------------------
112IPB Bus clocking configuration.
113 ---------------------------------------------------------------------------*/
114#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
115
116/*-------------------------------------------------------------------------
117 * PCI Mapping:
118 * 0x40000000 - 0x4fffffff - PCI Memory
119 * 0x50000000 - 0x50ffffff - PCI IO Space
120 * -----------------------------------------------------------------------*/
121#define CONFIG_PCI 1
122#define CONFIG_PCI_PNP 1
123#define CONFIG_PCI_SCAN_SHOW 1
124#define CONFIG_PCI_MEM_BUS 0x40000000
125#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
126#define CONFIG_PCI_MEM_SIZE 0x10000000
127#define CONFIG_PCI_IO_BUS 0x50000000
128#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
129#define CONFIG_PCI_IO_SIZE 0x01000000
130#define CONFIG_SYS_XLB_PIPELINING 1
131
132/*---------------------------------------------------------------------------
133 I2C configuration
134---------------------------------------------------------------------------*/
135#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
136#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
137#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
138#define CONFIG_SYS_I2C_SLAVE 0x7F
139
140/*---------------------------------------------------------------------------
141 EEPROM CAT24WC32 configuration
142---------------------------------------------------------------------------*/
143#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
144#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
146#define CONFIG_SYS_EEPROM_SIZE 2048
147#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
148#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
149
150/*---------------------------------------------------------------------------
151RTC configuration
152---------------------------------------------------------------------------*/
153#define RTC
154#define CONFIG_RTC_PCF8563 1
155#define CONFIG_SYS_I2C_RTC_ADDR 0x51
156
157/*---------------------------------------------------------------------------
158 Flash configuration
159---------------------------------------------------------------------------*/
160
161#define CONFIG_SYS_FLASH_BASE 0xff000000
162#define CONFIG_SYS_FLASH_SIZE 0x01000000
163#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
164
165#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
166#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
167#define CONFIG_SYS_FLASH_EMPTY_INFO
168#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
169#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
170 /* (= chip selects) */
171#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
172
173/*
174 * Use also hardware protection. This seems required, as the BDI uses
175 * hardware protection. Without this, U-Boot can't work with this sectors,
176 * as its protection is software only by default
177 */
178#define CONFIG_SYS_FLASH_PROTECTION 1
179
180/*---------------------------------------------------------------------------
181 Environment settings
182---------------------------------------------------------------------------*/
183
184/* pcm030 ships with environment is EEPROM by default */
185#define CONFIG_ENV_IS_IN_EEPROM 1
186#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
187 /*beginning of the EEPROM */
188#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
189
190#define CONFIG_ENV_OVERWRITE 1
191
192/*-----------------------------------------------------------------------------
193 Memory map
194-----------------------------------------------------------------------------*/
195#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
196 /* bootloader or debugger config */
197#define CONFIG_SYS_SDRAM_BASE 0x00000000
198#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
199/* Use SRAM until RAM will be available */
200#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200201#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400202 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200204 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400208#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209# define CONFIG_SYS_RAMBOOT 1
210#endif
211
212#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
213#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
214#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
215
216/*-----------------------------------------------------------------------------
217 Ethernet configuration
218-----------------------------------------------------------------------------*/
219#define CONFIG_MPC5xxx_FEC 1
220#define CONFIG_MPC5xxx_FEC_MII100
221#define CONFIG_PHY_ADDR 0x01
222
223/*---------------------------------------------------------------------------
224 GPIO configuration
225 ---------------------------------------------------------------------------*/
226
227/* GPIO port configuration
228 *
229 * Pin mapping:
230 *
231 * [29:31] = 01x
232 * PSC1_0 -> AC97 SDATA out
233 * PSC1_1 -> AC97 SDTA in
234 * PSC1_2 -> AC97 SYNC out
235 * PSC1_3 -> AC97 bitclock out
236 * PSC1_4 -> AC97 reset out
237 *
238 * [25:27] = 001
239 * PSC2_0 -> CAN 1 Tx out
240 * PSC2_1 -> CAN 1 Rx in
241 * PSC2_2 -> CAN 2 Tx out
242 * PSC2_3 -> CAN 2 Rx in
243 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
244 *
245 *
246 * [20:23] = 1100
247 * PSC3_0 -> UART Tx out
248 * PSC3_1 -> UART Rx in
249 * PSC3_2 -> UART RTS (in/out FIXME)
250 * PSC3_3 -> UART CTS (in/out FIXME)
251 * PSC3_4 -> LocalPlus Bus CS6 \
252 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
253 * PSC3_6 -> dedicated SPI MOSI out (master case)
254 * PSC3_7 -> dedicated SPI MISO in (master case)
255 * PSC3_8 -> dedicated SPI SS out (master case)
256 * PSC3_9 -> dedicated SPI CLK out (master case)
257 *
258 * [18:19] = 01
259 * USB_0 -> USB OE out
260 * USB_1 -> USB Tx- out
261 * USB_2 -> USB Tx+ out
262 * USB_3 -> USB RxD (in/out FIXME)
263 * USB_4 -> USB Rx+ in
264 * USB_5 -> USB Rx- in
265 * USB_6 -> USB PortPower out
266 * USB_7 -> USB speed out
267 * USB_8 -> USB suspend (in/out FIXME)
268 * USB_9 -> USB overcurrent in
269 *
270 * [17] = 0
271 * USB differential mode
272 *
273 * [16] = 0
274 * PCI enabled
275 *
276 * [12:15] = 0101
277 * ETH_0 -> ETH Txen
278 * ETH_1 -> ETH TxD0
279 * ETH_2 -> ETH TxD1
280 * ETH_3 -> ETH TxD2
281 * ETH_4 -> ETH TxD3
282 * ETH_5 -> ETH Txerr
283 * ETH_6 -> ETH MDC
284 * ETH_7 -> ETH MDIO
285 * ETH_8 -> ETH RxDv
286 * ETH_9 -> ETH RxCLK
287 * ETH_10 -> ETH Collision
288 * ETH_11 -> ETH TxD
289 * ETH_12 -> ETH RxD0
290 * ETH_13 -> ETH RxD1
291 * ETH_14 -> ETH RxD2
292 * ETH_15 -> ETH RxD3
293 * ETH_16 -> ETH Rxerr
294 * ETH_17 -> ETH CRS
295 *
296 * [9:11] = 101
297 * PSC6_0 -> UART RxD in
298 * PSC6_1 -> UART CTS (in/out FIXME)
299 * PSC6_2 -> UART TxD out
300 * PSC6_3 -> UART RTS (in/out FIXME)
301 *
302 * [2:3/6:7] = 00/11
303 * TMR_0 -> ATA_CS0 out
304 * TMR_1 -> ATA_CS1 out
305 * TMR_2 -> GPIO
306 * TMR_3 -> GPIO
307 * TMR_4 -> GPIO
308 * TMR_5 -> GPIO
309 * TMR_6 -> GPIO
310 * TMR_7 -> GPIO
311 * I2C_0 -> I2C 1 Clock out
312 * I2C_1 -> I2C 1 IO in/out
313 * I2C_2 -> I2C 2 Clock out
314 * I2C_3 -> I2C 2 IO in/out
315 *
316 * [4] = 1
317 * PSC3_5 is used as CS7
318 *
319 * [5] = 1
320 * PSC3_4 is used as CS6
321 *
322 * [1] = 0
323 * gpio_wkup_7 is GPIO
324 *
325 * [0] = 0
326 * gpio_wkup_6 is GPIO
327 *
328 */
329#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
330
331/*-----------------------------------------------------------------------------
332 Miscellaneous configurable options
333-------------------------------------------------------------------------------*/
334#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Smirlc9969942009-06-14 18:21:28 -0400335
336#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
337
338#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
339#if defined(CONFIG_CMD_KGDB)
340#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
341#endif
342
343#if defined(CONFIG_CMD_KGDB)
344#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
345#else
346#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
347#endif
348#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
349 /* Print Buffer Size */
350#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
351#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
352
353#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
354#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
355
356#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400357
358#define CONFIG_DISPLAY_BOARDINFO 1
359
360/*-----------------------------------------------------------------------------
361 Various low-level settings
362-----------------------------------------------------------------------------*/
363#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
364#define CONFIG_SYS_HID0_FINAL HID0_ICE
365
366/* no burst access on the LPB */
367#define CONFIG_SYS_CS_BURST 0x00000000
368/* one deadcycle for the 33MHz statemachine */
369#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
370/* one additional waitstate for the 33MHz statemachine */
371#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
372#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
373#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
374
375#define CONFIG_SYS_RESET_ADDRESS 0xff000000
376
377/*-----------------------------------------------------------------------
378 * USB stuff
379 *-----------------------------------------------------------------------
380 */
381#define CONFIG_USB_CLOCK 0x0001BBBB
382#define CONFIG_USB_CONFIG 0x00001000
383
384/*---------------------------------------------------------------------------
385 IDE/ATA stuff Supports IDE harddisk
386----------------------------------------------------------------------------*/
387
388#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
389#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
390#undef CONFIG_IDE_LED /* LED for ide not supported */
391#define CONFIG_SYS_ATA_CS_ON_TIMER01
392#define CONFIG_IDE_RESET 1 /* reset for ide supported */
393#define CONFIG_IDE_PREINIT
394#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
395#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
396#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
397#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
398/* Offset for data I/O */
399#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
400/* Offset for normal register accesses */
401#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
402/* Offset for alternate registers */
403#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
404/* Interval between registers */
405#define CONFIG_SYS_ATA_STRIDE 4
406#define CONFIG_ATAPI 1
407
408/* we enable IDE and FAT support, so we also need partition support */
409#define CONFIG_DOS_PARTITION 1
410
411/* USB */
412#define CONFIG_USB_OHCI
413#define CONFIG_USB_STORAGE
414
415/* pass open firmware flat tree */
Jon Smirlc9969942009-06-14 18:21:28 -0400416#define OF_CPU "PowerPC,5200@0"
417#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
418#define OF_SOC "soc5200@f0000000"
419#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
420
421#endif /* __CONFIG_H */