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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 97039ab98c551c7860bc0977d684ef686159e0d7 / . / arch / mips / include / asm / cacheops.h
blob: 70bcad7694dfc48410551c3a7c571fadfef764db [file] [log] [blame]
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]1/*
2 * Cache operations for the cache instruction.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]8 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
9 * (C) Copyright 1999 Silicon Graphics, Inc.
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]10 */
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]11#ifndef __ASM_CACHEOPS_H
12#define __ASM_CACHEOPS_H
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]13
14/*
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]15 * Cache Operations available on all MIPS processors with R4000-style caches
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]16 */
17#define Index_Invalidate_I 0x00
18#define Index_Writeback_Inv_D 0x01
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]19#define Index_Load_Tag_I 0x04
20#define Index_Load_Tag_D 0x05
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]23#if defined(CONFIG_CPU_LOONGSON2)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]24#define Hit_Invalidate_I 0x00
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]25#else
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]26#define Hit_Invalidate_I 0x10
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]27#endif
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]28#define Hit_Invalidate_D 0x11
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]29#define Hit_Writeback_Inv_D 0x15
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]30
31/*
32 * R4000-specific cacheops
33 */
34#define Create_Dirty_Excl_D 0x0d
35#define Fill 0x14
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]36#define Hit_Writeback_I 0x18
37#define Hit_Writeback_D 0x19
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]38
39/*
40 * R4000SC and R4400SC-specific cacheops
41 */
42#define Index_Invalidate_SI 0x02
43#define Index_Writeback_Inv_SD 0x03
44#define Index_Load_Tag_SI 0x06
45#define Index_Load_Tag_SD 0x07
46#define Index_Store_Tag_SI 0x0A
47#define Index_Store_Tag_SD 0x0B
48#define Create_Dirty_Excl_SD 0x0f
49#define Hit_Invalidate_SI 0x12
50#define Hit_Invalidate_SD 0x13
51#define Hit_Writeback_Inv_SD 0x17
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]52#define Hit_Writeback_SD 0x1b
wdenk6069ff22003-02-28 00:49:47 +0000[diff] [blame]53#define Hit_Set_Virtual_SI 0x1e
54#define Hit_Set_Virtual_SD 0x1f
55
Shinya Kuribayashi282223a2008-03-25 11:43:17 +0900[diff] [blame]56/*
57 * R5000-specific cacheops
58 */
59#define R5K_Page_Invalidate_S 0x17
60
61/*
62 * RM7000-specific cacheops
63 */
64#define Page_Invalidate_T 0x16
65
66/*
67 * R10000-specific cacheops
68 *
69 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
70 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
71 */
72#define Index_Writeback_Inv_S 0x03
73#define Index_Load_Tag_S 0x07
74#define Index_Store_Tag_S 0x0B
75#define Hit_Invalidate_S 0x13
76#define Cache_Barrier 0x14
77#define Hit_Writeback_Inv_S 0x17
78#define Index_Load_Data_I 0x18
79#define Index_Load_Data_D 0x19
80#define Index_Load_Data_S 0x1b
81#define Index_Store_Data_I 0x1c
82#define Index_Store_Data_D 0x1d
83#define Index_Store_Data_S 0x1f
84
85#endif /* __ASM_CACHEOPS_H */