blob: 97c3ce6e74d625664ce9d5b34c15534a0153c210 [file] [log] [blame]
Hou Zhiqiangf83c7782019-08-20 09:35:36 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * MPC8548 Silicon/SoC Device Tree Source (post include)
4 *
5 * Copyright 2012 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9&soc {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 device_type = "soc";
13 compatible = "fsl,mpc8548-immr", "simple-bus";
14 bus-frequency = <0x0>;
15
16 mpic: pic@40000 {
17 interrupt-controller;
18 #address-cells = <0>;
19 #interrupt-cells = <4>;
20 reg = <0x40000 0x40000>;
21 compatible = "fsl,mpic";
22 device_type = "open-pic";
23 big-endian;
24 single-cpu-affinity;
25 last-interrupt-source = <255>;
26 };
27};
Hou Zhiqiang00acf262019-08-27 11:05:23 +000028
29&pcie {
Pali Rohár95f8dfe2022-04-14 22:52:03 +020030 compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq";
Hou Zhiqiang00acf262019-08-27 11:05:23 +000031 law_trgt_if = <2>;
32 #address-cells = <3>;
33 #size-cells = <2>;
34 device_type = "pci";
35 bus-range = <0x0 0xff>;
36};