wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (c) 2004 Sascha Hauer <sascha@saschahauer.de> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <common.h> |
| 21 | #if defined (CONFIG_IMX) |
| 22 | |
| 23 | #include <asm/arch/imx-regs.h> |
| 24 | |
| 25 | #ifndef CONFIG_IMX_SERIAL_NONE |
| 26 | |
| 27 | #if defined CONFIG_IMX_SERIAL1 |
| 28 | #define UART_BASE IMX_UART1_BASE |
| 29 | #elif defined CONFIG_IMX_SERIAL2 |
| 30 | #define UART_BASE IMX_UART2_BASE |
| 31 | #else |
| 32 | #error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" |
| 33 | #endif |
| 34 | |
| 35 | struct imx_serial { |
| 36 | volatile uint32_t urxd[16]; |
| 37 | volatile uint32_t utxd[16]; |
| 38 | volatile uint32_t ucr1; |
| 39 | volatile uint32_t ucr2; |
| 40 | volatile uint32_t ucr3; |
| 41 | volatile uint32_t ucr4; |
| 42 | volatile uint32_t ufcr; |
| 43 | volatile uint32_t usr1; |
| 44 | volatile uint32_t usr2; |
| 45 | volatile uint32_t uesc; |
| 46 | volatile uint32_t utim; |
| 47 | volatile uint32_t ubir; |
| 48 | volatile uint32_t ubmr; |
| 49 | volatile uint32_t ubrc; |
| 50 | volatile uint32_t bipr[4]; |
| 51 | volatile uint32_t bmpr[4]; |
| 52 | volatile uint32_t uts; |
| 53 | }; |
| 54 | |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 55 | DECLARE_GLOBAL_DATA_PTR; |
| 56 | |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 57 | void serial_setbrg (void) |
| 58 | { |
| 59 | serial_init(); |
| 60 | } |
| 61 | |
| 62 | extern void imx_gpio_mode(int gpio_mode); |
| 63 | |
| 64 | /* |
| 65 | * Initialise the serial port with the given baudrate. The settings |
| 66 | * are always 8 data bits, no parity, 1 stop bit, no start bits. |
| 67 | * |
| 68 | */ |
| 69 | int serial_init (void) |
| 70 | { |
| 71 | volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 72 | unsigned int ufcr_rfdiv; |
| 73 | unsigned int refclk; |
| 74 | |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 75 | #ifdef CONFIG_IMX_SERIAL1 |
| 76 | imx_gpio_mode(PC11_PF_UART1_TXD); |
| 77 | imx_gpio_mode(PC12_PF_UART1_RXD); |
| 78 | #else |
| 79 | imx_gpio_mode(PB30_PF_UART2_TXD); |
| 80 | imx_gpio_mode(PB31_PF_UART2_RXD); |
| 81 | #endif |
| 82 | |
| 83 | /* Disable UART */ |
| 84 | base->ucr1 &= ~UCR1_UARTEN; |
| 85 | |
| 86 | /* Set to default POR state */ |
| 87 | |
| 88 | base->ucr1 = 0x00000004; |
| 89 | base->ucr2 = 0x00000000; |
| 90 | base->ucr3 = 0x00000000; |
| 91 | base->ucr4 = 0x00008040; |
| 92 | base->uesc = 0x0000002B; |
| 93 | base->utim = 0x00000000; |
| 94 | base->ubir = 0x00000000; |
| 95 | base->ubmr = 0x00000000; |
| 96 | base->uts = 0x00000000; |
| 97 | /* Set clocks */ |
| 98 | base->ucr4 |= UCR4_REF16; |
| 99 | |
| 100 | /* Configure FIFOs */ |
| 101 | base->ufcr = 0xa81; |
| 102 | |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 103 | /* set the baud rate. |
| 104 | * |
| 105 | * baud * 16 x |
| 106 | * --------- = - |
| 107 | * refclk y |
| 108 | * |
| 109 | * x - 1 = UBIR |
| 110 | * y - 1 = UBMR |
| 111 | * |
| 112 | * each register is 16 bits wide. refclk max is 96 MHz |
| 113 | * |
| 114 | */ |
| 115 | |
| 116 | ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7; |
| 117 | if (ufcr_rfdiv == 6) |
| 118 | ufcr_rfdiv = 7; |
| 119 | else |
| 120 | ufcr_rfdiv = 6 - ufcr_rfdiv; |
| 121 | |
| 122 | refclk = get_PERCLK1(); |
| 123 | refclk /= ufcr_rfdiv; |
| 124 | |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 125 | /* Set the numerator value minus one of the BRM ratio */ |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 126 | base->ubir = (gd->baudrate / 100) - 1; |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 127 | |
| 128 | /* Set the denominator value minus one of the BRM ratio */ |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 129 | base->ubmr = (refclk/(16 * 100)) - 1; |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 130 | |
| 131 | /* Set to 8N1 */ |
| 132 | base->ucr2 &= ~UCR2_PREN; |
| 133 | base->ucr2 |= UCR2_WS; |
| 134 | base->ucr2 &= ~UCR2_STPB; |
| 135 | |
| 136 | /* Ignore RTS */ |
| 137 | base->ucr2 |= UCR2_IRTS; |
| 138 | |
| 139 | /* Enable UART */ |
| 140 | base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; |
| 141 | |
| 142 | /* Enable FIFOs */ |
| 143 | base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; |
| 144 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 145 | /* Clear status flags */ |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 146 | base->usr2 |= USR2_ADET | |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 147 | USR2_DTRF | |
| 148 | USR2_IDLE | |
| 149 | USR2_IRINT | |
| 150 | USR2_WAKE | |
| 151 | USR2_RTSF | |
| 152 | USR2_BRCD | |
| 153 | USR2_ORE; |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 154 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 155 | /* Clear status flags */ |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 156 | base->usr1 |= USR1_PARITYERR | |
Andrew Dyer | 48fed40 | 2008-09-12 02:20:46 +0200 | [diff] [blame] | 157 | USR1_RTSD | |
| 158 | USR1_ESCF | |
| 159 | USR1_FRAMERR | |
| 160 | USR1_AIRINT | |
| 161 | USR1_AWAKE; |
wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 162 | return (0); |
| 163 | } |
| 164 | |
| 165 | /* |
| 166 | * Read a single byte from the serial port. Returns 1 on success, 0 |
| 167 | * otherwise. When the function is successful, the character read is |
| 168 | * written into its argument c. |
| 169 | */ |
| 170 | int serial_getc (void) |
| 171 | { |
| 172 | volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; |
| 173 | unsigned char ch; |
| 174 | |
| 175 | while(base->uts & UTS_RXEMPTY); |
| 176 | |
| 177 | ch = (char)base->urxd[0]; |
| 178 | |
| 179 | return ch; |
| 180 | } |
| 181 | |
| 182 | #ifdef CONFIG_HWFLOW |
| 183 | static int hwflow = 0; /* turned off by default */ |
| 184 | int hwflow_onoff(int on) |
| 185 | { |
| 186 | } |
| 187 | #endif |
| 188 | |
| 189 | /* |
| 190 | * Output a single byte to the serial port. |
| 191 | */ |
| 192 | void serial_putc (const char c) |
| 193 | { |
| 194 | volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; |
| 195 | |
| 196 | /* Wait for Tx FIFO not full */ |
| 197 | while (base->uts & UTS_TXFULL); |
| 198 | |
| 199 | base->utxd[0] = c; |
| 200 | |
| 201 | /* If \n, also do \r */ |
| 202 | if (c == '\n') |
| 203 | serial_putc ('\r'); |
| 204 | } |
| 205 | |
| 206 | /* |
| 207 | * Test whether a character is in the RX buffer |
| 208 | */ |
| 209 | int serial_tstc (void) |
| 210 | { |
| 211 | volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; |
| 212 | |
| 213 | /* If receive fifo is empty, return false */ |
| 214 | if (base->uts & UTS_RXEMPTY) |
| 215 | return 0; |
| 216 | return 1; |
| 217 | } |
| 218 | |
| 219 | void |
| 220 | serial_puts (const char *s) |
| 221 | { |
| 222 | while (*s) { |
| 223 | serial_putc (*s++); |
| 224 | } |
| 225 | } |
| 226 | #endif /* CONFIG_IMX_SERIAL_NONE */ |
| 227 | #endif /* defined CONFIG_IMX */ |