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Stefan Roese5e7abce2010-09-11 09:31:43 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5e7abce2010-09-11 09:31:43 +02006 */
7
8#ifndef _PPC440GP_H_
9#define _PPC440GP_H_
10
11#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
12
13/*
14 * Some SoC specific registers (not common for all 440 SoC's)
15 */
Stefan Roese550650d2010-09-20 16:05:31 +020016
17/* Memory mapped register */
18#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
19
20#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
21#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
22
23#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
Stefan Roese5e7abce2010-09-11 09:31:43 +020024
25#define SDR0_PCI0 0x0300
26
27#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
28#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
29
30#define CNTRL_DCR_BASE 0x0b0
31
32#define CPC0_SYS0 (CNTRL_DCR_BASE + 0x30) /* System configuration reg 0 */
33#define CPC0_SYS1 (CNTRL_DCR_BASE + 0x31) /* System configuration reg 1 */
34
35#define CPC0_STRP0 (CNTRL_DCR_BASE + 0x34) /* Power-on config reg 0 (RO) */
36#define CPC0_STRP1 (CNTRL_DCR_BASE + 0x35) /* Power-on config reg 1 (RO) */
37
38#define CPC0_GPIO (CNTRL_DCR_BASE + 0x38) /* GPIO config reg (440GP) */
39
40#define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */
41#define CPC0_CR1 (CNTRL_DCR_BASE + 0x3a) /* Control 1 register */
42
43#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
44#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
45#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
46#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
47#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
48#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
49#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
50#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
51#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
52#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
53#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
54#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
55
56#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
57#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
58
59#endif /* _PPC440GP_H_ */