blob: 1ebbc4c9e254ae450541650acd99d92b02fe1a22 [file] [log] [blame]
rickb841b6e2017-05-18 14:37:53 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/arch-ae3xx/ae3xx.h>
13
14/*
15 * CPU and Board Configuration Options
16 */
17#define CONFIG_USE_INTERRUPT
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21#define CONFIG_SKIP_TRUNOFF_WATCHDOG
22
ricke336b732017-08-29 10:12:02 +080023#define CONFIG_ARCH_MAP_SYSMEM
rickb841b6e2017-05-18 14:37:53 +080024
25#define CONFIG_BOOTP_SEND_HOSTNAME
26#define CONFIG_BOOTP_SERVERIP
27
28#ifdef CONFIG_SKIP_LOWLEVEL_INIT
rickb841b6e2017-05-18 14:37:53 +080029#ifdef CONFIG_OF_CONTROL
30#undef CONFIG_OF_SEPARATE
31#define CONFIG_OF_EMBED
32#endif
rickb841b6e2017-05-18 14:37:53 +080033#endif
34
35/*
36 * Timer
37 */
38#define CONFIG_SYS_CLK_FREQ 39062500
39#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
40
41/*
42 * Use Externel CLOCK or PCLK
43 */
44#undef CONFIG_FTRTC010_EXTCLK
45
46#ifndef CONFIG_FTRTC010_EXTCLK
47#define CONFIG_FTRTC010_PCLK
48#endif
49
50#ifdef CONFIG_FTRTC010_EXTCLK
51#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
52#else
53#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
54#endif
55
56#define TIMER_LOAD_VAL 0xffffffff
57
58/*
59 * Real Time Clock
60 */
61#define CONFIG_RTC_FTRTC010
62
63/*
64 * Real Time Clock Divider
65 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
66 */
67#define OSC_5MHZ (5*1000000)
68#define OSC_CLK (4*OSC_5MHZ)
69#define RTC_DIV_COUNT (0.5) /* Why?? */
70
71/*
72 * Serial console configuration
73 */
74
75/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
rickb841b6e2017-05-18 14:37:53 +080076#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
78#ifndef CONFIG_DM_SERIAL
79#define CONFIG_SYS_NS16550_REG_SIZE -4
80#endif
81#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
82
83/*
rickb841b6e2017-05-18 14:37:53 +080084 * Miscellaneous configurable options
85 */
rickb841b6e2017-05-18 14:37:53 +080086
rickb841b6e2017-05-18 14:37:53 +080087/*
88 * Size of malloc() pool
89 */
90/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
91#define CONFIG_SYS_MALLOC_LEN (512 << 10)
92
93/*
94 * Physical Memory Map
95 */
96#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
97
98#define PHYS_SDRAM_1 \
99 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
100
101#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
102
103#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
104#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
105
106#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
107
108#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
109 GENERATED_GBL_DATA_SIZE)
110
111/*
112 * Load address and memory test area should agree with
113 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
114 */
115#define CONFIG_SYS_LOAD_ADDR 0x300000
116
117/* memtest works on 63 MB in DRAM */
118#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
119#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
120
121/*
122 * Static memory controller configuration
123 */
124#define CONFIG_FTSMC020
125
126#ifdef CONFIG_FTSMC020
127#include <faraday/ftsmc020.h>
128
129#define CONFIG_SYS_FTSMC020_CONFIGS { \
130 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
131 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
132}
133
134#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
135#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
136 FTSMC020_BANK_SIZE_32M | \
137 FTSMC020_BANK_MBW_32)
138
139#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
140 FTSMC020_TPR_AST(1) | \
141 FTSMC020_TPR_CTW(1) | \
142 FTSMC020_TPR_ATI(1) | \
143 FTSMC020_TPR_AT2(1) | \
144 FTSMC020_TPR_WTC(1) | \
145 FTSMC020_TPR_AHT(1) | \
146 FTSMC020_TPR_TRNA(1))
147#endif
148
149/*
150 * FLASH on ADP_AG101P is connected to BANK0
151 * Just disalbe the other BANK to avoid detection error.
152 */
153#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
154 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
155 FTSMC020_BANK_SIZE_32M | \
156 FTSMC020_BANK_MBW_32)
157
158#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
159 FTSMC020_TPR_CTW(3) | \
160 FTSMC020_TPR_ATI(0xf) | \
161 FTSMC020_TPR_AT2(3) | \
162 FTSMC020_TPR_WTC(3) | \
163 FTSMC020_TPR_AHT(3) | \
164 FTSMC020_TPR_TRNA(0xf))
165
166#define FTSMC020_BANK1_CONFIG (0x00)
167#define FTSMC020_BANK1_TIMING (0x00)
168#endif /* CONFIG_FTSMC020 */
169
170/*
171 * FLASH and environment organization
172 */
173/* use CFI framework */
174#define CONFIG_SYS_FLASH_CFI
175#define CONFIG_FLASH_CFI_DRIVER
176
177#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
179#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
180
181/* support JEDEC */
182#ifdef CONFIG_CFI_FLASH
183#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
184#endif
185
186/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
187#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
188#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
189#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
190#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
191
192#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
193#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
194
195/* max number of memory banks */
196/*
197 * There are 4 banks supported for this Controller,
198 * but we have only 1 bank connected to flash on board
199 */
200#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
201#define CONFIG_SYS_MAX_FLASH_BANKS 1
202#endif
203#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
204
205/* max number of sectors on one chip */
206#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
rickb841b6e2017-05-18 14:37:53 +0800207#define CONFIG_SYS_MAX_FLASH_SECT 512
208
209/* environments */
rick7b1a50b2017-08-28 15:13:09 +0800210#define CONFIG_ENV_SPI_BUS 0
211#define CONFIG_ENV_SPI_CS 0
212#define CONFIG_ENV_SPI_MAX_HZ 50000000
213#define CONFIG_ENV_SPI_MODE 0
214#define CONFIG_ENV_SECT_SIZE 0x1000
215#define CONFIG_ENV_OFFSET 0x140000
rickb841b6e2017-05-18 14:37:53 +0800216#define CONFIG_ENV_SIZE 8192
217#define CONFIG_ENV_OVERWRITE
218
rick7b1a50b2017-08-28 15:13:09 +0800219
220/* SPI FLASH */
221#define CONFIG_SF_DEFAULT_BUS 0
222#define CONFIG_SF_DEFAULT_CS 0
223#define CONFIG_SF_DEFAULT_SPEED 1000000
224#define CONFIG_SF_DEFAULT_MODE 0
225
rickb841b6e2017-05-18 14:37:53 +0800226/*
227 * For booting Linux, the board info and command line data
228 * have to be in the first 16 MB of memory, since this is
229 * the maximum mapped by the Linux kernel during initialization.
230 */
231
232/* Initial Memory map for Linux*/
233#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
234/* Increase max gunzip size */
235#define CONFIG_SYS_BOOTM_LEN (64 << 20)
236
237#endif /* __CONFIG_H */