blob: e9cc274c7336ea3c5ef0f71399d0ed265c1f1b84 [file] [log] [blame]
Xie Xiaobo49f5bef2013-06-24 15:01:30 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
York Sun3aab0cd2013-08-12 14:57:12 -07004 * SPDX-License-Identifier: GPL-2.0+
Xie Xiaobo49f5bef2013-06-24 15:01:30 +08005 */
6
7/*
8 * QorIQ P1 Tower boards configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Ying Zhange838b0c2014-11-04 15:10:46 +080013#define CONFIG_SYS_GENERIC_BOARD
14#define CONFIG_DISPLAY_BOARDINFO
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080015#if defined(CONFIG_TWR_P1025)
16#define CONFIG_BOARDNAME "TWR-P1025"
17#define CONFIG_P1025
18#define CONFIG_PHY_ATHEROS
19#define CONFIG_QE
20#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
21#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
22#endif
23
24#ifdef CONFIG_SDCARD
25#define CONFIG_RAMBOOT_SDCARD
26#define CONFIG_SYS_RAMBOOT
27#define CONFIG_SYS_EXTRA_ENV_RELOC
28#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053029#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080030#endif
31
32#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053033#define CONFIG_SYS_TEXT_BASE 0xeff40000
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080034#endif
35
36#ifndef CONFIG_RESET_VECTOR_ADDRESS
37#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
38#endif
39
40#ifndef CONFIG_SYS_MONITOR_BASE
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42#endif
43
44/* High Level Configuration Options */
45#define CONFIG_BOOKE
46#define CONFIG_E500
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080047
48#define CONFIG_MP
49
50#define CONFIG_FSL_ELBC
51#define CONFIG_PCI
52#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
53#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
54#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
55#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
56#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
57#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
58
59#define CONFIG_FSL_LAW
60#define CONFIG_TSEC_ENET /* tsec ethernet support */
61#define CONFIG_ENV_OVERWRITE
62
63#define CONFIG_CMD_SATA
64#define CONFIG_SATA_SIL3114
65#define CONFIG_SYS_SATA_MAX_DEVICE 2
66#define CONFIG_LIBATA
67#define CONFIG_LBA48
68
69#ifndef __ASSEMBLY__
70extern unsigned long get_board_sys_clk(unsigned long dummy);
71#endif
72#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
73
74#define CONFIG_DDR_CLK_FREQ 66666666
75
76#define CONFIG_HWCONFIG
77/*
78 * These can be toggled for performance analysis, otherwise use default.
79 */
80#define CONFIG_L2_CACHE
81#define CONFIG_BTB
82
83#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
84
85#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
86#define CONFIG_SYS_MEMTEST_END 0x1fffffff
87#define CONFIG_PANIC_HANG /* do not reset board on panic */
88
89#define CONFIG_SYS_CCSRBAR 0xffe00000
90#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
91
92/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070093#define CONFIG_SYS_FSL_DDR3
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080094
95#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
96#define CONFIG_CHIP_SELECTS_PER_CTRL 1
97
98#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
99#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
101
102#define CONFIG_NUM_DDR_CONTROLLERS 1
103#define CONFIG_DIMM_SLOTS_PER_CTLR 1
104
105/* Default settings for DDR3 */
106#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
107#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
108#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
109#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
110#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
111#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
112
113#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
115#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
116#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
117
118#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
119#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
120#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
121#define CONFIG_SYS_DDR_RCW_1 0x00000000
122#define CONFIG_SYS_DDR_RCW_2 0x00000000
123#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
124#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
125#define CONFIG_SYS_DDR_TIMING_4 0x00220001
126#define CONFIG_SYS_DDR_TIMING_5 0x03402400
127
128#define CONFIG_SYS_DDR_TIMING_3 0x00020000
129#define CONFIG_SYS_DDR_TIMING_0 0x00220004
130#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
131#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
132#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
133#define CONFIG_SYS_DDR_MODE_1 0x80461320
134#define CONFIG_SYS_DDR_MODE_2 0x00008000
135#define CONFIG_SYS_DDR_INTERVAL 0x09480000
136
137/*
138 * Memory map
139 *
140 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
141 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
142 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
143 *
144 * Localbus
145 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
146 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
147 *
148 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
149 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
150 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
151 */
152
153/*
154 * Local Bus Definitions
155 */
156#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
157#define CONFIG_SYS_FLASH_BASE 0xec000000
158
159#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
160
161#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
162 | BR_PS_16 | BR_V)
163
164#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
165
166#define CONFIG_SYS_SSD_BASE 0xe0000000
167#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
168#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
169 BR_PS_16 | BR_V)
170#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
171 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
172 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
173
174#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
175#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
176
177#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
178#define CONFIG_SYS_FLASH_QUIET_TEST
179#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
180
181#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
182
183#undef CONFIG_SYS_FLASH_CHECKSUM
184#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
185#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
186
187#define CONFIG_FLASH_CFI_DRIVER
188#define CONFIG_SYS_FLASH_CFI
189#define CONFIG_SYS_FLASH_EMPTY_INFO
190#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
191
192#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
193
194#define CONFIG_SYS_INIT_RAM_LOCK
195#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
196/* Initial L1 address */
197#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
198#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
199#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
200/* Size of used area in RAM */
201#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
202
203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
204 GENERATED_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530207#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800208#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
209
210#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
211#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
212
213/* Serial Port
214 * open - index 2
215 * shorted - index 1
216 */
217#define CONFIG_CONS_INDEX 1
218#undef CONFIG_SERIAL_SOFTWARE_FIFO
219#define CONFIG_SYS_NS16550
220#define CONFIG_SYS_NS16550_SERIAL
221#define CONFIG_SYS_NS16550_REG_SIZE 1
222#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
223
224#define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
226
227#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
229
230/* Use the HUSH parser */
231#define CONFIG_SYS_HUSH_PARSER
232#ifdef CONFIG_SYS_HUSH_PARSER
233#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
234#endif
235
236/*
237 * Pass open firmware flat tree
238 */
239#define CONFIG_OF_LIBFDT
240#define CONFIG_OF_BOARD_SETUP
241#define CONFIG_OF_STDOUT_VIA_ALIAS
242
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800243/* new uImage format support */
244#define CONFIG_FIT
245#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
246
247/* I2C */
248#define CONFIG_SYS_I2C
249#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
250#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
251#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
252#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
253#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
254
255/*
256 * I2C2 EEPROM
257 */
258#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
259#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
260#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
261
262#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
263
264/* enable read and write access to EEPROM */
265#define CONFIG_CMD_EEPROM
266#define CONFIG_SYS_I2C_MULTI_EEPROMS
267#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
268#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
269#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
270
271/*
272 * eSPI - Enhanced SPI
273 */
274#define CONFIG_HARD_SPI
275#define CONFIG_FSL_ESPI
276
277#if defined(CONFIG_PCI)
278/*
279 * General PCI
280 * Memory space is mapped 1-1, but I/O space must start from 0.
281 */
282
283/* controller 2, direct to uli, tgtid 2, Base address 9000 */
284#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
285#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
286#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
287#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
288#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
289#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
290#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
291#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
292#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
293
294/* controller 1, tgtid 1, Base address a000 */
295#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
296#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
297#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
298#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
299#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
300#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
301#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
302#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
303#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
304
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800305#define CONFIG_PCI_PNP /* do pci plug-and-play */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800306#define CONFIG_CMD_PCI
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800307
308#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
309#define CONFIG_DOS_PARTITION
310#endif /* CONFIG_PCI */
311
312#if defined(CONFIG_TSEC_ENET)
313
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800314#define CONFIG_MII /* MII PHY management */
315#define CONFIG_TSEC1
316#define CONFIG_TSEC1_NAME "eTSEC1"
317#undef CONFIG_TSEC2
318#undef CONFIG_TSEC2_NAME
319#define CONFIG_TSEC3
320#define CONFIG_TSEC3_NAME "eTSEC3"
321
322#define TSEC1_PHY_ADDR 2
323#define TSEC2_PHY_ADDR 0
324#define TSEC3_PHY_ADDR 1
325
326#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
327#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
328#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
329
330#define TSEC1_PHYIDX 0
331#define TSEC2_PHYIDX 0
332#define TSEC3_PHYIDX 0
333
334#define CONFIG_ETHPRIME "eTSEC1"
335
336#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
337
338#define CONFIG_HAS_ETH0
339#define CONFIG_HAS_ETH1
340#undef CONFIG_HAS_ETH2
341#endif /* CONFIG_TSEC_ENET */
342
343#ifdef CONFIG_QE
344/* QE microcode/firmware address */
345#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800346#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800347#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
348#endif /* CONFIG_QE */
349
350#ifdef CONFIG_TWR_P1025
351/*
352 * QE UEC ethernet configuration
353 */
354#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
355
356#undef CONFIG_UEC_ETH
357#define CONFIG_PHY_MODE_NEED_CHANGE
358
359#define CONFIG_UEC_ETH1 /* ETH1 */
360#define CONFIG_HAS_ETH0
361
362#ifdef CONFIG_UEC_ETH1
363#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
364#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
365#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
366#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
367#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
368#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
369#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
370#endif /* CONFIG_UEC_ETH1 */
371
372#define CONFIG_UEC_ETH5 /* ETH5 */
373#define CONFIG_HAS_ETH1
374
375#ifdef CONFIG_UEC_ETH5
376#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
377#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
378#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
379#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
380#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
381#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
382#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
383#endif /* CONFIG_UEC_ETH5 */
384#endif /* CONFIG_TWR-P1025 */
385
386/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800387 * Dynamic MTD Partition support with mtdparts
388 */
389#define CONFIG_MTD_DEVICE
390#define CONFIG_MTD_PARTITIONS
391#define CONFIG_CMD_MTDPARTS
392#define CONFIG_FLASH_CFI_MTD
393#define MTDIDS_DEFAULT "nor0=ec000000.nor"
394#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
395 "256k(dtb),5632k(kernel),57856k(fs)," \
396 "256k(qe-ucode-firmware),1280k(u-boot)"
397
398/*
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800399 * Environment
400 */
401#ifdef CONFIG_SYS_RAMBOOT
402#ifdef CONFIG_RAMBOOT_SDCARD
403#define CONFIG_ENV_IS_IN_MMC
404#define CONFIG_ENV_SIZE 0x2000
405#define CONFIG_SYS_MMC_ENV_DEV 0
406#else
407#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
408#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
409#define CONFIG_ENV_SIZE 0x2000
410#endif
411#else
412#define CONFIG_ENV_IS_IN_FLASH
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800413#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800414#define CONFIG_ENV_SIZE 0x2000
415#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
416#endif
417
418#define CONFIG_LOADS_ECHO /* echo on for serial download */
419#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
420
421/*
422 * Command line configuration.
423 */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800424#define CONFIG_CMD_IRQ
425#define CONFIG_CMD_PING
426#define CONFIG_CMD_I2C
427#define CONFIG_CMD_MII
428#define CONFIG_CMD_ELF
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800429#define CONFIG_CMD_REGINFO
430
431/*
432 * USB
433 */
434#define CONFIG_HAS_FSL_DR_USB
435
436#if defined(CONFIG_HAS_FSL_DR_USB)
437#define CONFIG_USB_EHCI
438
439#ifdef CONFIG_USB_EHCI
440#define CONFIG_CMD_USB
441#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
442#define CONFIG_USB_EHCI_FSL
443#define CONFIG_USB_STORAGE
444#endif
445#endif
446
447#define CONFIG_MMC
448
449#ifdef CONFIG_MMC
450#define CONFIG_FSL_ESDHC
451#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
452#define CONFIG_CMD_MMC
453#define CONFIG_GENERIC_MMC
454#endif
455
456#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
457 || defined(CONFIG_FSL_SATA)
458#define CONFIG_CMD_EXT2
459#define CONFIG_CMD_FAT
460#define CONFIG_DOS_PARTITION
461#endif
462
463#undef CONFIG_WATCHDOG /* watchdog disabled */
464
465/*
466 * Miscellaneous configurable options
467 */
468#define CONFIG_SYS_LONGHELP /* undef to save memory */
469#define CONFIG_CMDLINE_EDITING /* Command-line editing */
470#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800471#if defined(CONFIG_CMD_KGDB)
472#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
473#else
474#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
475#endif
476#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
477 /* Print Buffer Size */
478#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
479#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800480
481/*
482 * For booting Linux, the board info and command line data
483 * have to be in the first 64 MB of memory, since this is
484 * the maximum mapped by the Linux kernel during initialization.
485 */
486#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
487#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
488
489/*
490 * Environment Configuration
491 */
492#define CONFIG_HOSTNAME unknown
493#define CONFIG_ROOTPATH "/opt/nfsroot"
494#define CONFIG_BOOTFILE "uImage"
495#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
496
497/* default location for tftp and bootm */
498#define CONFIG_LOADADDR 1000000
499
500#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
501#define CONFIG_BOOTARGS /* the boot command will set bootargs */
502
503#define CONFIG_BAUDRATE 115200
504
505#define CONFIG_EXTRA_ENV_SETTINGS \
506"netdev=eth0\0" \
507"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
508"loadaddr=1000000\0" \
509"bootfile=uImage\0" \
510"dtbfile=twr-p1025twr.dtb\0" \
511"ramdiskfile=rootfs.ext2.gz.uboot\0" \
512"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
513"tftpflash=tftpboot $loadaddr $uboot; " \
514 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
515 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
516 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
517 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
518 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
519"kernelflash=tftpboot $loadaddr $bootfile; " \
520 "protect off 0xefa80000 +$filesize; " \
521 "erase 0xefa80000 +$filesize; " \
522 "cp.b $loadaddr 0xefa80000 $filesize; " \
523 "protect on 0xefa80000 +$filesize; " \
524 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
525"dtbflash=tftpboot $loadaddr $dtbfile; " \
526 "protect off 0xefe80000 +$filesize; " \
527 "erase 0xefe80000 +$filesize; " \
528 "cp.b $loadaddr 0xefe80000 $filesize; " \
529 "protect on 0xefe80000 +$filesize; " \
530 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
531"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
532 "protect off 0xeeb80000 +$filesize; " \
533 "erase 0xeeb80000 +$filesize; " \
534 "cp.b $loadaddr 0xeeb80000 $filesize; " \
535 "protect on 0xeeb80000 +$filesize; " \
536 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
537"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
538 "protect off 0xefec0000 +$filesize; " \
539 "erase 0xefec0000 +$filesize; " \
540 "cp.b $loadaddr 0xefec0000 $filesize; " \
541 "protect on 0xefec0000 +$filesize; " \
542 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
543"consoledev=ttyS0\0" \
544"ramdiskaddr=2000000\0" \
545"ramdiskfile=rootfs.ext2.gz.uboot\0" \
546"fdtaddr=c00000\0" \
547"bdev=sda1\0" \
548"norbootaddr=ef080000\0" \
549"norfdtaddr=ef040000\0" \
550"ramdisk_size=120000\0" \
551"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
552"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
553
554#define CONFIG_NFSBOOTCOMMAND \
555"setenv bootargs root=/dev/nfs rw " \
556"nfsroot=$serverip:$rootpath " \
557"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
558"console=$consoledev,$baudrate $othbootargs;" \
559"tftp $loadaddr $bootfile&&" \
560"tftp $fdtaddr $fdtfile&&" \
561"bootm $loadaddr - $fdtaddr"
562
563#define CONFIG_HDBOOT \
564"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
565"console=$consoledev,$baudrate $othbootargs;" \
566"usb start;" \
567"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
568"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
569"bootm $loadaddr - $fdtaddr"
570
571#define CONFIG_USB_FAT_BOOT \
572"setenv bootargs root=/dev/ram rw " \
573"console=$consoledev,$baudrate $othbootargs " \
574"ramdisk_size=$ramdisk_size;" \
575"usb start;" \
576"fatload usb 0:2 $loadaddr $bootfile;" \
577"fatload usb 0:2 $fdtaddr $fdtfile;" \
578"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
579"bootm $loadaddr $ramdiskaddr $fdtaddr"
580
581#define CONFIG_USB_EXT2_BOOT \
582"setenv bootargs root=/dev/ram rw " \
583"console=$consoledev,$baudrate $othbootargs " \
584"ramdisk_size=$ramdisk_size;" \
585"usb start;" \
586"ext2load usb 0:4 $loadaddr $bootfile;" \
587"ext2load usb 0:4 $fdtaddr $fdtfile;" \
588"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
589"bootm $loadaddr $ramdiskaddr $fdtaddr"
590
591#define CONFIG_NORBOOT \
592"setenv bootargs root=/dev/mtdblock3 rw " \
593"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
594"bootm $norbootaddr - $norfdtaddr"
595
596#define CONFIG_RAMBOOTCOMMAND_TFTP \
597"setenv bootargs root=/dev/ram rw " \
598"console=$consoledev,$baudrate $othbootargs " \
599"ramdisk_size=$ramdisk_size;" \
600"tftp $ramdiskaddr $ramdiskfile;" \
601"tftp $loadaddr $bootfile;" \
602"tftp $fdtaddr $fdtfile;" \
603"bootm $loadaddr $ramdiskaddr $fdtaddr"
604
605#define CONFIG_RAMBOOTCOMMAND \
606"setenv bootargs root=/dev/ram rw " \
607"console=$consoledev,$baudrate $othbootargs " \
608"ramdisk_size=$ramdisk_size;" \
609"bootm 0xefa80000 0xeeb80000 0xefe80000"
610
611#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
612
613#endif /* __CONFIG_H */