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Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +09001/*
2 * Configuation settings for the sh7757lcr board
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +09007 */
8
9#ifndef __SH7757LCR_H
10#define __SH7757LCR_H
11
12#undef DEBUG
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090013#define CONFIG_CPU_SH7757 1
14#define CONFIG_SH7757LCR 1
Nobuhiro Iwamatsu3ed81642011-10-31 13:16:02 +090015#define CONFIG_SH7757LCR_DDR_ECC 1
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090016
17#define CONFIG_SYS_TEXT_BASE 0x8ef80000
18#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
19
Yoshihiro Shimoda0c2a37a2011-10-11 18:11:03 +090020#define CONFIG_CMD_MII
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090021#define CONFIG_CMD_PING
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090022#define CONFIG_CMD_SDRAM
23#define CONFIG_CMD_SF
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090024#define CONFIG_CMD_MD5SUM
25#define CONFIG_MD5
Yoshihiro Shimoda566f63d2012-03-05 20:11:12 +000026#define CONFIG_CMD_MMC
27#define CONFIG_CMD_EXT2
28#define CONFIG_DOS_PARTITION
29#define CONFIG_MAC_PARTITION
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090030
31#define CONFIG_BAUDRATE 115200
32#define CONFIG_BOOTDELAY 3
33#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
34
35#define CONFIG_VERSION_VARIABLE
36#undef CONFIG_SHOW_BOOT_PROGRESS
37
38/* MEMORY */
39#define SH7757LCR_SDRAM_BASE (0x80000000)
40#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
41#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
42#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
43
44#define CONFIG_SYS_LONGHELP
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090045#define CONFIG_SYS_CBSIZE 256
46#define CONFIG_SYS_PBSIZE 256
47#define CONFIG_SYS_MAXARGS 16
48#define CONFIG_SYS_BARGSIZE 512
49#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
50
51/* SCIF */
52#define CONFIG_SCIF_CONSOLE 1
53#define CONFIG_CONS_SCIF2 1
54#undef CONFIG_SYS_CONSOLE_INFO_QUIET
55#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
56#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
57
58#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
59#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
60 224 * 1024 * 1024)
61#undef CONFIG_SYS_ALT_MEMTEST
62#undef CONFIG_SYS_MEMTEST_SCRATCH
63#undef CONFIG_SYS_LOADS_BAUD_CHANGE
64
65#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
66#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
67#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
68 (128 + 16) * 1024 * 1024)
69
70#define CONFIG_SYS_MONITOR_BASE 0x00000000
71#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
72#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
73#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
74
75/* FLASH */
76#define CONFIG_SYS_NO_FLASH
77
78/* Ether */
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090079#define CONFIG_SH_ETHER 1
80#define CONFIG_SH_ETHER_USE_PORT 0
81#define CONFIG_SH_ETHER_PHY_ADDR 1
82#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
Yoshihiro Shimoda0c2a37a2011-10-11 18:11:03 +090083#define CONFIG_PHYLIB
84#define CONFIG_BITBANGMII
85#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsua80a6612012-05-16 10:23:21 +090086#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090087
88#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
89#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
90#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
91#define SH7757LCR_ETHERNET_MAC_SIZE 17
92#define SH7757LCR_ETHERNET_NUM_CH 2
Helmut Raiger9660e442011-10-20 04:19:47 +000093#define CONFIG_BOARD_LATE_INIT
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090094
95/* Gigabit Ether */
96#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
97
98/* SPI */
99#define CONFIG_SH_SPI 1
100#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +0900101#define CONFIG_SPI_FLASH_STMICRO 1
102
Yoshihiro Shimoda566f63d2012-03-05 20:11:12 +0000103/* MMCIF */
104#define CONFIG_MMC 1
105#define CONFIG_GENERIC_MMC 1
106#define CONFIG_SH_MMCIF 1
107#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
108#define CONFIG_SH_MMCIF_CLK 48000000
109
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +0900110/* SH7757 board */
111#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
112#define SH7757LCR_GRA_OFFSET 0x1f000000
113#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
114#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
115#define SH7757LCR_PCIEBRG_ADDR 0x00090000
116#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
117
118/* ENV setting */
119#define CONFIG_ENV_IS_EMBEDDED
120#define CONFIG_ENV_IS_IN_SPI_FLASH
121#define CONFIG_ENV_SECT_SIZE (64 * 1024)
122#define CONFIG_ENV_ADDR (0x00080000)
123#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
124#define CONFIG_ENV_OVERWRITE 1
125#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
126#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
127#define CONFIG_EXTRA_ENV_SETTINGS \
128 "netboot=bootp; bootm\0"
129
130/* Board Clock */
131#define CONFIG_SYS_CLK_FREQ 48000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900132#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
133#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +0900134#define CONFIG_SYS_TMU_CLK_DIV 4
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +0900135#endif /* __SH7757LCR_H */