blob: f540b15d6ce3bd15b59ef718c1e32080a96c9354 [file] [log] [blame]
Simon Glass97cb0922016-03-11 22:07:30 -07001/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _I915_REG_H_
9#define _I915_REG_H_
10
11/* Hotplug control (945+ only) */
12#define PORT_HOTPLUG_EN 0x61110
13#define HDMIB_HOTPLUG_INT_EN (1 << 29)
14#define DPB_HOTPLUG_INT_EN (1 << 29)
15#define HDMIC_HOTPLUG_INT_EN (1 << 28)
16#define DPC_HOTPLUG_INT_EN (1 << 28)
17#define HDMID_HOTPLUG_INT_EN (1 << 27)
18#define DPD_HOTPLUG_INT_EN (1 << 27)
19#define SDVOB_HOTPLUG_INT_EN (1 << 26)
20#define SDVOC_HOTPLUG_INT_EN (1 << 25)
21#define TV_HOTPLUG_INT_EN (1 << 18)
22#define CRT_HOTPLUG_INT_EN (1 << 9)
23#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
24#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
25/* must use period 64 on GM45 according to docs */
26#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
27#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
28#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
29#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
30#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
31#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
32#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
33#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
34#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
35#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
36#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
37#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
38
39/* Backlight control */
40#define BLC_PWM_CTL2 0x61250 /* 965+ only */
41#define BLM_PWM_ENABLE (1 << 31)
42#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
43#define BLM_PIPE_SELECT (1 << 29)
44#define BLM_PIPE_SELECT_IVB (3 << 29)
45#define BLM_PIPE_A (0 << 29)
46#define BLM_PIPE_B (1 << 29)
47#define BLM_PIPE_C (2 << 29) /* ivb + */
48#define BLM_PIPE(pipe) ((pipe) << 29)
49#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
50#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
51#define BLM_PHASE_IN_ENABLE (1 << 25)
52#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
53#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
54#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
55#define BLM_PHASE_IN_COUNT_SHIFT (8)
56#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
57#define BLM_PHASE_IN_INCR_SHIFT (0)
58#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
59#define BLC_PWM_CTL 0x61254
60/*
61 * This is the most significant 15 bits of the number of backlight cycles in a
62 * complete cycle of the modulated backlight control.
63 *
64 * The actual value is this field multiplied by two.
65 */
66#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
67#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
68#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
69/*
70 * This is the number of cycles out of the backlight modulation cycle for which
71 * the backlight is on.
72 *
73 * This field must be no greater than the number of cycles in the complete
74 * backlight modulation cycle.
75 */
76#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
77#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
78#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
79#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
80
81#define BLC_HIST_CTL 0x61260
82
83/*
84 * New registers for PCH-split platforms. Safe where new bits show up, the
85 * register layout machtes with gen4 BLC_PWM_CTL[12]
86 */
87#define BLC_PWM_CPU_CTL2 0x48250
88#define BLC_PWM2_ENABLE (1<<31)
89#define BLC_PWM_CPU_CTL 0x48254
90
91#define BLM_HIST_CTL 0x48260
92#define ENH_HIST_ENABLE (1<<31)
93#define ENH_MODIF_TBL_ENABLE (1<<30)
94#define ENH_PIPE_A_SELECT (0<<29)
95#define ENH_PIPE_B_SELECT (1<<29)
96#define ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
97#define HIST_MODE_YUV (0<<24)
98#define HIST_MODE_HSV (1<<24)
99#define ENH_MODE_DIRECT (0<<13)
100#define ENH_MODE_ADDITIVE (1<<13)
101#define ENH_MODE_MULTIPLICATIVE (2<<13)
102#define BIN_REGISTER_SET (1<<11)
103#define ENH_NUM_BINS 32
104
105#define BLM_HIST_ENH 0x48264
106
107#define BLM_HIST_GUARD_BAND 0x48268
108#define BLM_HIST_INTR_ENABLE (1<<31)
109#define BLM_HIST_EVENT_STATUS (1<<30)
110#define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)
111#define BLM_HIST_INTR_DELAY_SHIFT 22
112
113/*
114 * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
115 * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
116 */
117#define BLC_PWM_PCH_CTL1 0xc8250
118#define BLM_PCH_PWM_ENABLE (1 << 31)
119#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
120#define BLM_PCH_POLARITY (1 << 29)
121#define BLC_PWM_PCH_CTL2 0xc8254
122
123/* digital port hotplug */
124#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
125#define PORTD_HOTPLUG_ENABLE (1 << 20)
126#define PORTD_PULSE_DURATION_2ms (0)
127#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
128#define PORTD_PULSE_DURATION_6ms (2 << 18)
129#define PORTD_PULSE_DURATION_100ms (3 << 18)
130#define PORTD_PULSE_DURATION_MASK (3 << 18)
131#define PORTD_HOTPLUG_NO_DETECT (0)
132#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
133#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
134#define PORTC_HOTPLUG_ENABLE (1 << 12)
135#define PORTC_PULSE_DURATION_2ms (0)
136#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
137#define PORTC_PULSE_DURATION_6ms (2 << 10)
138#define PORTC_PULSE_DURATION_100ms (3 << 10)
139#define PORTC_PULSE_DURATION_MASK (3 << 10)
140#define PORTC_HOTPLUG_NO_DETECT (0)
141#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
142#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
143#define PORTB_HOTPLUG_ENABLE (1 << 4)
144#define PORTB_PULSE_DURATION_2ms (0)
145#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
146#define PORTB_PULSE_DURATION_6ms (2 << 2)
147#define PORTB_PULSE_DURATION_100ms (3 << 2)
148#define PORTB_PULSE_DURATION_MASK (3 << 2)
149#define PORTB_HOTPLUG_NO_DETECT (0)
150#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
151#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
152
153#define PCH_GPIOA 0xc5010
154#define PCH_GPIOB 0xc5014
155#define PCH_GPIOC 0xc5018
156#define PCH_GPIOD 0xc501c
157#define PCH_GPIOE 0xc5020
158#define PCH_GPIOF 0xc5024
159
160#define PCH_GMBUS0 0xc5100
161#define PCH_GMBUS1 0xc5104
162#define PCH_GMBUS2 0xc5108
163#define PCH_GMBUS3 0xc510c
164#define PCH_GMBUS4 0xc5110
165#define PCH_GMBUS5 0xc5120
166
167#define _PCH_DPLL_A 0xc6014
168#define _PCH_DPLL_B 0xc6018
169#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
170
171#define _PCH_FPA0 0xc6040
172#define FP_CB_TUNE (0x3<<22)
173#define _PCH_FPA1 0xc6044
174#define _PCH_FPB0 0xc6048
175#define _PCH_FPB1 0xc604c
176#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
177#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
178
179#define PCH_DPLL_TEST 0xc606c
180
181#define PCH_DREF_CONTROL 0xC6200
182#define DREF_CONTROL_MASK 0x7fc3
183#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
184#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
185#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
186#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
187#define DREF_SSC_SOURCE_DISABLE (0<<11)
188#define DREF_SSC_SOURCE_ENABLE (2<<11)
189#define DREF_SSC_SOURCE_MASK (3<<11)
190#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
191#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
192#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
193#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
194#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
195#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
196#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
197#define DREF_SSC4_DOWNSPREAD (0<<6)
198#define DREF_SSC4_CENTERSPREAD (1<<6)
199#define DREF_SSC1_DISABLE (0<<1)
200#define DREF_SSC1_ENABLE (1<<1)
201#define DREF_SSC4_DISABLE (0)
202#define DREF_SSC4_ENABLE (1)
203
204#define PCH_RAWCLK_FREQ 0xc6204
205#define FDL_TP1_TIMER_SHIFT 12
206#define FDL_TP1_TIMER_MASK (3<<12)
207#define FDL_TP2_TIMER_SHIFT 10
208#define FDL_TP2_TIMER_MASK (3<<10)
209#define RAWCLK_FREQ_MASK 0x3ff
210
211#define PCH_DPLL_TMR_CFG 0xc6208
212
213#define PCH_SSC4_PARMS 0xc6210
214#define PCH_SSC4_AUX_PARMS 0xc6214
215
216#define PCH_DPLL_SEL 0xc7000
217#define TRANSA_DPLL_ENABLE (1<<3)
218#define TRANSA_DPLLB_SEL (1<<0)
219#define TRANSA_DPLLA_SEL 0
220#define TRANSB_DPLL_ENABLE (1<<7)
221#define TRANSB_DPLLB_SEL (1<<4)
222#define TRANSB_DPLLA_SEL (0)
223#define TRANSC_DPLL_ENABLE (1<<11)
224#define TRANSC_DPLLB_SEL (1<<8)
225#define TRANSC_DPLLA_SEL (0)
226
227/* transcoder */
228
229#define _TRANS_HTOTAL_A 0xe0000
230#define TRANS_HTOTAL_SHIFT 16
231#define TRANS_HACTIVE_SHIFT 0
232#define _TRANS_HBLANK_A 0xe0004
233#define TRANS_HBLANK_END_SHIFT 16
234#define TRANS_HBLANK_START_SHIFT 0
235#define _TRANS_HSYNC_A 0xe0008
236#define TRANS_HSYNC_END_SHIFT 16
237#define TRANS_HSYNC_START_SHIFT 0
238#define _TRANS_VTOTAL_A 0xe000c
239#define TRANS_VTOTAL_SHIFT 16
240#define TRANS_VACTIVE_SHIFT 0
241#define _TRANS_VBLANK_A 0xe0010
242#define TRANS_VBLANK_END_SHIFT 16
243#define TRANS_VBLANK_START_SHIFT 0
244#define _TRANS_VSYNC_A 0xe0014
245#define TRANS_VSYNC_END_SHIFT 16
246#define TRANS_VSYNC_START_SHIFT 0
247#define _TRANS_VSYNCSHIFT_A 0xe0028
248
249#define _TRANSA_DATA_M1 0xe0030
250#define _TRANSA_DATA_N1 0xe0034
251#define _TRANSA_DATA_M2 0xe0038
252#define _TRANSA_DATA_N2 0xe003c
253#define _TRANSA_DP_LINK_M1 0xe0040
254#define _TRANSA_DP_LINK_N1 0xe0044
255#define _TRANSA_DP_LINK_M2 0xe0048
256#define _TRANSA_DP_LINK_N2 0xe004c
257
258/* Per-transcoder DIP controls */
259
260#define _VIDEO_DIP_CTL_A 0xe0200
261#define _VIDEO_DIP_DATA_A 0xe0208
262#define _VIDEO_DIP_GCP_A 0xe0210
263
264#define _VIDEO_DIP_CTL_B 0xe1200
265#define _VIDEO_DIP_DATA_B 0xe1208
266#define _VIDEO_DIP_GCP_B 0xe1210
267
268#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
269#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
270#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
271
272#define VLV_VIDEO_DIP_CTL_A 0x60200
273#define VLV_VIDEO_DIP_DATA_A 0x60208
274#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
275
276#define VLV_VIDEO_DIP_CTL_B 0x61170
277#define VLV_VIDEO_DIP_DATA_B 0x61174
278#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
279
280#define VLV_TVIDEO_DIP_CTL(pipe) \
281 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
282#define VLV_TVIDEO_DIP_DATA(pipe) \
283 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
284#define VLV_TVIDEO_DIP_GCP(pipe) \
285 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
286
287/* vlv has 2 sets of panel control regs. */
288#define PIPEA_PP_STATUS 0x61200
289#define PIPEA_PP_CONTROL 0x61204
290#define PIPEA_PP_ON_DELAYS 0x61208
291#define PIPEA_PP_OFF_DELAYS 0x6120c
292#define PIPEA_PP_DIVISOR 0x61210
293
294#define PIPEB_PP_STATUS 0x61300
295#define PIPEB_PP_CONTROL 0x61304
296#define PIPEB_PP_ON_DELAYS 0x61308
297#define PIPEB_PP_OFF_DELAYS 0x6130c
298#define PIPEB_PP_DIVISOR 0x61310
299
300#define PCH_PP_STATUS 0xc7200
301#define PCH_PP_CONTROL 0xc7204
302#define PANEL_UNLOCK_REGS (0xabcd << 16)
303#define PANEL_UNLOCK_MASK (0xffff << 16)
304#define EDP_FORCE_VDD (1 << 3)
305#define EDP_BLC_ENABLE (1 << 2)
306#define PANEL_POWER_RESET (1 << 1)
307#define PANEL_POWER_OFF (0 << 0)
308#define PANEL_POWER_ON (1 << 0)
309#define PCH_PP_ON_DELAYS 0xc7208
310#define PANEL_PORT_SELECT_MASK (3 << 30)
311#define PANEL_PORT_SELECT_LVDS (0 << 30)
312#define PANEL_PORT_SELECT_DPA (1 << 30)
313#define EDP_PANEL (1 << 30)
314#define PANEL_PORT_SELECT_DPC (2 << 30)
315#define PANEL_PORT_SELECT_DPD (3 << 30)
316#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
317#define PANEL_POWER_UP_DELAY_SHIFT 16
318#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
319#define PANEL_LIGHT_ON_DELAY_SHIFT 0
320
321#define PCH_PP_OFF_DELAYS 0xc720c
322#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
323#define PANEL_POWER_PORT_LVDS (0 << 30)
324#define PANEL_POWER_PORT_DP_A (1 << 30)
325#define PANEL_POWER_PORT_DP_C (2 << 30)
326#define PANEL_POWER_PORT_DP_D (3 << 30)
327#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
328#define PANEL_POWER_DOWN_DELAY_SHIFT 16
329#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
330#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
331
332#define PCH_PP_DIVISOR 0xc7210
333#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
334#define PP_REFERENCE_DIVIDER_SHIFT 8
335#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
336#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
337
338#define PCH_DP_B 0xe4100
339#define PCH_DPB_AUX_CH_CTL 0xe4110
340#define PCH_DPB_AUX_CH_DATA1 0xe4114
341#define PCH_DPB_AUX_CH_DATA2 0xe4118
342#define PCH_DPB_AUX_CH_DATA3 0xe411c
343#define PCH_DPB_AUX_CH_DATA4 0xe4120
344#define PCH_DPB_AUX_CH_DATA5 0xe4124
345
346#define PCH_DP_C 0xe4200
347#define PCH_DPC_AUX_CH_CTL 0xe4210
348#define PCH_DPC_AUX_CH_DATA1 0xe4214
349#define PCH_DPC_AUX_CH_DATA2 0xe4218
350#define PCH_DPC_AUX_CH_DATA3 0xe421c
351#define PCH_DPC_AUX_CH_DATA4 0xe4220
352#define PCH_DPC_AUX_CH_DATA5 0xe4224
353
354#define PCH_DP_D 0xe4300
355#define PCH_DPD_AUX_CH_CTL 0xe4310
356#define PCH_DPD_AUX_CH_DATA1 0xe4314
357#define PCH_DPD_AUX_CH_DATA2 0xe4318
358#define PCH_DPD_AUX_CH_DATA3 0xe431c
359#define PCH_DPD_AUX_CH_DATA4 0xe4320
360#define PCH_DPD_AUX_CH_DATA5 0xe4324
361
362#endif /* _I915_REG_H_ */