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Eugen Hristevf0854522018-07-06 11:15:10 +03001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
Eugen Hristevb6a8cce2021-08-17 13:29:23 +03004 * SAMA5D2 Industrial Connectivity Platform
Eugen Hristevf0854522018-07-06 11:15:10 +03005 *
6 * Copyright (c) 2018, Microchip Technology Inc.
7 * 2018, Eugen Hristev <eugen.hristev@microchip.com>
8 */
9/dts-v1/;
10#include "sama5d2.dtsi"
11#include "sama5d2-pinfunc.h"
12
13/ {
14 model = "Microchip SAMA5D2 ICP";
15 compatible = "atmel,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
16
17 aliases {
18 serial0 = &uart0;
19 i2c1 = &i2c1;
20 };
21
22 chosen {
23 stdout-path = "serial0:115200n8";
24 };
25
26 ahb {
27
28 sdmmc0: sdio-host@a0000000 {
29 bus-width = <4>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_sdmmc0_default>;
32 status = "okay";
33 };
34
35 apb {
Mihai Sain5b435082021-08-17 13:29:22 +030036
37 qspi1: spi@f0024000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
40 status = "okay";
41
42 flash@0 {
43 compatible = "jedec,spi-nor";
44 reg = <0>;
45 spi-max-frequency = <83000000>;
46 spi-rx-bus-width = <4>;
47 spi-tx-bus-width = <4>;
48 };
49 };
50
Razvan Stefanescufe5963d2018-12-12 12:42:05 +020051 macb0: ethernet@f8008000 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
54 phy-mode = "internal";
55 status = "okay";
56 };
57
Eugen Hristevb6a8cce2021-08-17 13:29:23 +030058 uart0: serial@f801c000 { /* mikrobus1 uart */
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_mikrobus1_uart>;
61 status = "okay";
62 };
63
Eugen Hristevf0854522018-07-06 11:15:10 +030064 i2c1: i2c@fc028000 {
65 dmas = <0>, <0>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_i2c1_default>;
68 status = "okay";
69
70 eeprom@50 {
Eugen Hristevbb5eedb2020-12-07 09:30:59 +020071 compatible = "microchip,24aa02e48";
Eugen Hristevf0854522018-07-06 11:15:10 +030072 reg = <0x50>;
73 pagesize = <16>;
74 };
75
76 eeprom@52 {
Eugen Hristevbb5eedb2020-12-07 09:30:59 +020077 compatible = "microchip,24aa02e48";
Eugen Hristevf0854522018-07-06 11:15:10 +030078 reg = <0x52>;
79 pagesize = <16>;
80 };
81
82 eeprom@53 {
Eugen Hristevbb5eedb2020-12-07 09:30:59 +020083 compatible = "microchip,24aa02e48";
Eugen Hristevf0854522018-07-06 11:15:10 +030084 reg = <0x53>;
85 pagesize = <16>;
86 };
87 };
Eugen Hristevb6a8cce2021-08-17 13:29:23 +030088
Eugen Hristevf0854522018-07-06 11:15:10 +030089 pioA: gpio@fc038000 {
90 status = "okay";
91 pinctrl {
92 pinctrl_i2c1_default: i2c1_default {
93 pinmux = <PIN_PD19__TWD1>,
94 <PIN_PD20__TWCK1>;
95 bias-disable;
96 };
97
Razvan Stefanescufe5963d2018-12-12 12:42:05 +020098 pinctrl_macb0_rmii: macb0_rmii {
99 pinmux = <PIN_PD1__GRXCK>,
100 <PIN_PD2__GTXER>,
101 <PIN_PD5__GRX2>,
102 <PIN_PD6__GRX3>,
103 <PIN_PD7__GTX2>,
104 <PIN_PD8__GTX3>,
105 <PIN_PD9__GTXCK>,
106 <PIN_PD10__GTXEN>,
107 <PIN_PD11__GRXDV>,
108 <PIN_PD12__GRXER>,
109 <PIN_PD13__GRX0>,
110 <PIN_PD14__GRX1>,
111 <PIN_PD15__GTX0>,
112 <PIN_PD16__GTX1>,
113 <PIN_PD17__GMDC>,
114 <PIN_PD18__GMDIO>;
115 bias-disable;
116 };
117
118 pinctrl_macb0_phy_irq: macb0_phy_irq {
119 pinmux = <PIN_PD3__GPIO>;
120 bias-disable;
121 };
122
123 pinctrl_macb0_rst: macb0_sw_rst {
124 pinmux = <PIN_PD4__GPIO>;
125 bias-pull-up;
126 };
127
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300128 pinctrl_mikrobus1_uart: mikrobus1_uart {
129 pinmux = <PIN_PB26__URXD0>,
130 <PIN_PB27__UTXD0>;
131 bias-disable;
132 };
133
Mihai Sain5b435082021-08-17 13:29:22 +0300134 pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
135 pinmux = <PIN_PA6__QSPI1_SCK>,
136 <PIN_PA11__QSPI1_CS>;
137 bias-disable;
138 };
139
140 pinctrl_qspi1_dat_default: qspi1_dat_default {
141 pinmux = <PIN_PA7__QSPI1_IO0>,
142 <PIN_PA8__QSPI1_IO1>,
143 <PIN_PA9__QSPI1_IO2>,
144 <PIN_PA10__QSPI1_IO3>;
145 bias-pull-up;
146 };
147
Eugen Hristevf0854522018-07-06 11:15:10 +0300148 pinctrl_sdmmc0_default: sdmmc0_default {
149 pinmux = <PIN_PA1__SDMMC0_CMD>,
150 <PIN_PA2__SDMMC0_DAT0>,
151 <PIN_PA3__SDMMC0_DAT1>,
152 <PIN_PA4__SDMMC0_DAT2>,
153 <PIN_PA5__SDMMC0_DAT3>,
154 <PIN_PA0__SDMMC0_CK>,
155 <PIN_PA13__SDMMC0_CD>;
156 bias-disable;
157 };
Eugen Hristevf0854522018-07-06 11:15:10 +0300158 };
159 };
160 };
161 };
162};