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Lukasz Majewski1d7993d2019-06-24 15:50:45 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <malloc.h>
10#include <clk-uclass.h>
11#include <dm/device.h>
12#include <dm/uclass.h>
13#include <clk.h>
14#include "clk.h"
15
Giulio Benetti16faa592020-01-10 15:46:53 +010016#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
17#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020018
Giulio Benettif4b70942020-01-10 15:46:55 +010019#define BM_PLL_POWER (0x1 << 12)
20
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020021struct clk_pllv3 {
22 struct clk clk;
23 void __iomem *base;
Giulio Benettif4b70942020-01-10 15:46:55 +010024 u32 power_bit;
25 bool powerup_set;
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020026 u32 div_mask;
27 u32 div_shift;
28};
29
30#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
31
Giulio Benetti16faa592020-01-10 15:46:53 +010032static ulong clk_pllv3_generic_get_rate(struct clk *clk)
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020033{
34 struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
35 unsigned long parent_rate = clk_get_parent_rate(clk);
36
37 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
38
39 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
40}
41
Giulio Benettif4b70942020-01-10 15:46:55 +010042static int clk_pllv3_generic_enable(struct clk *clk)
43{
44 struct clk_pllv3 *pll = to_clk_pllv3(clk);
45 u32 val;
46
47 val = readl(pll->base);
48 if (pll->powerup_set)
49 val |= pll->power_bit;
50 else
51 val &= ~pll->power_bit;
52 writel(val, pll->base);
53
54 return 0;
55}
56
Giulio Benetticbb20012020-01-10 15:46:56 +010057static int clk_pllv3_generic_disable(struct clk *clk)
58{
59 struct clk_pllv3 *pll = to_clk_pllv3(clk);
60 u32 val;
61
62 val = readl(pll->base);
63 if (pll->powerup_set)
64 val &= ~pll->power_bit;
65 else
66 val |= pll->power_bit;
67 writel(val, pll->base);
68
69 return 0;
70}
71
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020072static const struct clk_ops clk_pllv3_generic_ops = {
Giulio Benetti16faa592020-01-10 15:46:53 +010073 .get_rate = clk_pllv3_generic_get_rate,
Giulio Benettif4b70942020-01-10 15:46:55 +010074 .enable = clk_pllv3_generic_enable,
Giulio Benetticbb20012020-01-10 15:46:56 +010075 .disable = clk_pllv3_generic_disable,
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020076};
77
78struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
79 const char *parent_name, void __iomem *base,
80 u32 div_mask)
81{
82 struct clk_pllv3 *pll;
83 struct clk *clk;
84 char *drv_name;
85 int ret;
86
87 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
88 if (!pll)
89 return ERR_PTR(-ENOMEM);
90
Giulio Benettif4b70942020-01-10 15:46:55 +010091 pll->power_bit = BM_PLL_POWER;
92
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020093 switch (type) {
94 case IMX_PLLV3_GENERIC:
Giulio Benetti16faa592020-01-10 15:46:53 +010095 drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
Giulio Benetti4abd8072020-01-10 15:46:54 +010096 pll->div_shift = 0;
Giulio Benettif4b70942020-01-10 15:46:55 +010097 pll->powerup_set = false;
Giulio Benetti16faa592020-01-10 15:46:53 +010098 break;
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020099 case IMX_PLLV3_USB:
Giulio Benetti16faa592020-01-10 15:46:53 +0100100 drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
Giulio Benetti4abd8072020-01-10 15:46:54 +0100101 pll->div_shift = 1;
Giulio Benettif4b70942020-01-10 15:46:55 +0100102 pll->powerup_set = true;
Lukasz Majewski1d7993d2019-06-24 15:50:45 +0200103 break;
104 default:
105 kfree(pll);
106 return ERR_PTR(-ENOTSUPP);
107 }
108
109 pll->base = base;
110 pll->div_mask = div_mask;
111 clk = &pll->clk;
112
113 ret = clk_register(clk, drv_name, name, parent_name);
114 if (ret) {
115 kfree(pll);
116 return ERR_PTR(ret);
117 }
118
119 return clk;
120}
121
122U_BOOT_DRIVER(clk_pllv3_generic) = {
Giulio Benetti16faa592020-01-10 15:46:53 +0100123 .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
124 .id = UCLASS_CLK,
125 .ops = &clk_pllv3_generic_ops,
126 .flags = DM_FLAG_PRE_RELOC,
127};
128
129U_BOOT_DRIVER(clk_pllv3_usb) = {
130 .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
Lukasz Majewski1d7993d2019-06-24 15:50:45 +0200131 .id = UCLASS_CLK,
132 .ops = &clk_pllv3_generic_ops,
133 .flags = DM_FLAG_PRE_RELOC,
134};