blob: e2340936fa62dd6f819a422aba290405e916b94d [file] [log] [blame]
Thomas Chouc960b132010-04-20 12:49:52 +08001/*
2 * Altera 10/100/1000 triple speed ethernet mac driver
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Thomas Chouc960b132010-04-20 12:49:52 +080011#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070012#include <cpu_func.h>
Thomas Chou96fa1e42015-10-22 15:29:11 +080013#include <dm.h>
14#include <errno.h>
15#include <fdt_support.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
Thomas Chou96fa1e42015-10-22 15:29:11 +080017#include <memalign.h>
18#include <miiphy.h>
Thomas Chouc960b132010-04-20 12:49:52 +080019#include <net.h>
Thomas Chouc960b132010-04-20 12:49:52 +080020#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060021#include <asm/global_data.h>
Masahiro Yamada9d86b892020-02-14 16:40:19 +090022#include <linux/dma-mapping.h>
Thomas Chou96fa1e42015-10-22 15:29:11 +080023#include <asm/io.h>
Thomas Chouc960b132010-04-20 12:49:52 +080024#include "altera_tse.h"
25
Thomas Chou96fa1e42015-10-22 15:29:11 +080026DECLARE_GLOBAL_DATA_PTR;
Thomas Chouc960b132010-04-20 12:49:52 +080027
Thomas Chou96fa1e42015-10-22 15:29:11 +080028static inline void alt_sgdma_construct_descriptor(
29 struct alt_sgdma_descriptor *desc,
30 struct alt_sgdma_descriptor *next,
31 void *read_addr,
32 void *write_addr,
Thomas Chou2cd0a522015-11-06 09:36:26 +080033 u16 length_or_eop,
Thomas Chouc960b132010-04-20 12:49:52 +080034 int generate_eop,
35 int read_fixed,
Thomas Chou96fa1e42015-10-22 15:29:11 +080036 int write_fixed_or_sop)
Thomas Chouc960b132010-04-20 12:49:52 +080037{
Thomas Chou2cd0a522015-11-06 09:36:26 +080038 u8 val;
Thomas Chou96fa1e42015-10-22 15:29:11 +080039
Thomas Chouc960b132010-04-20 12:49:52 +080040 /*
41 * Mark the "next" descriptor as "not" owned by hardware. This prevents
Thomas Chou96fa1e42015-10-22 15:29:11 +080042 * The SGDMA controller from continuing to process the chain.
Thomas Chouc960b132010-04-20 12:49:52 +080043 */
Thomas Chou96fa1e42015-10-22 15:29:11 +080044 next->descriptor_control = next->descriptor_control &
45 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
Thomas Chouc960b132010-04-20 12:49:52 +080046
Thomas Chou96fa1e42015-10-22 15:29:11 +080047 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
48 desc->source = virt_to_phys(read_addr);
49 desc->destination = virt_to_phys(write_addr);
50 desc->next = virt_to_phys(next);
Thomas Chouc960b132010-04-20 12:49:52 +080051 desc->bytes_to_transfer = length_or_eop;
Thomas Chouc960b132010-04-20 12:49:52 +080052
53 /*
54 * Set the descriptor control block as follows:
55 * - Set "owned by hardware" bit
56 * - Optionally set "generate EOP" bit
57 * - Optionally set the "read from fixed address" bit
58 * - Optionally set the "write to fixed address bit (which serves
59 * serves as a "generate SOP" control bit in memory-to-stream mode).
60 * - Set the 4-bit atlantic channel, if specified
61 *
62 * Note this step is performed after all other descriptor information
63 * has been filled out so that, if the controller already happens to be
64 * pointing at this descriptor, it will not run (via the "owned by
65 * hardware" bit) until all other descriptor has been set up.
66 */
Thomas Chou96fa1e42015-10-22 15:29:11 +080067 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
68 if (generate_eop)
69 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
70 if (read_fixed)
71 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
72 if (write_fixed_or_sop)
73 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
74 desc->descriptor_control = val;
Thomas Chouc960b132010-04-20 12:49:52 +080075}
76
Thomas Chou96fa1e42015-10-22 15:29:11 +080077static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
Thomas Chouc960b132010-04-20 12:49:52 +080078{
Thomas Chou96fa1e42015-10-22 15:29:11 +080079 int status;
80 ulong ctime;
Thomas Chouc960b132010-04-20 12:49:52 +080081
82 /* Wait for the descriptor (chain) to complete */
Thomas Chou96fa1e42015-10-22 15:29:11 +080083 ctime = get_timer(0);
84 while (1) {
85 status = readl(&regs->status);
86 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
Thomas Chouc960b132010-04-20 12:49:52 +080087 break;
Thomas Chou96fa1e42015-10-22 15:29:11 +080088 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
89 status = -ETIMEDOUT;
90 debug("sgdma timeout\n");
91 break;
92 }
Thomas Chouc960b132010-04-20 12:49:52 +080093 }
94
Thomas Chou96fa1e42015-10-22 15:29:11 +080095 /* Clear Run */
96 writel(0, &regs->control);
97 /* Clear status */
98 writel(0xff, &regs->status);
Thomas Chouc960b132010-04-20 12:49:52 +080099
Thomas Chou96fa1e42015-10-22 15:29:11 +0800100 return status;
101}
Joachim Foerster337aff52011-10-25 22:39:54 +0000102
Thomas Chou96fa1e42015-10-22 15:29:11 +0800103static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
104 struct alt_sgdma_descriptor *desc)
105{
Thomas Chou2cd0a522015-11-06 09:36:26 +0800106 u32 val;
Thomas Chouc960b132010-04-20 12:49:52 +0800107
108 /* Point the controller at the descriptor */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800109 writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
Thomas Chouc960b132010-04-20 12:49:52 +0800110
111 /*
112 * Set up SGDMA controller to:
113 * - Disable interrupt generation
114 * - Run once a valid descriptor is written to controller
115 * - Stop on an error with any particular descriptor
116 */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800117 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
118 writel(val, &regs->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800119
Thomas Chouc960b132010-04-20 12:49:52 +0800120 return 0;
121}
122
Thomas Chou96fa1e42015-10-22 15:29:11 +0800123static void tse_adjust_link(struct altera_tse_priv *priv,
124 struct phy_device *phydev)
Thomas Chouc960b132010-04-20 12:49:52 +0800125{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800126 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou2cd0a522015-11-06 09:36:26 +0800127 u32 refvar;
Thomas Chouc960b132010-04-20 12:49:52 +0800128
Thomas Chou96fa1e42015-10-22 15:29:11 +0800129 if (!phydev->link) {
130 debug("%s: No link.\n", phydev->dev->name);
131 return;
132 }
Thomas Chouc960b132010-04-20 12:49:52 +0800133
Thomas Chou96fa1e42015-10-22 15:29:11 +0800134 refvar = readl(&mac_dev->command_config);
135
136 if (phydev->duplex)
Thomas Chouc960b132010-04-20 12:49:52 +0800137 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
138 else
139 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
140
Thomas Chou96fa1e42015-10-22 15:29:11 +0800141 switch (phydev->speed) {
Thomas Chouc960b132010-04-20 12:49:52 +0800142 case 1000:
143 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
144 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
145 break;
146 case 100:
147 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
148 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
149 break;
150 case 10:
151 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
152 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
153 break;
154 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800155 writel(refvar, &mac_dev->command_config);
Thomas Chouc960b132010-04-20 12:49:52 +0800156}
157
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800158static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
Thomas Chouc960b132010-04-20 12:49:52 +0800159{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800160 struct altera_tse_priv *priv = dev_get_priv(dev);
161 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
Thomas Chouc960b132010-04-20 12:49:52 +0800162
Thomas Chou96fa1e42015-10-22 15:29:11 +0800163 alt_sgdma_construct_descriptor(
164 tx_desc,
165 tx_desc + 1,
166 packet, /* read addr */
167 NULL, /* write addr */
Thomas Chouc960b132010-04-20 12:49:52 +0800168 length, /* length or EOP ,will change for each tx */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800169 1, /* gen eop */
170 0, /* read fixed */
171 1 /* write fixed or sop */
Thomas Chouc960b132010-04-20 12:49:52 +0800172 );
Thomas Chouc960b132010-04-20 12:49:52 +0800173
174 /* send the packet */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800175 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
176 alt_sgdma_wait_transfer(priv->sgdma_tx);
177 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
178
179 return tx_desc->actual_bytes_transferred;
Thomas Chouc960b132010-04-20 12:49:52 +0800180}
181
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800182static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
183 uchar **packetp)
Thomas Chouc960b132010-04-20 12:49:52 +0800184{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800185 struct altera_tse_priv *priv = dev_get_priv(dev);
186 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
187 int packet_length;
Thomas Chouc960b132010-04-20 12:49:52 +0800188
Thomas Chou96fa1e42015-10-22 15:29:11 +0800189 if (rx_desc->descriptor_status &
Thomas Chouc960b132010-04-20 12:49:52 +0800190 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
Thomas Chou577662f2015-11-09 08:00:00 +0800191 alt_sgdma_wait_transfer(priv->sgdma_rx);
Thomas Chouc960b132010-04-20 12:49:52 +0800192 packet_length = rx_desc->actual_bytes_transferred;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800193 debug("recv %d bytes\n", packet_length);
194 *packetp = priv->rx_buf;
Joachim Foerster70d52f92011-10-17 05:24:46 +0000195
196 return packet_length;
Thomas Chouc960b132010-04-20 12:49:52 +0800197 }
198
Thomas Chou96fa1e42015-10-22 15:29:11 +0800199 return -EAGAIN;
Thomas Chouc960b132010-04-20 12:49:52 +0800200}
201
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800202static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
203 int length)
Thomas Chouc960b132010-04-20 12:49:52 +0800204{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800205 struct altera_tse_priv *priv = dev_get_priv(dev);
206 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800207
Thomas Chou96fa1e42015-10-22 15:29:11 +0800208 alt_sgdma_construct_descriptor(
209 rx_desc,
210 rx_desc + 1,
211 NULL, /* read addr */
212 priv->rx_buf, /* write addr */
213 0, /* length or EOP */
214 0, /* gen eop */
215 0, /* read fixed */
216 0 /* write fixed or sop */
217 );
218
219 /* setup the sgdma */
220 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
221 debug("recv setup\n");
222
223 return 0;
Thomas Chouc960b132010-04-20 12:49:52 +0800224}
225
Thomas Chouacd71c32015-11-08 10:57:05 +0800226static void altera_tse_stop_mac(struct altera_tse_priv *priv)
227{
228 struct alt_tse_mac *mac_dev = priv->mac_dev;
229 u32 status;
230 ulong ctime;
231
232 /* reset the mac */
233 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
234 ctime = get_timer(0);
235 while (1) {
236 status = readl(&mac_dev->command_config);
237 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
238 break;
239 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
240 debug("Reset mac timeout\n");
241 break;
242 }
243 }
244}
245
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800246static void altera_tse_stop_sgdma(struct udevice *dev)
Thomas Chouc960b132010-04-20 12:49:52 +0800247{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800248 struct altera_tse_priv *priv = dev_get_priv(dev);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800249 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
250 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
251 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800252 int ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800253
254 /* clear rx desc & wait for sgdma to complete */
255 rx_desc->descriptor_control = 0;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800256 writel(0, &rx_sgdma->control);
257 ret = alt_sgdma_wait_transfer(rx_sgdma);
258 if (ret == -ETIMEDOUT)
259 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
260 &rx_sgdma->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800261
Thomas Chou96fa1e42015-10-22 15:29:11 +0800262 writel(0, &tx_sgdma->control);
263 ret = alt_sgdma_wait_transfer(tx_sgdma);
264 if (ret == -ETIMEDOUT)
265 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
266 &tx_sgdma->control);
Thomas Chouc960b132010-04-20 12:49:52 +0800267}
268
Thomas Choue3e87262015-11-09 14:36:29 +0800269static void msgdma_reset(struct msgdma_csr *csr)
270{
271 u32 status;
272 ulong ctime;
273
274 /* Reset mSGDMA */
275 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
276 writel(MSGDMA_CSR_CTL_RESET, &csr->control);
277 ctime = get_timer(0);
278 while (1) {
279 status = readl(&csr->status);
280 if (!(status & MSGDMA_CSR_STAT_RESETTING))
281 break;
282 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
283 debug("Reset msgdma timeout\n");
284 break;
285 }
286 }
287 /* Clear status */
288 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
289}
290
291static u32 msgdma_wait(struct msgdma_csr *csr)
292{
293 u32 status;
294 ulong ctime;
295
296 /* Wait for the descriptor to complete */
297 ctime = get_timer(0);
298 while (1) {
299 status = readl(&csr->status);
300 if (!(status & MSGDMA_CSR_STAT_BUSY))
301 break;
302 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
303 debug("sgdma timeout\n");
304 break;
305 }
306 }
307 /* Clear status */
308 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
309
310 return status;
311}
312
313static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
314 int length)
315{
316 struct altera_tse_priv *priv = dev_get_priv(dev);
317 struct msgdma_extended_desc *desc = priv->tx_desc;
318 u32 tx_buf = virt_to_phys(packet);
319 u32 status;
320
321 writel(tx_buf, &desc->read_addr_lo);
322 writel(0, &desc->read_addr_hi);
323 writel(0, &desc->write_addr_lo);
324 writel(0, &desc->write_addr_hi);
325 writel(length, &desc->len);
326 writel(0, &desc->burst_seq_num);
327 writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
328 writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
329 status = msgdma_wait(priv->sgdma_tx);
330 debug("sent %d bytes, status %08x\n", length, status);
331
332 return 0;
333}
334
335static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
336 uchar **packetp)
337{
338 struct altera_tse_priv *priv = dev_get_priv(dev);
339 struct msgdma_csr *csr = priv->sgdma_rx;
340 struct msgdma_response *resp = priv->rx_resp;
341 u32 level, length, status;
342
343 level = readl(&csr->resp_fill_level);
344 if (level & 0xffff) {
345 length = readl(&resp->bytes_transferred);
346 status = readl(&resp->status);
347 debug("recv %d bytes, status %08x\n", length, status);
348 *packetp = priv->rx_buf;
349
350 return length;
351 }
352
353 return -EAGAIN;
354}
355
356static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
357 int length)
358{
359 struct altera_tse_priv *priv = dev_get_priv(dev);
360 struct msgdma_extended_desc *desc = priv->rx_desc;
361 u32 rx_buf = virt_to_phys(priv->rx_buf);
362
363 writel(0, &desc->read_addr_lo);
364 writel(0, &desc->read_addr_hi);
365 writel(rx_buf, &desc->write_addr_lo);
366 writel(0, &desc->write_addr_hi);
367 writel(PKTSIZE_ALIGN, &desc->len);
368 writel(0, &desc->burst_seq_num);
369 writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
370 writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
371 debug("recv setup\n");
372
373 return 0;
374}
375
376static void altera_tse_stop_msgdma(struct udevice *dev)
377{
378 struct altera_tse_priv *priv = dev_get_priv(dev);
379
380 msgdma_reset(priv->sgdma_rx);
381 msgdma_reset(priv->sgdma_tx);
382}
383
Thomas Chou96fa1e42015-10-22 15:29:11 +0800384static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Thomas Chouc960b132010-04-20 12:49:52 +0800385{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800386 struct altera_tse_priv *priv = bus->priv;
387 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou2cd0a522015-11-06 09:36:26 +0800388 u32 value;
Thomas Chouc960b132010-04-20 12:49:52 +0800389
Thomas Chou96fa1e42015-10-22 15:29:11 +0800390 /* set mdio address */
391 writel(addr, &mac_dev->mdio_phy1_addr);
392 /* get the data */
393 value = readl(&mac_dev->mdio_phy1[reg]);
Thomas Chouc960b132010-04-20 12:49:52 +0800394
Thomas Chou96fa1e42015-10-22 15:29:11 +0800395 return value & 0xffff;
Thomas Chouc960b132010-04-20 12:49:52 +0800396}
397
Thomas Chou96fa1e42015-10-22 15:29:11 +0800398static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
399 u16 val)
Thomas Chouc960b132010-04-20 12:49:52 +0800400{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800401 struct altera_tse_priv *priv = bus->priv;
402 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chouc960b132010-04-20 12:49:52 +0800403
Thomas Chou96fa1e42015-10-22 15:29:11 +0800404 /* set mdio address */
405 writel(addr, &mac_dev->mdio_phy1_addr);
406 /* set the data */
407 writel(val, &mac_dev->mdio_phy1[reg]);
Thomas Chouc960b132010-04-20 12:49:52 +0800408
Thomas Chou6c7c4442010-04-27 20:15:10 +0800409 return 0;
410}
411
Thomas Chou96fa1e42015-10-22 15:29:11 +0800412static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
Thomas Chouc960b132010-04-20 12:49:52 +0800413{
Thomas Chou96fa1e42015-10-22 15:29:11 +0800414 struct mii_dev *bus = mdio_alloc();
Thomas Chouc960b132010-04-20 12:49:52 +0800415
Thomas Chou96fa1e42015-10-22 15:29:11 +0800416 if (!bus) {
417 printf("Failed to allocate MDIO bus\n");
418 return -ENOMEM;
419 }
Thomas Chouc960b132010-04-20 12:49:52 +0800420
Thomas Chou96fa1e42015-10-22 15:29:11 +0800421 bus->read = tse_mdio_read;
422 bus->write = tse_mdio_write;
Ben Whitten192bc692015-12-30 13:05:58 +0000423 snprintf(bus->name, sizeof(bus->name), "%s", name);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800424
425 bus->priv = (void *)priv;
426
427 return mdio_register(bus);
428}
429
430static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
431{
432 struct phy_device *phydev;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800433
Marek Vasutfd591022023-05-31 00:51:19 +0200434 phydev = phy_connect(priv->bus, -1, dev, priv->interface);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800435 if (!phydev)
436 return -ENODEV;
437
Thomas Chou96fa1e42015-10-22 15:29:11 +0800438 phydev->supported &= PHY_GBIT_FEATURES;
439 phydev->advertising = phydev->supported;
440
441 priv->phydev = phydev;
442 phy_config(phydev);
443
444 return 0;
445}
446
447static int altera_tse_write_hwaddr(struct udevice *dev)
448{
449 struct altera_tse_priv *priv = dev_get_priv(dev);
450 struct alt_tse_mac *mac_dev = priv->mac_dev;
Simon Glassc69cda22020-12-03 16:55:20 -0700451 struct eth_pdata *pdata = dev_get_plat(dev);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800452 u8 *hwaddr = pdata->enetaddr;
Thomas Chou2cd0a522015-11-06 09:36:26 +0800453 u32 mac_lo, mac_hi;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800454
455 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
456 (hwaddr[1] << 8) | hwaddr[0];
457 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
458 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
459
460 writel(mac_lo, &mac_dev->mac_addr_0);
461 writel(mac_hi, &mac_dev->mac_addr_1);
462 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
463 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
464 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
465 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
466 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
467 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
468 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
469 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
470
471 return 0;
472}
473
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800474static int altera_tse_send(struct udevice *dev, void *packet, int length)
475{
476 struct altera_tse_priv *priv = dev_get_priv(dev);
477 unsigned long tx_buf = (unsigned long)packet;
478
479 flush_dcache_range(tx_buf, tx_buf + length);
480
481 return priv->ops->send(dev, packet, length);
482}
483
484static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
485{
486 struct altera_tse_priv *priv = dev_get_priv(dev);
487
488 return priv->ops->recv(dev, flags, packetp);
489}
490
491static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
492 int length)
493{
494 struct altera_tse_priv *priv = dev_get_priv(dev);
495 unsigned long rx_buf = (unsigned long)priv->rx_buf;
496
497 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
498
499 return priv->ops->free_pkt(dev, packet, length);
500}
501
502static void altera_tse_stop(struct udevice *dev)
503{
504 struct altera_tse_priv *priv = dev_get_priv(dev);
505
506 priv->ops->stop(dev);
507 altera_tse_stop_mac(priv);
508}
509
Thomas Chou96fa1e42015-10-22 15:29:11 +0800510static int altera_tse_start(struct udevice *dev)
511{
512 struct altera_tse_priv *priv = dev_get_priv(dev);
513 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou2cd0a522015-11-06 09:36:26 +0800514 u32 val;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800515 int ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800516
517 /* need to create sgdma */
Thomas Chouc960b132010-04-20 12:49:52 +0800518 debug("Configuring rx desc\n");
Thomas Chou96fa1e42015-10-22 15:29:11 +0800519 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
Thomas Chouc960b132010-04-20 12:49:52 +0800520 /* start TSE */
521 debug("Configuring TSE Mac\n");
522 /* Initialize MAC registers */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800523 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
524 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
525 writel(0, &mac_dev->rx_sel_full_threshold);
526 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
527 writel(0, &mac_dev->tx_sel_full_threshold);
528 writel(8, &mac_dev->rx_almost_empty_threshold);
529 writel(8, &mac_dev->rx_almost_full_threshold);
530 writel(8, &mac_dev->tx_almost_empty_threshold);
531 writel(3, &mac_dev->tx_almost_full_threshold);
Thomas Chouc960b132010-04-20 12:49:52 +0800532
533 /* NO Shift */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800534 writel(0, &mac_dev->rx_cmd_stat);
535 writel(0, &mac_dev->tx_cmd_stat);
Thomas Chouc960b132010-04-20 12:49:52 +0800536
537 /* enable MAC */
Thomas Chou96fa1e42015-10-22 15:29:11 +0800538 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
539 writel(val, &mac_dev->command_config);
Thomas Chouc960b132010-04-20 12:49:52 +0800540
Thomas Chou96fa1e42015-10-22 15:29:11 +0800541 /* Start up the PHY */
542 ret = phy_startup(priv->phydev);
543 if (ret) {
544 debug("Could not initialize PHY %s\n",
545 priv->phydev->dev->name);
546 return ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800547 }
548
Thomas Chou96fa1e42015-10-22 15:29:11 +0800549 tse_adjust_link(priv, priv->phydev);
550
551 if (!priv->phydev->link)
552 return -EIO;
553
554 return 0;
Thomas Chouc960b132010-04-20 12:49:52 +0800555}
556
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800557static const struct tse_ops tse_sgdma_ops = {
558 .send = altera_tse_send_sgdma,
559 .recv = altera_tse_recv_sgdma,
560 .free_pkt = altera_tse_free_pkt_sgdma,
561 .stop = altera_tse_stop_sgdma,
562};
563
Thomas Choue3e87262015-11-09 14:36:29 +0800564static const struct tse_ops tse_msgdma_ops = {
565 .send = altera_tse_send_msgdma,
566 .recv = altera_tse_recv_msgdma,
567 .free_pkt = altera_tse_free_pkt_msgdma,
568 .stop = altera_tse_stop_msgdma,
569};
570
Thomas Chou96fa1e42015-10-22 15:29:11 +0800571static int altera_tse_probe(struct udevice *dev)
Thomas Chouc960b132010-04-20 12:49:52 +0800572{
Simon Glassc69cda22020-12-03 16:55:20 -0700573 struct eth_pdata *pdata = dev_get_plat(dev);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800574 struct altera_tse_priv *priv = dev_get_priv(dev);
Thomas Chou75199d62015-11-06 09:37:17 +0800575 void *blob = (void *)gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700576 int node = dev_of_offset(dev);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800577 const char *list, *end;
578 const fdt32_t *cell;
579 void *base, *desc_mem = NULL;
580 unsigned long addr, size;
Thomas Chou75199d62015-11-06 09:37:17 +0800581 int parent, addrc, sizec;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800582 int len, idx;
583 int ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800584
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800585 priv->dma_type = dev_get_driver_data(dev);
586 if (priv->dma_type == ALT_SGDMA)
587 priv->ops = &tse_sgdma_ops;
Thomas Choue3e87262015-11-09 14:36:29 +0800588 else
589 priv->ops = &tse_msgdma_ops;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800590 /*
Thomas Chou75199d62015-11-06 09:37:17 +0800591 * decode regs. there are multiple reg tuples, and they need to
592 * match with reg-names.
Thomas Chou96fa1e42015-10-22 15:29:11 +0800593 */
Thomas Chou75199d62015-11-06 09:37:17 +0800594 parent = fdt_parent_offset(blob, node);
Simon Glasseed36602017-05-18 20:09:26 -0600595 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800596 list = fdt_getprop(blob, node, "reg-names", &len);
597 if (!list)
598 return -ENOENT;
599 end = list + len;
600 cell = fdt_getprop(blob, node, "reg", &len);
601 if (!cell)
602 return -ENOENT;
603 idx = 0;
604 while (list < end) {
605 addr = fdt_translate_address((void *)blob,
606 node, cell + idx);
Thomas Chou75199d62015-11-06 09:37:17 +0800607 size = fdt_addr_to_cpu(cell[idx + addrc]);
Thomas Choue2b259f2015-11-14 11:21:16 +0800608 base = map_physmem(addr, size, MAP_NOCACHE);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800609 len = strlen(list);
610 if (strcmp(list, "control_port") == 0)
611 priv->mac_dev = base;
612 else if (strcmp(list, "rx_csr") == 0)
613 priv->sgdma_rx = base;
Thomas Choue3e87262015-11-09 14:36:29 +0800614 else if (strcmp(list, "rx_desc") == 0)
615 priv->rx_desc = base;
616 else if (strcmp(list, "rx_resp") == 0)
617 priv->rx_resp = base;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800618 else if (strcmp(list, "tx_csr") == 0)
619 priv->sgdma_tx = base;
Thomas Choue3e87262015-11-09 14:36:29 +0800620 else if (strcmp(list, "tx_desc") == 0)
621 priv->tx_desc = base;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800622 else if (strcmp(list, "s1") == 0)
623 desc_mem = base;
Thomas Chou75199d62015-11-06 09:37:17 +0800624 idx += addrc + sizec;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800625 list += (len + 1);
Thomas Chouc960b132010-04-20 12:49:52 +0800626 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800627 /* decode fifo depth */
628 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
629 "rx-fifo-depth", 0);
630 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
631 "tx-fifo-depth", 0);
632 /* decode phy */
633 addr = fdtdec_get_int(blob, node,
634 "phy-handle", 0);
635 addr = fdt_node_offset_by_phandle(blob, addr);
636 priv->phyaddr = fdtdec_get_int(blob, addr,
637 "reg", 0);
638 /* init desc */
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800639 if (priv->dma_type == ALT_SGDMA) {
640 len = sizeof(struct alt_sgdma_descriptor) * 4;
641 if (!desc_mem) {
642 desc_mem = dma_alloc_coherent(len, &addr);
643 if (!desc_mem)
644 return -ENOMEM;
645 }
646 memset(desc_mem, 0, len);
647 priv->tx_desc = desc_mem;
648 priv->rx_desc = priv->tx_desc +
649 2 * sizeof(struct alt_sgdma_descriptor);
Joachim Foersterb962ac72011-10-17 05:24:44 +0000650 }
Thomas Chou96fa1e42015-10-22 15:29:11 +0800651 /* allocate recv packet buffer */
652 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
653 if (!priv->rx_buf)
654 return -ENOMEM;
Joachim Foersterb962ac72011-10-17 05:24:44 +0000655
Thomas Chou96fa1e42015-10-22 15:29:11 +0800656 /* stop controller */
657 debug("Reset TSE & SGDMAs\n");
658 altera_tse_stop(dev);
Thomas Chouc960b132010-04-20 12:49:52 +0800659
Thomas Chou96fa1e42015-10-22 15:29:11 +0800660 /* start the phy */
661 priv->interface = pdata->phy_interface;
662 tse_mdio_init(dev->name, priv);
663 priv->bus = miiphy_get_dev_by_name(dev->name);
Thomas Chouc960b132010-04-20 12:49:52 +0800664
Thomas Chou96fa1e42015-10-22 15:29:11 +0800665 ret = tse_phy_init(priv, dev);
Thomas Chouc960b132010-04-20 12:49:52 +0800666
Thomas Chou96fa1e42015-10-22 15:29:11 +0800667 return ret;
Thomas Chouc960b132010-04-20 12:49:52 +0800668}
Thomas Chou96fa1e42015-10-22 15:29:11 +0800669
Simon Glassd1998a92020-12-03 16:55:21 -0700670static int altera_tse_of_to_plat(struct udevice *dev)
Thomas Chou96fa1e42015-10-22 15:29:11 +0800671{
Simon Glassc69cda22020-12-03 16:55:20 -0700672 struct eth_pdata *pdata = dev_get_plat(dev);
Thomas Chou96fa1e42015-10-22 15:29:11 +0800673
Marek BehĂșn123ca112022-04-07 00:33:01 +0200674 pdata->phy_interface = dev_read_phy_mode(dev);
Marek BehĂșnffb0f6f2022-04-07 00:33:03 +0200675 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
Thomas Chou96fa1e42015-10-22 15:29:11 +0800676 return -EINVAL;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800677
678 return 0;
679}
680
681static const struct eth_ops altera_tse_ops = {
682 .start = altera_tse_start,
683 .send = altera_tse_send,
684 .recv = altera_tse_recv,
685 .free_pkt = altera_tse_free_pkt,
686 .stop = altera_tse_stop,
687 .write_hwaddr = altera_tse_write_hwaddr,
688};
689
690static const struct udevice_id altera_tse_ids[] = {
Thomas Choue3e87262015-11-09 14:36:29 +0800691 { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800692 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
693 {}
Thomas Chou96fa1e42015-10-22 15:29:11 +0800694};
695
696U_BOOT_DRIVER(altera_tse) = {
697 .name = "altera_tse",
698 .id = UCLASS_ETH,
699 .of_match = altera_tse_ids,
700 .ops = &altera_tse_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700701 .of_to_plat = altera_tse_of_to_plat,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700702 .plat_auto = sizeof(struct eth_pdata),
Simon Glass41575d82020-12-03 16:55:17 -0700703 .priv_auto = sizeof(struct altera_tse_priv),
Thomas Chou96fa1e42015-10-22 15:29:11 +0800704 .probe = altera_tse_probe,
705};