blob: 89442f9386ba8b5e10d15ae3448d7ea769b62808 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz6e53e272006-03-14 15:59:25 +01002/*
3 * (C) Copyright 2001, 2002, 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Keith Outwater, keith_outwater@mvis.com`
6 * Steven Scholz, steven.scholz@imc-berlin.de
Marian Balakowicz6e53e272006-03-14 15:59:25 +01007 */
8
9/*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
11 * DS1374 Real Time Clock (RTC).
12 *
13 * based on ds1337.c
14 */
15
16#include <common.h>
17#include <command.h>
18#include <rtc.h>
19#include <i2c.h>
20
Marian Balakowicz6e53e272006-03-14 15:59:25 +010021/*---------------------------------------------------------------------*/
22#undef DEBUG_RTC
23#define DEBUG_RTC
24
25#ifdef DEBUG_RTC
26#define DEBUGR(fmt,args...) printf(fmt ,##args)
27#else
28#define DEBUGR(fmt,args...)
29#endif
30/*---------------------------------------------------------------------*/
31
Tom Rini65cc0e22022-11-16 13:10:41 -050032#ifndef CFG_SYS_I2C_RTC_ADDR
33# define CFG_SYS_I2C_RTC_ADDR 0x68
Marian Balakowicz6e53e272006-03-14 15:59:25 +010034#endif
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
Marian Balakowicz6e53e272006-03-14 15:59:25 +010037# error The DS1374 is specified up to 400kHz in fast mode!
38#endif
39
40/*
41 * RTC register addresses
42 */
43#define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
44#define RTC_TOD_CNT_BYTE1_ADDR 0x01
45#define RTC_TOD_CNT_BYTE2_ADDR 0x02
46#define RTC_TOD_CNT_BYTE3_ADDR 0x03
47
48#define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
49#define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
50#define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
51
52#define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
53#define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
54#define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
55
56#define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
57#define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
58#define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
59#define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
60#define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
Heinrich Schuchardt691132e2020-04-20 18:31:21 +020061#define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdog/Alarm Counter Select */
Marian Balakowicz6e53e272006-03-14 15:59:25 +010062#define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
63#define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
64
65#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
66#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
67
Marian Balakowicz6e53e272006-03-14 15:59:25 +010068const char RtcTodAddr[] = {
69 RTC_TOD_CNT_BYTE0_ADDR,
70 RTC_TOD_CNT_BYTE1_ADDR,
71 RTC_TOD_CNT_BYTE2_ADDR,
72 RTC_TOD_CNT_BYTE3_ADDR
73};
74
75static uchar rtc_read (uchar reg);
York Sun472d5462013-04-01 11:29:11 -070076static void rtc_write(uchar reg, uchar val, bool set);
Marian Balakowicz6e53e272006-03-14 15:59:25 +010077static void rtc_write_raw (uchar reg, uchar val);
78
79/*
80 * Get the current time from the RTC
81 */
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030082int rtc_get (struct rtc_time *tm){
83 int rel = 0;
Marian Balakowicz6e53e272006-03-14 15:59:25 +010084 unsigned long time1, time2;
85 unsigned int limit;
86 unsigned char tmp;
87 unsigned int i;
88
89 /*
90 * Since the reads are being performed one byte at a time,
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020091 * there is a chance that a carry will occur during the read.
Marian Balakowicz6e53e272006-03-14 15:59:25 +010092 * To detect this, 2 reads are performed and compared.
93 */
94 limit = 10;
95 do {
96 i = 4;
97 time1 = 0;
98 while (i--) {
99 tmp = rtc_read(RtcTodAddr[i]);
100 time1 = (time1 << 8) | (tmp & 0xff);
101 }
102
103 i = 4;
104 time2 = 0;
105 while (i--) {
106 tmp = rtc_read(RtcTodAddr[i]);
107 time2 = (time2 << 8) | (tmp & 0xff);
108 }
109 } while ((time1 != time2) && limit--);
110
111 if (time1 != time2) {
112 printf("can't get consistent time from rtc chip\n");
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300113 rel = -1;
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100114 }
115
Kim Phillips4109df62008-07-10 14:00:15 -0500116 DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100117
Simon Glass9f9276c2015-04-20 12:37:18 -0600118 rtc_to_tm(time1, tm); /* To Gregorian Date */
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100119
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300120 if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100121 printf ("### Warning: RTC oscillator has stopped\n");
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300122 rel = -1;
123 }
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100124
125 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
126 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
127 tm->tm_hour, tm->tm_min, tm->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300128
129 return rel;
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100130}
131
132/*
133 * Set the RTC
134 */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200135int rtc_set (struct rtc_time *tmp){
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100136
137 unsigned long time;
138 unsigned i;
139
140 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
141 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
142 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
143
144 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
145 printf("WARNING: year should be between 1970 and 2069!\n");
146
Simon Glass71420982015-04-20 12:37:19 -0600147 time = rtc_mktime(tmp);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100148
Kim Phillips4109df62008-07-10 14:00:15 -0500149 DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100150
151 /* write to RTC_TOD_CNT_BYTEn_ADDR */
152 for (i = 0; i <= 3; i++) {
153 rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
154 time = time >> 8;
155 }
156
157 /* Start clock */
York Sun472d5462013-04-01 11:29:11 -0700158 rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200159
160 return 0;
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100161}
162
163/*
164 * Reset the RTC. We setting the date back to 1970-01-01.
165 * We also enable the oscillator output on the SQW/OUT pin and program
166 * it for 32,768 Hz output. Note that according to the datasheet, turning
167 * on the square wave output increases the current drain on the backup
168 * battery to something between 480nA and 800nA.
169 */
170void rtc_reset (void){
171
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100172 /* clear status flags */
York Sun472d5462013-04-01 11:29:11 -0700173 rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100174
175 /* Initialise DS1374 oriented to MPC8349E-ADS */
176 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
177 |RTC_CTL_BIT_WACE
York Sun472d5462013-04-01 11:29:11 -0700178 |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100179 - set to 0 */
180 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
181 |RTC_CTL_BIT_WDSTR
182 |RTC_CTL_BIT_RS1
183 |RTC_CTL_BIT_RS2
York Sun472d5462013-04-01 11:29:11 -0700184 |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100185 set BBSQW and SQW to 32k
186 - set to 1 */
York Sun472d5462013-04-01 11:29:11 -0700187 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
188 rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
189 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100190}
191
192/*
193 * Helper functions
194 */
195static uchar rtc_read (uchar reg)
196{
Tom Rini65cc0e22022-11-16 13:10:41 -0500197 return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100198}
199
York Sun472d5462013-04-01 11:29:11 -0700200static void rtc_write(uchar reg, uchar val, bool set)
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100201{
York Sun472d5462013-04-01 11:29:11 -0700202 if (set == true) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500203 val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg);
204 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100205 } else {
Tom Rini65cc0e22022-11-16 13:10:41 -0500206 val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val;
207 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100208 }
209}
210
211static void rtc_write_raw (uchar reg, uchar val)
212{
Tom Rini65cc0e22022-11-16 13:10:41 -0500213 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowicz6e53e272006-03-14 15:59:25 +0100214}