Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 1 | /* |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 2 | * Copyright 2006 Freescale Semiconductor |
| 3 | * Jeff Brown |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <watchdog.h> |
| 27 | #include <command.h> |
| 28 | #include <asm/cache.h> |
Becky Bruce | e34a0e9 | 2008-05-08 19:02:51 -0500 | [diff] [blame] | 29 | #include <asm/mmu.h> |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 30 | #include <mpc86xx.h> |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 31 | #include <tsec.h> |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 32 | #include <asm/fsl_law.h> |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 33 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 34 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 35 | int |
| 36 | checkcpu(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 37 | { |
| 38 | sys_info_t sysinfo; |
| 39 | uint pvr, svr; |
| 40 | uint ver; |
| 41 | uint major, minor; |
| 42 | uint lcrr; /* local bus clock ratio register */ |
| 43 | uint clkdiv; /* clock divider portion of lcrr */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | 9553df8 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 45 | volatile ccsr_gur_t *gur = &immap->im_gur; |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 46 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 47 | puts("Freescale PowerPC\n"); |
| 48 | |
| 49 | pvr = get_pvr(); |
| 50 | ver = PVR_VER(pvr); |
| 51 | major = PVR_MAJ(pvr); |
| 52 | minor = PVR_MIN(pvr); |
| 53 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 54 | puts("CPU:\n"); |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 55 | puts(" Core: "); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 56 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 57 | switch (ver) { |
| 58 | case PVR_VER(PVR_86xx): |
Jon Loeliger | 9553df8 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 59 | { |
| 60 | uint msscr0 = mfspr(MSSCR0); |
| 61 | printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); |
| 62 | if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) |
| 63 | puts("\n Core1Translation Enabled"); |
| 64 | debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); |
| 65 | } |
| 66 | break; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 67 | default: |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 68 | puts("Unknown"); |
| 69 | break; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 70 | } |
| 71 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 72 | |
| 73 | svr = get_svr(); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 74 | ver = SVR_SOC_VER(svr); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 75 | major = SVR_MAJ(svr); |
| 76 | minor = SVR_MIN(svr); |
| 77 | |
| 78 | puts(" System: "); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 79 | switch (ver) { |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 80 | case SVR_8641: |
Jon Loeliger | d14ba6a | 2006-09-14 08:40:36 -0500 | [diff] [blame] | 81 | if (SVR_SUBVER(svr) == 1) { |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 82 | puts("8641D"); |
Jon Loeliger | d14ba6a | 2006-09-14 08:40:36 -0500 | [diff] [blame] | 83 | } else { |
| 84 | puts("8641"); |
| 85 | } |
| 86 | break; |
Jon Loeliger | 9553df8 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 87 | case SVR_8610: |
| 88 | puts("8610"); |
| 89 | break; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 90 | default: |
| 91 | puts("Unknown"); |
| 92 | break; |
| 93 | } |
| 94 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
| 95 | |
| 96 | get_sys_info(&sysinfo); |
| 97 | |
| 98 | puts(" Clocks: "); |
| 99 | printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); |
| 100 | printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); |
| 101 | printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 102 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #if defined(CONFIG_SYS_LBC_LCRR) |
| 104 | lcrr = CONFIG_SYS_LBC_LCRR; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 105 | #else |
| 106 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 108 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 109 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 110 | lcrr = lbc->lcrr; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 111 | } |
| 112 | #endif |
Trent Piepho | a5d212a | 2008-12-03 15:16:34 -0800 | [diff] [blame] | 113 | clkdiv = lcrr & LCRR_CLKDIV; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 114 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { |
Trent Piepho | 9863d6a | 2008-12-03 15:16:36 -0800 | [diff] [blame^] | 115 | clkdiv *= 2; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 116 | printf("LBC:%4lu MHz\n", |
| 117 | sysinfo.freqSystemBus / 1000000 / clkdiv); |
| 118 | } else { |
| 119 | printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); |
| 120 | } |
| 121 | |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 122 | puts(" L2: "); |
Jon Loeliger | 126aa70 | 2006-05-30 17:47:00 -0500 | [diff] [blame] | 123 | if (get_l2cr() & 0x80000000) |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 124 | puts("Enabled\n"); |
Jon Loeliger | 126aa70 | 2006-05-30 17:47:00 -0500 | [diff] [blame] | 125 | else |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 126 | puts("Disabled\n"); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 127 | |
| 128 | return 0; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 132 | static inline void |
| 133 | soft_restart(unsigned long addr) |
| 134 | { |
Jason Jin | a8318ec | 2007-10-26 18:32:00 +0800 | [diff] [blame] | 135 | #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 136 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 137 | /* |
| 138 | * SRR0 has system reset vector, SRR1 has default MSR value |
| 139 | * rfi restores MSR from SRR1 and sets the PC to the SRR0 value |
| 140 | */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 141 | |
| 142 | __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); |
| 143 | __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); |
| 144 | __asm__ __volatile__ ("mtspr 27, 4"); |
| 145 | __asm__ __volatile__ ("rfi"); |
| 146 | |
| 147 | #else /* CONFIG_MPC8641HPCN */ |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 148 | |
| 149 | out8(PIXIS_BASE + PIXIS_RST, 0); |
| 150 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 151 | #endif /* !CONFIG_MPC8641HPCN */ |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 152 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 153 | while (1) ; /* not reached */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | |
Jon Loeliger | 126aa70 | 2006-05-30 17:47:00 -0500 | [diff] [blame] | 157 | /* |
| 158 | * No generic way to do board reset. Simply call soft_reset. |
| 159 | */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 160 | void |
Jon Loeliger | 126aa70 | 2006-05-30 17:47:00 -0500 | [diff] [blame] | 161 | do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 162 | { |
Jason Jin | a8318ec | 2007-10-26 18:32:00 +0800 | [diff] [blame] | 163 | #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 164 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #ifdef CONFIG_SYS_RESET_ADDRESS |
| 166 | ulong addr = CONFIG_SYS_RESET_ADDRESS; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 167 | #else |
| 168 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, |
| 170 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 171 | * address. Better pick an address known to be invalid on your |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | * system and assign it to CONFIG_SYS_RESET_ADDRESS. |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 173 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 175 | #endif |
| 176 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 177 | /* flush and disable I/D cache */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 178 | __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); |
| 179 | __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); |
| 180 | __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); |
| 181 | __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); |
| 182 | __asm__ __volatile__ ("sync"); |
| 183 | __asm__ __volatile__ ("mtspr 1008, 4"); |
| 184 | __asm__ __volatile__ ("isync"); |
| 185 | __asm__ __volatile__ ("sync"); |
| 186 | __asm__ __volatile__ ("mtspr 1008, 5"); |
| 187 | __asm__ __volatile__ ("isync"); |
| 188 | __asm__ __volatile__ ("sync"); |
| 189 | |
Jon Loeliger | 126aa70 | 2006-05-30 17:47:00 -0500 | [diff] [blame] | 190 | soft_restart(addr); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 191 | |
| 192 | #else /* CONFIG_MPC8641HPCN */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 193 | |
Haiying Wang | 3d98b85 | 2007-01-22 12:37:30 -0600 | [diff] [blame] | 194 | out8(PIXIS_BASE + PIXIS_RST, 0); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 195 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 196 | #endif /* !CONFIG_MPC8641HPCN */ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 197 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 198 | while (1) ; /* not reached */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 202 | /* |
| 203 | * Get timebase clock frequency |
| 204 | */ |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 205 | unsigned long |
| 206 | get_tbclk(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 207 | { |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 208 | sys_info_t sys_info; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 209 | |
| 210 | get_sys_info(&sys_info); |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 211 | return (sys_info.freqSystemBus + 3L) / 4L; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 212 | } |
| 213 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 214 | |
| 215 | #if defined(CONFIG_WATCHDOG) |
| 216 | void |
| 217 | watchdog_reset(void) |
| 218 | { |
Jason Jin | 3473ab7 | 2008-05-13 11:50:36 +0800 | [diff] [blame] | 219 | #if defined(CONFIG_MPC8610) |
| 220 | /* |
| 221 | * This actually feed the hard enabled watchdog. |
| 222 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Jason Jin | 3473ab7 | 2008-05-13 11:50:36 +0800 | [diff] [blame] | 224 | volatile ccsr_wdt_t *wdt = &immap->im_wdt; |
| 225 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 226 | u32 tmp = gur->pordevsr; |
| 227 | |
| 228 | if (tmp & 0x4000) { |
| 229 | wdt->swsrr = 0x556c; |
| 230 | wdt->swsrr = 0xaa39; |
| 231 | } |
| 232 | #endif |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 233 | } |
| 234 | #endif /* CONFIG_WATCHDOG */ |
| 235 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 236 | |
| 237 | #if defined(CONFIG_DDR_ECC) |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 238 | void |
| 239 | dma_init(void) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 240 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 242 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 243 | |
| 244 | dma->satr0 = 0x00040000; |
| 245 | dma->datr0 = 0x00040000; |
| 246 | asm("sync; isync"); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 247 | } |
| 248 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 249 | uint |
| 250 | dma_check(void) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 251 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 253 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 254 | volatile uint status = dma->sr0; |
| 255 | |
| 256 | /* While the channel is busy, spin */ |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 257 | while ((status & 4) == 4) { |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 258 | status = dma->sr0; |
| 259 | } |
| 260 | |
| 261 | if (status != 0) { |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 262 | printf("DMA Error: status = %x\n", status); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 263 | } |
| 264 | return status; |
| 265 | } |
| 266 | |
Jon Loeliger | ffff3ae | 2006-08-22 12:06:18 -0500 | [diff] [blame] | 267 | int |
| 268 | dma_xfer(void *dest, uint count, void *src) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 269 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 271 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 272 | |
| 273 | dma->dar0 = (uint) dest; |
| 274 | dma->sar0 = (uint) src; |
| 275 | dma->bcr0 = count; |
| 276 | dma->mr0 = 0xf000004; |
| 277 | asm("sync;isync"); |
| 278 | dma->mr0 = 0xf000005; |
| 279 | asm("sync;isync"); |
| 280 | return dma_check(); |
| 281 | } |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 282 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 283 | #endif /* CONFIG_DDR_ECC */ |
| 284 | |
| 285 | |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 286 | /* |
| 287 | * Print out the state of various machine registers. |
Becky Bruce | e34a0e9 | 2008-05-08 19:02:51 -0500 | [diff] [blame] | 288 | * Currently prints out LAWs, BR0/OR0, and BATs |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 289 | */ |
| 290 | void mpc86xx_reginfo(void) |
| 291 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 292 | immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 293 | ccsr_lbc_t *lbc = &immap->im_lbc; |
| 294 | |
Becky Bruce | e34a0e9 | 2008-05-08 19:02:51 -0500 | [diff] [blame] | 295 | print_bats(); |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 296 | print_laws(); |
| 297 | |
| 298 | printf ("Local Bus Controller Registers\n" |
| 299 | "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); |
| 300 | printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); |
| 301 | printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); |
| 302 | printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); |
| 303 | printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); |
| 304 | printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); |
| 305 | printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); |
| 306 | printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 307 | |
| 308 | } |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 309 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 310 | /* |
| 311 | * Initializes on-chip ethernet controllers. |
| 312 | * to override, implement board_eth_init() |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 313 | */ |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 314 | int cpu_eth_init(bd_t *bis) |
| 315 | { |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 316 | #if defined(CONFIG_TSEC_ENET) |
| 317 | tsec_standard_init(bis); |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 318 | #endif |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 319 | |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 320 | return 0; |
| 321 | } |