blob: 533f46976a09bc5aadea4eef007756e1543dcb1f [file] [log] [blame]
Michael Schwingenaebf00f2008-01-16 19:51:14 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * Configuration settings for the AcTux-2 board.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingenaebf00f2008-01-16 19:51:14 +01008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_IXP425 1
14#define CONFIG_ACTUX2 1
15
Marek Vasut8e807ec2012-03-06 00:45:35 +010016#define CONFIG_MACH_TYPE 1480
17
Michael Schwingenaebf00f2008-01-16 19:51:14 +010018#define CONFIG_DISPLAY_CPUINFO 1
19#define CONFIG_DISPLAY_BOARDINFO 1
20
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010021#define CONFIG_IXP_SERIAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
Michael Schwingenaebf00f2008-01-16 19:51:14 +010023#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 5
25#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Michael Schwingenaf050482011-05-23 00:00:05 +020026#define CONFIG_BOARD_EARLY_INIT_F 1
27#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds"
Michael Schwingenaebf00f2008-01-16 19:51:14 +010028
29/***************************************************************
30 * U-boot generic defines start here.
31 ***************************************************************/
Michael Schwingenaebf00f2008-01-16 19:51:14 +010032/* Size of malloc() pool */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Michael Schwingenaebf00f2008-01-16 19:51:14 +010034
35/* allow to overwrite serial and ethaddr */
36#define CONFIG_ENV_OVERWRITE
37
38/* Command line configuration. */
39#include <config_cmd_default.h>
40
41#define CONFIG_CMD_ELF
42#undef CONFIG_CMD_PCI
43#undef CONFIG_PCI
44
45#define CONFIG_BOOTCOMMAND "run boot_flash"
46/* enable passing of ATAGs */
47#define CONFIG_CMDLINE_TAG 1
48#define CONFIG_SETUP_MEMORY_TAGS 1
49#define CONFIG_INITRD_TAG 1
50#define CONFIG_REVISION_TAG 1
51
52#if defined(CONFIG_CMD_KGDB)
53# define CONFIG_KGDB_BAUDRATE 230400
54/* which serial port to use */
55# define CONFIG_KGDB_SER_INDEX 1
56#endif
57
58/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_LONGHELP
60#define CONFIG_SYS_PROMPT "=> "
Michael Schwingenaebf00f2008-01-16 19:51:14 +010061/* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_CBSIZE 256
Michael Schwingenaebf00f2008-01-16 19:51:14 +010063/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Michael Schwingenaebf00f2008-01-16 19:51:14 +010065/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_MAXARGS 16
Michael Schwingenaebf00f2008-01-16 19:51:14 +010067/* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Michael Schwingenaebf00f2008-01-16 19:51:14 +010069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_MEMTEST_START 0x00400000
71#define CONFIG_SYS_MEMTEST_END 0x00800000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010072
Michael Schwingenaf050482011-05-23 00:00:05 +020073/* timer clock - 2* OSC_IN system clock */
74#define CONFIG_IXP425_TIMER_CLK 66666666
75#define CONFIG_SYS_HZ 1000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010076
77/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_LOAD_ADDR 0x00010000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010079
80/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
Michael Schwingenaebf00f2008-01-16 19:51:14 +010082 115200, 230400 }
83#define CONFIG_SERIAL_RTS_ACTIVE 1
84
Michael Schwingenaebf00f2008-01-16 19:51:14 +010085/* Expansion bus settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_EXP_CS0 0xbd113042
Michael Schwingenaebf00f2008-01-16 19:51:14 +010087
88/* SDRAM settings */
89#define CONFIG_NR_DRAM_BANKS 1
90#define PHYS_SDRAM_1 0x00000000
Michael Schwingenaf050482011-05-23 00:00:05 +020091#define CONFIG_SYS_SDRAM_BASE 0x00000000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010092
93/* 16MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_SDR_CONFIG 0x3A
Michael Schwingenaebf00f2008-01-16 19:51:14 +010095#define PHYS_SDRAM_1_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
97#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
98#define CONFIG_SYS_DRAM_SIZE 0x01000000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010099
100/* FLASH organization */
Michael Schwingenaf050482011-05-23 00:00:05 +0200101#define CONFIG_SYS_TEXT_BASE 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_MAX_FLASH_BANKS 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100103/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAX_FLASH_SECT 140
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100105#define PHYS_FLASH_1 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
109#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
110#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Michael Schwingenaf050482011-05-23 00:00:05 +0200111#define CONFIG_BOARD_SIZE_LIMIT 262144
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100112
113/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200115#define CONFIG_FLASH_CFI_DRIVER
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100116/* no byte writes on IXP4xx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100118
119/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_EMPTY_INFO
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100121
122/* Ethernet */
123
124/* include IXP4xx NPE support */
125#define CONFIG_IXP4XX_NPE 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100126/* NPE0 PHY address */
127#define CONFIG_PHY_ADDR 0x00
128/* MII PHY management */
129#define CONFIG_MII 1
Michael Schwingenaf050482011-05-23 00:00:05 +0200130/* fixed-speed switch without standard PHY registers on MII */
131#define CONFIG_MII_NPE0_FIXEDLINK 1
132#define CONFIG_MII_NPE0_SPEED 100
133#define CONFIG_MII_NPE0_FULLDUPLEX 1
134
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100135/* Number of ethernet rx buffers & descriptors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_RX_ETH_BUFFER 16
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100137#define CONFIG_RESET_PHY_R 1
138/* ethernet switch connected to MII port */
139#define CONFIG_MII_ETHSWITCH 1
140
141#define CONFIG_CMD_DHCP
142#define CONFIG_CMD_NET
143#define CONFIG_CMD_MII
144#define CONFIG_CMD_PING
145#undef CONFIG_CMD_NFS
146
147/* BOOTP options */
148#define CONFIG_BOOTP_BOOTFILESIZE
149#define CONFIG_BOOTP_BOOTPATH
150#define CONFIG_BOOTP_GATEWAY
151#define CONFIG_BOOTP_HOSTNAME
152
153/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_CACHELINE_SIZE 32
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100155
156/*
157 * environment organization:
158 * one flash sector, embedded in uboot area (bottom bootblock flash)
159 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200160#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_SIZE 0x2000
162#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_USE_PPCENV 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100164
165#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARDb4e2f892009-01-31 09:53:39 +0100166 "npe_ucode=50040000\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100167 "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
168 "kerneladdr=50050000\0" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200169 "kernelfile=actux2/uImage\0" \
170 "rootfile=actux2/rootfs\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100171 "rootaddr=50170000\0" \
172 "loadaddr=10000\0" \
173 "updateboot_ser=mw.b 10000 ff 40000;" \
174 " loady ${loadaddr};" \
175 " run eraseboot writeboot\0" \
176 "updateboot_net=mw.b 10000 ff 40000;" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200177 " tftp ${loadaddr} actux2/u-boot.bin;" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100178 " run eraseboot writeboot\0" \
179 "eraseboot=protect off 50000000 50003fff;" \
180 " protect off 50006000 5003ffff;" \
181 " erase 50000000 50003fff;" \
182 " erase 50006000 5003ffff\0" \
183 "writeboot=cp.b 10000 50000000 4000;" \
184 " cp.b 16000 50006000 3a000\0" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200185 "updateucode=loady;" \
186 " era ${npe_ucode} +${filesize};" \
187 " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100188 "updateroot=tftp ${loadaddr} ${rootfile};" \
189 " era ${rootaddr} +${filesize};" \
190 " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
191 "updatekern=tftp ${loadaddr} ${kernelfile};" \
192 " era ${kerneladdr} +${filesize};" \
193 " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
194 "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
195 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
196 "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
197 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
198 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
199 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
200 "boot_flash=run flashargs addtty addeth;" \
201 " bootm ${kerneladdr}\0" \
202 "boot_net=run netargs addtty addeth;" \
203 " tftpboot ${loadaddr} ${kernelfile};" \
204 " bootm\0"
205
Michael Schwingenaf050482011-05-23 00:00:05 +0200206/* additions for new relocation code, must be added to all boards */
207#define CONFIG_SYS_INIT_SP_ADDR \
208 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
209
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100210#endif /* __CONFIG_H */