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Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +02001/*
2 * Copyright (C) 2008 Atmel Corporation
3 *
4 * Configuration settings for the Favr-32 EarthLCD LCD kit.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020012
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000013#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_FAVR32_EZKIT
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020016
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000017#define CONFIG_FAVR32_EZKIT_EXT_FLASH
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020018
19/*
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020020 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
21 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
22 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020024 */
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000025#define CONFIG_PLL
26#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_OSC0_HZ 20000000
28#define CONFIG_SYS_PLL0_DIV 1
29#define CONFIG_SYS_PLL0_MUL 7
30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020031/*
32 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020034 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_CLKDIV_CPU 0
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020036/*
37 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020039 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_CLKDIV_HSB 1
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020041/*
42 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020044 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_CLKDIV_PBA 2
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020046/*
47 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020049 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_CLKDIV_PBB 1
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020051
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070052/* Reserve VM regions for SDRAM and NOR flash */
53#define CONFIG_SYS_NR_VM_REGIONS 2
54
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020055/*
56 * The PLLOPT register controls the PLL like this:
57 * icp = PLLOPT<2>
58 * ivco = PLLOPT<1:0>
59 *
60 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
61 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_PLL0_OPT 0x04
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020063
Andreas Bießmannf4278b72010-11-04 23:15:31 +000064#define CONFIG_USART_BASE ATMEL_BASE_USART3
65#define CONFIG_USART_ID 3
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020066
67/* User serviceable stuff */
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000068#define CONFIG_DOS_PARTITION
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020069
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000070#define CONFIG_CMDLINE_TAG
71#define CONFIG_SETUP_MEMORY_TAGS
72#define CONFIG_INITRD_TAG
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020073
74#define CONFIG_STACKSIZE (2048)
75
76#define CONFIG_BAUDRATE 115200
77#define CONFIG_BOOTARGS \
78 "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
79
80#define CONFIG_BOOTCOMMAND \
81 "fsload; bootm $(fileaddr)"
82
83/*
84 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
85 * data on the serial line may interrupt the boot sequence.
86 */
87#define CONFIG_BOOTDELAY 1
Andreas Bießmanneacbfe72011-04-18 04:12:40 +000088#define CONFIG_AUTOBOOT
89#define CONFIG_AUTOBOOT_KEYED
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020090#define CONFIG_AUTOBOOT_PROMPT \
Haavard Skinnemoen25da0b82008-08-20 09:27:37 +020091 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +020092#define CONFIG_AUTOBOOT_DELAY_STR "d"
93#define CONFIG_AUTOBOOT_STOP_STR " "
94
95/*
96 * After booting the board for the first time, new ethernet addresses
97 * should be generated and assigned to the environment variables
98 * "ethaddr" and "eth1addr". This is normally done during production.
99 */
Andreas Bießmanneacbfe72011-04-18 04:12:40 +0000100#define CONFIG_OVERWRITE_ETHADDR_ONCE
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200101
102/*
103 * BOOTP options
104 */
105#define CONFIG_BOOTP_SUBNETMASK
106#define CONFIG_BOOTP_GATEWAY
107
108
109/*
110 * Command line configuration.
111 */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_ASKENV
115#define CONFIG_CMD_DHCP
116#define CONFIG_CMD_EXT2
117#define CONFIG_CMD_FAT
118#define CONFIG_CMD_JFFS2
119#define CONFIG_CMD_MMC
120
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200121#undef CONFIG_CMD_FPGA
122#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200123#undef CONFIG_CMD_SOURCE
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200124#undef CONFIG_CMD_XIMG
125
Andreas Bießmanneacbfe72011-04-18 04:12:40 +0000126#define CONFIG_ATMEL_USART
127#define CONFIG_MACB
128#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmanneacbfe72011-04-18 04:12:40 +0000130#define CONFIG_SYS_HSDRAMC
131#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200132#define CONFIG_GENERIC_ATMEL_MCI
133#define CONFIG_GENERIC_MMC
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_DCACHE_LINESZ 32
136#define CONFIG_SYS_ICACHE_LINESZ 32
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200137
138#define CONFIG_NR_DRAM_BANKS 1
139
140/* External flash on Favr-32 */
141#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARDee9536a2008-09-01 01:16:33 +0200143#define CONFIG_FLASH_CFI_DRIVER 1
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200144#endif
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_BASE 0x00000000
147#define CONFIG_SYS_FLASH_SIZE 0x800000
148#define CONFIG_SYS_MAX_FLASH_BANKS 1
149#define CONFIG_SYS_MAX_FLASH_SECT 135
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann8e218a92011-04-18 04:12:45 +0000152#define CONFIG_SYS_TEXT_BASE 0x00000000
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
155#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
156#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200157
Andreas Bießmanneacbfe72011-04-18 04:12:40 +0000158#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200159#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MALLOC_LEN (256*1024)
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200165
166/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
168#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200169
170/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PROMPT "U-Boot> "
172#define CONFIG_SYS_CBSIZE 256
173#define CONFIG_SYS_MAXARGS 16
174#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmanneacbfe72011-04-18 04:12:40 +0000175#define CONFIG_SYS_LONGHELP
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
178#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
179#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Hans-Christian Egtvedt0eb57172008-08-06 14:42:13 +0200180
181#endif /* __CONFIG_H */