| Bin Meng | 5656d04 | 2019-07-18 00:34:07 -0700 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | .. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> |
| 3 | |
| 4 | Cherry Hill CRB |
| 5 | =============== |
| 6 | |
| 7 | This uses Intel FSP for Braswell platform. Download it from Intel FSP website, |
| 8 | put the .fd file to the board directory and rename it to fsp.bin. |
| 9 | |
| 10 | Extract descriptor.bin and me.bin from the original BIOS on the board using |
| 11 | ifdtool and put them to the board directory as well. |
| 12 | |
| 13 | Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS |
| 14 | image for the integrated graphics device. Instead a new binary called Video |
| 15 | BIOS Table (VBT) is shipped. Put it to the board directory and rename it to |
| 16 | vbt.bin if you want graphics support in U-Boot. |
| 17 | |
| 18 | Now you can build U-Boot and obtain u-boot.rom:: |
| 19 | |
| 20 | $ make cherryhill_defconfig |
| 21 | $ make all |
| 22 | |
| 23 | An important note for programming u-boot.rom to the on-board SPI flash is that |
| 24 | you need make sure the SPI flash's 'quad enable' bit in its status register |
| 25 | matches the settings in the descriptor.bin, otherwise the board won't boot. |
| 26 | |
| 27 | For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the |
| 28 | status register by DediProg in: Config > Modify Status Register > Write Status |
| 29 | Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it |
| 30 | persists in SPI flash part regardless of the u-boot.rom image burned. |