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Heiko Schocher2605e902007-02-16 07:57:42 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* especially an MPC5200 */
34#define CONFIG_JUPITER 1 /* ... on Jupiter board */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define CONFIG_BOARD_EARLY_INIT_R 1
39#define CONFIG_BOARD_EARLY_INIT_F 1
40
41#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42#define BOOTFLAG_WARM 0x02 /* Software reboot */
43
Becky Bruce31d82672008-05-08 19:02:12 -050044#define CONFIG_HIGH_BATS 1 /* High BATs supported */
45
Heiko Schocher2605e902007-02-16 07:57:42 +010046/*
47 * Serial console configuration
48 */
49#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
51#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52
53/*
54 * PCI Mapping:
55 * 0x40000000 - 0x4fffffff - PCI Memory
56 * 0x50000000 - 0x50ffffff - PCI IO Space
57 */
Wolfgang Denk769104c2007-03-08 21:49:27 +010058/*#define CONFIG_PCI */
Heiko Schocher2605e902007-02-16 07:57:42 +010059
60#if defined(CONFIG_PCI)
61#define CONFIG_PCI_PNP 1
62#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050063#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Heiko Schocher2605e902007-02-16 07:57:42 +010064
65#define CONFIG_PCI_MEM_BUS 0x40000000
66#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67#define CONFIG_PCI_MEM_SIZE 0x10000000
68
69#define CONFIG_PCI_IO_BUS 0x50000000
70#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71#define CONFIG_PCI_IO_SIZE 0x01000000
Heiko Schocher2605e902007-02-16 07:57:42 +010072#endif
73
74#define CFG_XLB_PIPELINING 1
75
76#define CONFIG_NET_MULTI 1
77#define CONFIG_MII 1
78#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
79
80/* Partitions */
81#define CONFIG_MAC_PARTITION
82#define CONFIG_DOS_PARTITION
83#define CONFIG_ISO_PARTITION
84
85#define CONFIG_TIMESTAMP /* Print image info with timestamp */
86
Heiko Schocher2605e902007-02-16 07:57:42 +010087
Jon Loeligerbc234c12007-07-04 22:32:51 -050088/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050089 * BOOTP options
90 */
91#define CONFIG_BOOTP_BOOTFILESIZE
92#define CONFIG_BOOTP_BOOTPATH
93#define CONFIG_BOOTP_GATEWAY
94#define CONFIG_BOOTP_HOSTNAME
95
96
97/*
Jon Loeligerbc234c12007-07-04 22:32:51 -050098 * Command line configuration.
99 */
100#include <config_cmd_default.h>
101
102#define CONFIG_CMD_NFS
103#define CONFIG_CMD_SNTP
104
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500105#if defined(CONFIG_PCI)
106#define CODFIG_CMD_PCI
107#endif
108
Heiko Schocher2605e902007-02-16 07:57:42 +0100109
110/*
111 * Autobooting
112 */
113#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
114
115#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100116 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Heiko Schocher2605e902007-02-16 07:57:42 +0100117 "echo"
118
119#undef CONFIG_BOOTARGS
120
121#define CONFIG_EXTRA_ENV_SETTINGS \
122 "netdev=eth0\0" \
123 "nfsargs=setenv bootargs root=/dev/nfs rw " \
124 "nfsroot=${serverip}:${rootpath}\0" \
125 "ramargs=setenv bootargs root=/dev/ram rw\0" \
126 "addip=setenv bootargs ${bootargs} " \
127 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
128 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100129 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocher2605e902007-02-16 07:57:42 +0100130 "bootm ${kernel_addr}\0" \
131 "flash_self=run ramargs addip;" \
132 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100133 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
Heiko Schocher8502e302007-03-13 09:40:59 +0100134 "${baudrate}\0" \
135 "contyp=ttyS0\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100136 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
Heiko Schocher8502e302007-03-13 09:40:59 +0100137 "bootm\0" \
138 "rootpath=/opt/eldk/ppc_6xx\0" \
Heiko Schocher2605e902007-02-16 07:57:42 +0100139 "bootfile=/tftpboot/jupiter/uImage\0" \
140 ""
141
142#define CONFIG_BOOTCOMMAND "run flash_self"
143
144/*
145 * IPB Bus clocking configuration.
146 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200147#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
Heiko Schocher2605e902007-02-16 07:57:42 +0100148
149#if 0
150/* pass open firmware flat tree */
Grant Likelycf2817a2007-09-06 09:46:23 -0600151#define CONFIG_OF_LIBFDT 1
Heiko Schocher2605e902007-02-16 07:57:42 +0100152#define CONFIG_OF_BOARD_SETUP 1
153
Heiko Schocher2605e902007-02-16 07:57:42 +0100154#define OF_CPU "PowerPC,5200@0"
155#define OF_SOC "soc5200@f0000000"
156#define OF_TBCLK (bd->bi_busfreq / 8)
157#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
158#endif
159
160#if 0
161/*
162 * I2C configuration
163 */
164#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
165#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
166
167#define CFG_I2C_SPEED 100000 /* 100 kHz */
168#define CFG_I2C_SLAVE 0x7F
169
170/*
171 * EEPROM configuration
172 */
173#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
174#define CFG_I2C_EEPROM_ADDR_LEN 1
175#define CFG_EEPROM_PAGE_WRITE_BITS 3
176#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
177#endif
178
179/*
180 * Flash configuration
181 */
182#define CFG_FLASH_BASE 0xFF000000
183#define CFG_FLASH_SIZE 0x01000000
184
185#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
186
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
Heiko Schocher2605e902007-02-16 07:57:42 +0100188
189#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
190#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
191
192#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
193
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200194#define CONFIG_FLASH_CFI_DRIVER
Heiko Schocher2605e902007-02-16 07:57:42 +0100195#define CFG_FLASH_CFI
196#define CFG_FLASH_EMPTY_INFO
197#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
198#define CFG_UPDATE_FLASH_SIZE 1
199#define CFG_FLASH_USE_BUFFER_WRITE 1
200
201/*
202 * Environment settings
203 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200204#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_SIZE 0x20000
206#define CONFIG_ENV_SECT_SIZE 0x20000
Heiko Schocher2605e902007-02-16 07:57:42 +0100207#define CONFIG_ENV_OVERWRITE 1
208
Heiko Schocher8502e302007-03-13 09:40:59 +0100209/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
211#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher8502e302007-03-13 09:40:59 +0100212
Heiko Schocher2605e902007-02-16 07:57:42 +0100213/*
214 * Memory map
215 */
216#define CFG_MBAR 0xF0000000
217#define CFG_SDRAM_BASE 0x00000000
218#define CFG_DEFAULT_MBAR 0x80000000
219
220/* Use SRAM until RAM will be available */
221#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
222#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
223
224
225#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
226#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
227#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
228
229#define CFG_MONITOR_BASE TEXT_BASE
230#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
231# define CFG_RAMBOOT 1
232#endif
233
234#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
235#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
236#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
237
238/*
239 * Ethernet configuration
240 */
241#define CONFIG_MPC5xxx_FEC 1
242/*
243 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
244 */
245/* #define CONFIG_FEC_10MBIT 1 */
246#define CONFIG_PHY_ADDR 0x00
247
248/*
249 * GPIO configuration
250 */
251#define CFG_GPS_PORT_CONFIG 0x10000004
252
253/*
254 * Miscellaneous configurable options
255 */
256#define CFG_LONGHELP /* undef to save memory */
257#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Heiko Schocher8502e302007-03-13 09:40:59 +0100258
259#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
260#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
261#ifdef CFG_HUSH_PARSER
262#define CFG_PROMPT_HUSH_PS2 "> "
263#endif
Jon Loeligerbc234c12007-07-04 22:32:51 -0500264#if defined(CONFIG_CMD_KGDB)
Heiko Schocher2605e902007-02-16 07:57:42 +0100265#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
266#else
267#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
268#endif
269#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
270#define CFG_MAXARGS 16 /* max number of command args */
271#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
272
273#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
274#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
275#define CFG_ALT_MEMTEST 1
276
277#define CFG_LOAD_ADDR 0x200000 /* default load address */
278
279#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
280
Jon Loeligerbc234c12007-07-04 22:32:51 -0500281#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
282#if defined(CONFIG_CMD_KGDB)
283# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
284#endif
285
Heiko Schocher2605e902007-02-16 07:57:42 +0100286/*
287 * Various low-level settings
288 */
289#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
290#define CFG_HID0_FINAL HID0_ICE
291
292#define CFG_BOOTCS_START CFG_FLASH_BASE
293#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
294#define CFG_BOOTCS_CFG 0x00047801
295#define CFG_CS0_START CFG_FLASH_BASE
296#define CFG_CS0_SIZE CFG_FLASH_SIZE
297
298#define CFG_CS_BURST 0x00000000
299#define CFG_CS_DEADCYCLE 0x33333333
300
301#define CFG_RESET_ADDRESS 0xff000000
302
303#endif /* __CONFIG_H */