blob: 8e3b83986501b4194d3af4cd37aa4c60c55b13af [file] [log] [blame]
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanok0b23fb32009-07-21 19:32:21 +04009 */
10
11#include <common.h>
12#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060013#include <memalign.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040014#include <net.h>
Jeroen Hofstee84f64c82014-10-08 22:57:40 +020015#include <netdev.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040016#include <miiphy.h>
17#include "fec_mxc.h"
18
19#include <asm/arch/clock.h>
20#include <asm/arch/imx-regs.h>
Peng Fanfbecbaa2015-08-12 17:46:51 +080021#include <asm/imx-common/sys_proto.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040022#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090023#include <linux/errno.h>
Marek Vasute2a66e62012-08-26 10:19:20 +000024#include <linux/compiler.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040025
26DECLARE_GLOBAL_DATA_PTR;
27
Marek Vasutbc1ce152012-08-29 03:49:49 +000028/*
29 * Timeout the transfer after 5 mS. This is usually a bit more, since
30 * the code in the tightloops this timeout is used in adds some overhead.
31 */
32#define FEC_XFER_TIMEOUT 5000
33
Fabio Estevamdb5b7f52014-08-25 13:34:16 -030034/*
35 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
36 * 64-byte alignment in the DMA RX FEC buffer.
37 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
38 * satisfies the alignment on other SoCs (32-bytes)
39 */
40#define FEC_DMA_RX_MINALIGN 64
41
Ilya Yanok0b23fb32009-07-21 19:32:21 +040042#ifndef CONFIG_MII
43#error "CONFIG_MII has to be defined!"
44#endif
45
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000046#ifndef CONFIG_FEC_XCV_TYPE
47#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasut392b8502011-09-11 18:05:33 +000048#endif
49
Marek Vasutbe7e87e2011-11-08 23:18:10 +000050/*
51 * The i.MX28 operates with packets in big endian. We need to swap them before
52 * sending and after receiving.
53 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000054#ifdef CONFIG_MX28
55#define CONFIG_FEC_MXC_SWAP_PACKET
56#endif
57
58#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
59
60/* Check various alignment issues at compile time */
61#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
62#error "ARCH_DMA_MINALIGN must be multiple of 16!"
63#endif
64
65#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
66 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
67#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
Marek Vasutbe7e87e2011-11-08 23:18:10 +000068#endif
69
Ilya Yanok0b23fb32009-07-21 19:32:21 +040070#undef DEBUG
71
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000072#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +000073static void swap_packet(uint32_t *packet, int length)
74{
75 int i;
76
77 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
78 packet[i] = __swab32(packet[i]);
79}
80#endif
81
82/*
Ilya Yanok0b23fb32009-07-21 19:32:21 +040083 * MII-interface related functions
84 */
Troy Kisky13947f42012-02-07 14:08:47 +000085static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
86 uint8_t regAddr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +040087{
Ilya Yanok0b23fb32009-07-21 19:32:21 +040088 uint32_t reg; /* convenient holder for the PHY register */
89 uint32_t phy; /* convenient holder for the PHY */
90 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +000091 int val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +040092
93 /*
94 * reading from any PHY's register is done by properly
95 * programming the FEC's MII data register.
96 */
Marek Vasutd133b882011-09-11 18:05:34 +000097 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +040098 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
99 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
100
101 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +0000102 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400103
104 /*
105 * wait for the related interrupt
106 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000107 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000108 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400109 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
110 printf("Read MDIO failed...\n");
111 return -1;
112 }
113 }
114
115 /*
116 * clear mii interrupt bit
117 */
Marek Vasutd133b882011-09-11 18:05:34 +0000118 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400119
120 /*
121 * it's now safe to read the PHY's register
122 */
Troy Kisky13947f42012-02-07 14:08:47 +0000123 val = (unsigned short)readl(&eth->mii_data);
124 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
125 regAddr, val);
126 return val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400127}
128
Troy Kisky575c5cc2012-10-22 16:40:41 +0000129static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic4294b242010-02-01 14:51:30 +0100130{
131 /*
132 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
133 * and do not drop the Preamble.
Måns Rullgård843a3e52015-12-08 15:38:45 +0000134 *
135 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
136 * MII_SPEED) register that defines the MDIO output hold time. Earlier
137 * versions are RAZ there, so just ignore the difference and write the
138 * register always.
139 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
140 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
141 * output.
142 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
143 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
144 * holdtime cannot result in a value greater than 3.
Stefano Babic4294b242010-02-01 14:51:30 +0100145 */
Måns Rullgård843a3e52015-12-08 15:38:45 +0000146 u32 pclk = imx_get_fecclk();
147 u32 speed = DIV_ROUND_UP(pclk, 5000000);
148 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
Markus Niebel6ba45cc2014-02-05 10:54:11 +0100149#ifdef FEC_QUIRK_ENET_MAC
150 speed--;
151#endif
Måns Rullgård843a3e52015-12-08 15:38:45 +0000152 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky575c5cc2012-10-22 16:40:41 +0000153 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100154}
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400155
Troy Kisky13947f42012-02-07 14:08:47 +0000156static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
157 uint8_t regAddr, uint16_t data)
158{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400159 uint32_t reg; /* convenient holder for the PHY register */
160 uint32_t phy; /* convenient holder for the PHY */
161 uint32_t start;
162
163 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
164 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
165
166 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000167 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400168
169 /*
170 * wait for the MII interrupt
171 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000172 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000173 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400174 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
175 printf("Write MDIO failed...\n");
176 return -1;
177 }
178 }
179
180 /*
181 * clear MII interrupt bit
182 */
Marek Vasutd133b882011-09-11 18:05:34 +0000183 writel(FEC_IEVENT_MII, &eth->ievent);
Troy Kisky13947f42012-02-07 14:08:47 +0000184 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400185 regAddr, data);
186
187 return 0;
188}
189
Jeroen Hofstee84f64c82014-10-08 22:57:40 +0200190static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
191 int regAddr)
Troy Kisky13947f42012-02-07 14:08:47 +0000192{
193 return fec_mdio_read(bus->priv, phyAddr, regAddr);
194}
195
Jeroen Hofstee84f64c82014-10-08 22:57:40 +0200196static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
197 int regAddr, u16 data)
Troy Kisky13947f42012-02-07 14:08:47 +0000198{
199 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
200}
201
202#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400203static int miiphy_restart_aneg(struct eth_device *dev)
204{
Stefano Babicb774fe92012-02-22 00:24:35 +0000205 int ret = 0;
206#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200207 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000208 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200209
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400210 /*
211 * Wake up from sleep if necessary
212 * Reset PHY, then delay 300ns
213 */
John Rigbycb17b922010-01-25 23:12:55 -0700214#ifdef CONFIG_MX27
Troy Kisky13947f42012-02-07 14:08:47 +0000215 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700216#endif
Troy Kisky13947f42012-02-07 14:08:47 +0000217 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400218 udelay(1000);
219
220 /*
221 * Set the auto-negotiation advertisement register bits
222 */
Troy Kisky13947f42012-02-07 14:08:47 +0000223 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500224 LPA_100FULL | LPA_100HALF | LPA_10FULL |
225 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky13947f42012-02-07 14:08:47 +0000226 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500227 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000228
229 if (fec->mii_postcall)
230 ret = fec->mii_postcall(fec->phy_id);
231
Stefano Babicb774fe92012-02-22 00:24:35 +0000232#endif
Marek Vasut2e5f4422011-09-11 18:05:36 +0000233 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400234}
235
Hannes Schmelzer07507012016-06-22 12:07:14 +0200236#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400237static int miiphy_wait_aneg(struct eth_device *dev)
238{
239 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000240 int status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200241 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000242 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400243
244 /*
245 * Wait for AN completion
246 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000247 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400248 do {
249 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
250 printf("%s: Autonegotiation timeout\n", dev->name);
251 return -1;
252 }
253
Troy Kisky13947f42012-02-07 14:08:47 +0000254 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
255 if (status < 0) {
256 printf("%s: Autonegotiation failed. status: %d\n",
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400257 dev->name, status);
258 return -1;
259 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500260 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400261
262 return 0;
263}
Hannes Schmelzer07507012016-06-22 12:07:14 +0200264#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky13947f42012-02-07 14:08:47 +0000265#endif
266
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400267static int fec_rx_task_enable(struct fec_priv *fec)
268{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000269 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400270 return 0;
271}
272
273static int fec_rx_task_disable(struct fec_priv *fec)
274{
275 return 0;
276}
277
278static int fec_tx_task_enable(struct fec_priv *fec)
279{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000280 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400281 return 0;
282}
283
284static int fec_tx_task_disable(struct fec_priv *fec)
285{
286 return 0;
287}
288
289/**
290 * Initialize receive task's buffer descriptors
291 * @param[in] fec all we know about the device yet
292 * @param[in] count receive buffer count to be allocated
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000293 * @param[in] dsize desired size of each receive buffer
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400294 * @return 0 on success
295 *
Marek Vasut79e5f272013-10-12 20:36:25 +0200296 * Init all RX descriptors to default values.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400297 */
Marek Vasut79e5f272013-10-12 20:36:25 +0200298static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400299{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000300 uint32_t size;
Marek Vasut79e5f272013-10-12 20:36:25 +0200301 uint8_t *data;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000302 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400303
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400304 /*
Marek Vasut79e5f272013-10-12 20:36:25 +0200305 * Reload the RX descriptors with default values and wipe
306 * the RX buffers.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400307 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000308 size = roundup(dsize, ARCH_DMA_MINALIGN);
309 for (i = 0; i < count; i++) {
Marek Vasut79e5f272013-10-12 20:36:25 +0200310 data = (uint8_t *)fec->rbd_base[i].data_pointer;
311 memset(data, 0, dsize);
312 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
313
314 fec->rbd_base[i].status = FEC_RBD_EMPTY;
315 fec->rbd_base[i].data_length = 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000316 }
317
318 /* Mark the last RBD to close the ring. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200319 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400320 fec->rbd_index = 0;
321
Marek Vasut79e5f272013-10-12 20:36:25 +0200322 flush_dcache_range((unsigned)fec->rbd_base,
323 (unsigned)fec->rbd_base + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400324}
325
326/**
327 * Initialize transmit task's buffer descriptors
328 * @param[in] fec all we know about the device yet
329 *
330 * Transmit buffers are created externally. We only have to init the BDs here.\n
331 * Note: There is a race condition in the hardware. When only one BD is in
332 * use it must be marked with the WRAP bit to use it for every transmitt.
333 * This bit in combination with the READY bit results into double transmit
334 * of each data buffer. It seems the state machine checks READY earlier then
335 * resetting it after the first transfer.
336 * Using two BDs solves this issue.
337 */
338static void fec_tbd_init(struct fec_priv *fec)
339{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000340 unsigned addr = (unsigned)fec->tbd_base;
341 unsigned size = roundup(2 * sizeof(struct fec_bd),
342 ARCH_DMA_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200343
344 memset(fec->tbd_base, 0, size);
345 fec->tbd_base[0].status = 0;
346 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400347 fec->tbd_index = 0;
Marek Vasut79e5f272013-10-12 20:36:25 +0200348 flush_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400349}
350
351/**
352 * Mark the given read buffer descriptor as free
353 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
354 * @param[in] pRbd buffer descriptor to mark free again
355 */
356static void fec_rbd_clean(int last, struct fec_bd *pRbd)
357{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000358 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400359 if (last)
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000360 flags |= FEC_RBD_WRAP;
361 writew(flags, &pRbd->status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400362 writew(0, &pRbd->data_length);
363}
364
Fabio Estevambe252b62011-12-20 05:46:31 +0000365static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
366 unsigned char *mac)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400367{
Fabio Estevambe252b62011-12-20 05:46:31 +0000368 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500369 return !is_valid_ethaddr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400370}
371
Stefano Babic4294b242010-02-01 14:51:30 +0100372static int fec_set_hwaddr(struct eth_device *dev)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400373{
Stefano Babic4294b242010-02-01 14:51:30 +0100374 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400375 struct fec_priv *fec = (struct fec_priv *)dev->priv;
376
377 writel(0, &fec->eth->iaddr1);
378 writel(0, &fec->eth->iaddr2);
379 writel(0, &fec->eth->gaddr1);
380 writel(0, &fec->eth->gaddr2);
381
382 /*
383 * Set physical address
384 */
385 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
386 &fec->eth->paddr1);
387 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
388
389 return 0;
390}
391
Marek Vasuta5990b22012-05-01 11:09:41 +0000392/*
393 * Do initial configuration of the FEC registers
394 */
395static void fec_reg_setup(struct fec_priv *fec)
396{
397 uint32_t rcntrl;
398
399 /*
400 * Set interrupt mask register
401 */
402 writel(0x00000000, &fec->eth->imask);
403
404 /*
405 * Clear FEC-Lite interrupt event register(IEVENT)
406 */
407 writel(0xffffffff, &fec->eth->ievent);
408
409
410 /*
411 * Set FEC-Lite receive control register(R_CNTRL):
412 */
413
414 /* Start with frame length = 1518, common for all modes. */
415 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advans9d2d9242012-07-19 02:12:46 +0000416 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
417 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
418 if (fec->xcv_type == RGMII)
Marek Vasuta5990b22012-05-01 11:09:41 +0000419 rcntrl |= FEC_RCNTRL_RGMII;
420 else if (fec->xcv_type == RMII)
421 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasuta5990b22012-05-01 11:09:41 +0000422
423 writel(rcntrl, &fec->eth->r_cntrl);
424}
425
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400426/**
427 * Start the FEC engine
428 * @param[in] dev Our device to handle
429 */
430static int fec_open(struct eth_device *edev)
431{
432 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Troy Kisky28774cb2012-02-07 14:08:46 +0000433 int speed;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000434 uint32_t addr, size;
435 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400436
437 debug("fec_open: fec_open(dev)\n");
438 /* full-duplex, heartbeat disabled */
439 writel(1 << 2, &fec->eth->x_cntrl);
440 fec->rbd_index = 0;
441
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000442 /* Invalidate all descriptors */
443 for (i = 0; i < FEC_RBD_NUM - 1; i++)
444 fec_rbd_clean(0, &fec->rbd_base[i]);
445 fec_rbd_clean(1, &fec->rbd_base[i]);
446
447 /* Flush the descriptors into RAM */
448 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
449 ARCH_DMA_MINALIGN);
450 addr = (uint32_t)fec->rbd_base;
451 flush_dcache_range(addr, addr + size);
452
Troy Kisky28774cb2012-02-07 14:08:46 +0000453#ifdef FEC_QUIRK_ENET_MAC
Jason Liu2ef2b952011-12-16 05:17:07 +0000454 /* Enable ENET HW endian SWAP */
455 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
456 &fec->eth->ecntrl);
457 /* Enable ENET store and forward mode */
458 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
459 &fec->eth->x_wmrk);
460#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400461 /*
462 * Enable FEC-Lite controller
463 */
John Rigbycb17b922010-01-25 23:12:55 -0700464 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
465 &fec->eth->ecntrl);
Fabio Estevam7df51fd2013-09-13 00:36:27 -0300466#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700467 udelay(100);
468 /*
469 * setup the MII gasket for RMII mode
470 */
471
472 /* disable the gasket */
473 writew(0, &fec->eth->miigsk_enr);
474
475 /* wait for the gasket to be disabled */
476 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
477 udelay(2);
478
479 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
480 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
481
482 /* re-enable the gasket */
483 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
484
485 /* wait until MII gasket is ready */
486 int max_loops = 10;
487 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
488 if (--max_loops <= 0) {
489 printf("WAIT for MII Gasket ready timed out\n");
490 break;
491 }
492 }
493#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400494
Troy Kisky13947f42012-02-07 14:08:47 +0000495#ifdef CONFIG_PHYLIB
Troy Kisky4dc27ee2012-10-22 16:40:45 +0000496 {
Troy Kisky13947f42012-02-07 14:08:47 +0000497 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000498 int ret = phy_startup(fec->phydev);
499
500 if (ret) {
501 printf("Could not initialize PHY %s\n",
502 fec->phydev->dev->name);
503 return ret;
504 }
Troy Kisky13947f42012-02-07 14:08:47 +0000505 speed = fec->phydev->speed;
Troy Kisky13947f42012-02-07 14:08:47 +0000506 }
Hannes Schmelzer07507012016-06-22 12:07:14 +0200507#elif CONFIG_FEC_FIXED_SPEED
508 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky13947f42012-02-07 14:08:47 +0000509#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400510 miiphy_wait_aneg(edev);
Troy Kisky28774cb2012-02-07 14:08:46 +0000511 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200512 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky13947f42012-02-07 14:08:47 +0000513#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400514
Troy Kisky28774cb2012-02-07 14:08:46 +0000515#ifdef FEC_QUIRK_ENET_MAC
516 {
517 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wangbcb6e902013-05-27 22:55:43 +0000518 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky28774cb2012-02-07 14:08:46 +0000519 if (speed == _1000BASET)
520 ecr |= FEC_ECNTRL_SPEED;
521 else if (speed != _100BASET)
522 rcr |= FEC_RCNTRL_RMII_10T;
523 writel(ecr, &fec->eth->ecntrl);
524 writel(rcr, &fec->eth->r_cntrl);
525 }
526#endif
527 debug("%s:Speed=%i\n", __func__, speed);
528
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400529 /*
530 * Enable SmartDMA receive task
531 */
532 fec_rx_task_enable(fec);
533
534 udelay(100000);
535 return 0;
536}
537
538static int fec_init(struct eth_device *dev, bd_t* bd)
539{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400540 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200541 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
Marek Vasut79e5f272013-10-12 20:36:25 +0200542 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400543
John Rigbye9319f12010-10-13 14:31:08 -0600544 /* Initialize MAC address */
545 fec_set_hwaddr(dev);
546
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400547 /*
Marek Vasut79e5f272013-10-12 20:36:25 +0200548 * Setup transmit descriptors, there are two in total.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400549 */
Marek Vasut79e5f272013-10-12 20:36:25 +0200550 fec_tbd_init(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400551
Marek Vasut79e5f272013-10-12 20:36:25 +0200552 /* Setup receive descriptors. */
553 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400554
Marek Vasuta5990b22012-05-01 11:09:41 +0000555 fec_reg_setup(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000556
benoit.thebaudeau@advansf41471e2012-07-19 02:12:58 +0000557 if (fec->xcv_type != SEVENWIRE)
Troy Kisky575c5cc2012-10-22 16:40:41 +0000558 fec_mii_setspeed(fec->bus->priv);
Marek Vasut9eb37702011-09-11 18:05:31 +0000559
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400560 /*
561 * Set Opcode/Pause Duration Register
562 */
563 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
564 writel(0x2, &fec->eth->x_wmrk);
565 /*
566 * Set multicast address filter
567 */
568 writel(0x00000000, &fec->eth->gaddr1);
569 writel(0x00000000, &fec->eth->gaddr2);
570
571
Peng Fanfbecbaa2015-08-12 17:46:51 +0800572 /* Do not access reserved register for i.MX6UL */
Peng Fan87f99892016-05-23 18:36:04 +0800573 if (!is_mx6ul()) {
Peng Fanfbecbaa2015-08-12 17:46:51 +0800574 /* clear MIB RAM */
575 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
576 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400577
Peng Fanfbecbaa2015-08-12 17:46:51 +0800578 /* FIFO receive start register */
579 writel(0x520, &fec->eth->r_fstart);
580 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400581
582 /* size and address of each buffer */
583 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
584 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
585 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
586
Troy Kisky13947f42012-02-07 14:08:47 +0000587#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400588 if (fec->xcv_type != SEVENWIRE)
589 miiphy_restart_aneg(dev);
Troy Kisky13947f42012-02-07 14:08:47 +0000590#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400591 fec_open(dev);
592 return 0;
593}
594
595/**
596 * Halt the FEC engine
597 * @param[in] dev Our device to handle
598 */
599static void fec_halt(struct eth_device *dev)
600{
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200601 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400602 int counter = 0xffff;
603
604 /*
605 * issue graceful stop command to the FEC transmitter if necessary
606 */
John Rigbycb17b922010-01-25 23:12:55 -0700607 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400608 &fec->eth->x_cntrl);
609
610 debug("eth_halt: wait for stop regs\n");
611 /*
612 * wait for graceful stop to register
613 */
614 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700615 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400616
617 /*
618 * Disable SmartDMA tasks
619 */
620 fec_tx_task_disable(fec);
621 fec_rx_task_disable(fec);
622
623 /*
624 * Disable the Ethernet Controller
625 * Note: this will also reset the BD index counter!
626 */
John Rigby740d6ae2010-01-25 23:12:57 -0700627 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
628 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400629 fec->rbd_index = 0;
630 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400631 debug("eth_halt: done\n");
632}
633
634/**
635 * Transmit one frame
636 * @param[in] dev Our ethernet device to handle
637 * @param[in] packet Pointer to the data to be transmitted
638 * @param[in] length Data count in bytes
639 * @return 0 on success
640 */
Joe Hershberger442dac42012-05-21 14:45:27 +0000641static int fec_send(struct eth_device *dev, void *packet, int length)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400642{
643 unsigned int status;
Marek Vasutefe24d22012-08-26 10:19:21 +0000644 uint32_t size, end;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000645 uint32_t addr;
Marek Vasutbc1ce152012-08-29 03:49:49 +0000646 int timeout = FEC_XFER_TIMEOUT;
647 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400648
649 /*
650 * This routine transmits one frame. This routine only accepts
651 * 6-byte Ethernet addresses.
652 */
653 struct fec_priv *fec = (struct fec_priv *)dev->priv;
654
655 /*
656 * Check for valid length of data.
657 */
658 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100659 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400660 return -1;
661 }
662
663 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000664 * Setup the transmit buffer. We are always using the first buffer for
665 * transmission, the second will be empty and only used to stop the DMA
666 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400667 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000668#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000669 swap_packet((uint32_t *)packet, length);
670#endif
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000671
672 addr = (uint32_t)packet;
Marek Vasutefe24d22012-08-26 10:19:21 +0000673 end = roundup(addr + length, ARCH_DMA_MINALIGN);
674 addr &= ~(ARCH_DMA_MINALIGN - 1);
675 flush_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000676
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400677 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000678 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
679
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400680 /*
681 * update BD's status now
682 * This block:
683 * - is always the last in a chain (means no chain)
684 * - should transmitt the CRC
685 * - might be the last BD in the list, so the address counter should
686 * wrap (-> keep the WRAP flag)
687 */
688 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
689 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
690 writew(status, &fec->tbd_base[fec->tbd_index].status);
691
692 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000693 * Flush data cache. This code flushes both TX descriptors to RAM.
694 * After this code, the descriptors will be safely in RAM and we
695 * can start DMA.
696 */
697 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
698 addr = (uint32_t)fec->tbd_base;
699 flush_dcache_range(addr, addr + size);
700
701 /*
Marek Vasutab94cd42013-07-12 01:03:04 +0200702 * Below we read the DMA descriptor's last four bytes back from the
703 * DRAM. This is important in order to make sure that all WRITE
704 * operations on the bus that were triggered by previous cache FLUSH
705 * have completed.
706 *
707 * Otherwise, on MX28, it is possible to observe a corruption of the
708 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
709 * for the bus structure of MX28. The scenario is as follows:
710 *
711 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
712 * to DRAM due to flush_dcache_range()
713 * 2) ARM core writes the FEC registers via AHB_ARB2
714 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
715 *
716 * Note that 2) does sometimes finish before 1) due to reordering of
717 * WRITE accesses on the AHB bus, therefore triggering 3) before the
718 * DMA descriptor is fully written into DRAM. This results in occasional
719 * corruption of the DMA descriptor.
720 */
721 readl(addr + size - 4);
722
723 /*
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400724 * Enable SmartDMA transmit task
725 */
726 fec_tx_task_enable(fec);
727
728 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000729 * Wait until frame is sent. On each turn of the wait cycle, we must
730 * invalidate data cache to see what's really in RAM. Also, we need
731 * barrier here.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400732 */
Marek Vasut67449092012-08-29 03:49:50 +0000733 while (--timeout) {
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000734 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasutbc1ce152012-08-29 03:49:49 +0000735 break;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400736 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000737
Fabio Estevamf5992882014-08-25 13:34:17 -0300738 if (!timeout) {
739 ret = -EINVAL;
740 goto out;
741 }
742
743 /*
744 * The TDAR bit is cleared when the descriptors are all out from TX
745 * but on mx6solox we noticed that the READY bit is still not cleared
746 * right after TDAR.
747 * These are two distinct signals, and in IC simulation, we found that
748 * TDAR always gets cleared prior than the READY bit of last BD becomes
749 * cleared.
750 * In mx6solox, we use a later version of FEC IP. It looks like that
751 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
752 * version.
753 *
754 * Fix this by polling the READY bit of BD after the TDAR polling,
755 * which covers the mx6solox case and does not harm the other SoCs.
756 */
757 timeout = FEC_XFER_TIMEOUT;
758 while (--timeout) {
759 invalidate_dcache_range(addr, addr + size);
760 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
761 FEC_TBD_READY))
762 break;
763 }
764
Marek Vasut67449092012-08-29 03:49:50 +0000765 if (!timeout)
766 ret = -EINVAL;
767
Fabio Estevamf5992882014-08-25 13:34:17 -0300768out:
Marek Vasut67449092012-08-29 03:49:50 +0000769 debug("fec_send: status 0x%x index %d ret %i\n",
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400770 readw(&fec->tbd_base[fec->tbd_index].status),
Marek Vasut67449092012-08-29 03:49:50 +0000771 fec->tbd_index, ret);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400772 /* for next transmission use the other buffer */
773 if (fec->tbd_index)
774 fec->tbd_index = 0;
775 else
776 fec->tbd_index = 1;
777
Marek Vasutbc1ce152012-08-29 03:49:49 +0000778 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400779}
780
781/**
782 * Pull one frame from the card
783 * @param[in] dev Our ethernet device to handle
784 * @return Length of packet read
785 */
786static int fec_recv(struct eth_device *dev)
787{
788 struct fec_priv *fec = (struct fec_priv *)dev->priv;
789 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
790 unsigned long ievent;
791 int frame_length, len = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400792 uint16_t bd_status;
Marek Vasutefe24d22012-08-26 10:19:21 +0000793 uint32_t addr, size, end;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000794 int i;
Fabio Estevamfd37f192013-09-17 23:13:10 -0300795 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400796
797 /*
798 * Check if any critical events have happened
799 */
800 ievent = readl(&fec->eth->ievent);
801 writel(ievent, &fec->eth->ievent);
Marek Vasuteda959f2011-10-24 23:40:03 +0000802 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400803 if (ievent & FEC_IEVENT_BABR) {
804 fec_halt(dev);
805 fec_init(dev, fec->bd);
806 printf("some error: 0x%08lx\n", ievent);
807 return 0;
808 }
809 if (ievent & FEC_IEVENT_HBERR) {
810 /* Heartbeat error */
811 writel(0x00000001 | readl(&fec->eth->x_cntrl),
812 &fec->eth->x_cntrl);
813 }
814 if (ievent & FEC_IEVENT_GRA) {
815 /* Graceful stop complete */
816 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
817 fec_halt(dev);
818 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
819 &fec->eth->x_cntrl);
820 fec_init(dev, fec->bd);
821 }
822 }
823
824 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000825 * Read the buffer status. Before the status can be read, the data cache
826 * must be invalidated, because the data in RAM might have been changed
827 * by DMA. The descriptors are properly aligned to cachelines so there's
828 * no need to worry they'd overlap.
829 *
830 * WARNING: By invalidating the descriptor here, we also invalidate
831 * the descriptors surrounding this one. Therefore we can NOT change the
832 * contents of this descriptor nor the surrounding ones. The problem is
833 * that in order to mark the descriptor as processed, we need to change
834 * the descriptor. The solution is to mark the whole cache line when all
835 * descriptors in the cache line are processed.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400836 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000837 addr = (uint32_t)rbd;
838 addr &= ~(ARCH_DMA_MINALIGN - 1);
839 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
840 invalidate_dcache_range(addr, addr + size);
841
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400842 bd_status = readw(&rbd->status);
843 debug("fec_recv: status 0x%x\n", bd_status);
844
845 if (!(bd_status & FEC_RBD_EMPTY)) {
846 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
847 ((readw(&rbd->data_length) - 4) > 14)) {
848 /*
849 * Get buffer address and size
850 */
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200851 addr = readl(&rbd->data_pointer);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400852 frame_length = readw(&rbd->data_length) - 4;
853 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000854 * Invalidate data cache over the buffer
855 */
Marek Vasutefe24d22012-08-26 10:19:21 +0000856 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
857 addr &= ~(ARCH_DMA_MINALIGN - 1);
858 invalidate_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000859
860 /*
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400861 * Fill the buffer and pass it to upper layers
862 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000863#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200864 swap_packet((uint32_t *)addr, frame_length);
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000865#endif
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200866 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500867 net_process_received_packet(buff, frame_length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400868 len = frame_length;
869 } else {
870 if (bd_status & FEC_RBD_ERR)
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200871 printf("error frame: 0x%08x 0x%08x\n",
872 addr, bd_status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400873 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000874
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400875 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000876 * Free the current buffer, restart the engine and move forward
877 * to the next buffer. Here we check if the whole cacheline of
878 * descriptors was already processed and if so, we mark it free
879 * as whole.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400880 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000881 size = RXDESC_PER_CACHELINE - 1;
882 if ((fec->rbd_index & size) == size) {
883 i = fec->rbd_index - size;
884 addr = (uint32_t)&fec->rbd_base[i];
885 for (; i <= fec->rbd_index ; i++) {
886 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
887 &fec->rbd_base[i]);
888 }
889 flush_dcache_range(addr,
890 addr + ARCH_DMA_MINALIGN);
891 }
892
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400893 fec_rx_task_enable(fec);
894 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
895 }
896 debug("fec_recv: stop\n");
897
898 return len;
899}
900
Troy Kiskyef8e3a32012-10-22 16:40:44 +0000901static void fec_set_dev_name(char *dest, int dev_id)
902{
903 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
904}
905
Marek Vasut79e5f272013-10-12 20:36:25 +0200906static int fec_alloc_descs(struct fec_priv *fec)
907{
908 unsigned int size;
909 int i;
910 uint8_t *data;
911
912 /* Allocate TX descriptors. */
913 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
914 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
915 if (!fec->tbd_base)
916 goto err_tx;
917
918 /* Allocate RX descriptors. */
919 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
920 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
921 if (!fec->rbd_base)
922 goto err_rx;
923
924 memset(fec->rbd_base, 0, size);
925
926 /* Allocate RX buffers. */
927
928 /* Maximum RX buffer size. */
Fabio Estevamdb5b7f52014-08-25 13:34:16 -0300929 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200930 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevamdb5b7f52014-08-25 13:34:16 -0300931 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200932 if (!data) {
933 printf("%s: error allocating rxbuf %d\n", __func__, i);
934 goto err_ring;
935 }
936
937 memset(data, 0, size);
938
939 fec->rbd_base[i].data_pointer = (uint32_t)data;
940 fec->rbd_base[i].status = FEC_RBD_EMPTY;
941 fec->rbd_base[i].data_length = 0;
942 /* Flush the buffer to memory. */
943 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
944 }
945
946 /* Mark the last RBD to close the ring. */
947 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
948
949 fec->rbd_index = 0;
950 fec->tbd_index = 0;
951
952 return 0;
953
954err_ring:
955 for (; i >= 0; i--)
956 free((void *)fec->rbd_base[i].data_pointer);
957 free(fec->rbd_base);
958err_rx:
959 free(fec->tbd_base);
960err_tx:
961 return -ENOMEM;
962}
963
964static void fec_free_descs(struct fec_priv *fec)
965{
966 int i;
967
968 for (i = 0; i < FEC_RBD_NUM; i++)
969 free((void *)fec->rbd_base[i].data_pointer);
970 free(fec->rbd_base);
971 free(fec->tbd_base);
972}
973
Troy Kiskyfe428b92012-10-22 16:40:46 +0000974#ifdef CONFIG_PHYLIB
975int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
976 struct mii_dev *bus, struct phy_device *phydev)
977#else
978static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
979 struct mii_dev *bus, int phy_id)
980#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400981{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400982 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200983 struct fec_priv *fec;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400984 unsigned char ethaddr[6];
Marek Vasute382fb42011-09-11 18:05:37 +0000985 uint32_t start;
986 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400987
988 /* create and fill edev struct */
989 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
990 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200991 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000992 ret = -ENOMEM;
993 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400994 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200995
996 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
997 if (!fec) {
998 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000999 ret = -ENOMEM;
1000 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001001 }
1002
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +09001003 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001004 memset(fec, 0, sizeof(*fec));
1005
Marek Vasut79e5f272013-10-12 20:36:25 +02001006 ret = fec_alloc_descs(fec);
1007 if (ret)
1008 goto err3;
1009
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001010 edev->priv = fec;
1011 edev->init = fec_init;
1012 edev->send = fec_send;
1013 edev->recv = fec_recv;
1014 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +02001015 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001016
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001017 fec->eth = (struct ethernet_regs *)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001018 fec->bd = bd;
1019
Marek Vasut392b8502011-09-11 18:05:33 +00001020 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001021
1022 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -07001023 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +00001024 start = get_timer(0);
1025 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1026 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1027 printf("FEC MXC: Timeout reseting chip\n");
Marek Vasut79e5f272013-10-12 20:36:25 +02001028 goto err4;
Marek Vasute382fb42011-09-11 18:05:37 +00001029 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001030 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +00001031 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001032
Marek Vasuta5990b22012-05-01 11:09:41 +00001033 fec_reg_setup(fec);
Troy Kiskyef8e3a32012-10-22 16:40:44 +00001034 fec_set_dev_name(edev->name, dev_id);
1035 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kisky13947f42012-02-07 14:08:47 +00001036 fec->bus = bus;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001037 fec_mii_setspeed(bus->priv);
1038#ifdef CONFIG_PHYLIB
1039 fec->phydev = phydev;
1040 phy_connect_dev(phydev, edev);
1041 /* Configure phy */
1042 phy_config(phydev);
1043#else
1044 fec->phy_id = phy_id;
1045#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001046 eth_register(edev);
1047
Fabio Estevambe252b62011-12-20 05:46:31 +00001048 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1049 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +01001050 memcpy(edev->enetaddr, ethaddr, 6);
Eric Nelsonddb636b2013-08-02 10:37:00 -07001051 if (!getenv("ethaddr"))
1052 eth_setenv_enetaddr("ethaddr", ethaddr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001053 }
Marek Vasute382fb42011-09-11 18:05:37 +00001054 return ret;
Marek Vasut79e5f272013-10-12 20:36:25 +02001055err4:
1056 fec_free_descs(fec);
Marek Vasute382fb42011-09-11 18:05:37 +00001057err3:
1058 free(fec);
1059err2:
1060 free(edev);
1061err1:
1062 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001063}
1064
Troy Kiskyfe428b92012-10-22 16:40:46 +00001065struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1066{
1067 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1068 struct mii_dev *bus;
1069 int ret;
1070
1071 bus = mdio_alloc();
1072 if (!bus) {
1073 printf("mdio_alloc failed\n");
1074 return NULL;
1075 }
1076 bus->read = fec_phy_read;
1077 bus->write = fec_phy_write;
1078 bus->priv = eth;
1079 fec_set_dev_name(bus->name, dev_id);
1080
1081 ret = mdio_register(bus);
1082 if (ret) {
1083 printf("mdio_register failed\n");
1084 free(bus);
1085 return NULL;
1086 }
1087 fec_mii_setspeed(eth);
1088 return bus;
1089}
1090
Troy Kiskyeef24482012-10-22 16:40:42 +00001091int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1092{
Troy Kiskyfe428b92012-10-22 16:40:46 +00001093 uint32_t base_mii;
1094 struct mii_dev *bus = NULL;
1095#ifdef CONFIG_PHYLIB
1096 struct phy_device *phydev = NULL;
1097#endif
1098 int ret;
1099
1100#ifdef CONFIG_MX28
1101 /*
1102 * The i.MX28 has two ethernet interfaces, but they are not equal.
1103 * Only the first one can access the MDIO bus.
1104 */
1105 base_mii = MXS_ENET0_BASE;
1106#else
1107 base_mii = addr;
1108#endif
Troy Kiskyeef24482012-10-22 16:40:42 +00001109 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001110 bus = fec_get_miibus(base_mii, dev_id);
1111 if (!bus)
1112 return -ENOMEM;
1113#ifdef CONFIG_PHYLIB
1114 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1115 if (!phydev) {
Måns Rullgård845a57b2015-12-08 15:38:46 +00001116 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001117 free(bus);
1118 return -ENOMEM;
1119 }
1120 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1121#else
1122 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1123#endif
1124 if (ret) {
1125#ifdef CONFIG_PHYLIB
1126 free(phydev);
1127#endif
Måns Rullgård845a57b2015-12-08 15:38:46 +00001128 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001129 free(bus);
1130 }
1131 return ret;
Troy Kiskyeef24482012-10-22 16:40:42 +00001132}
1133
Troy Kisky09439c32012-10-22 16:40:40 +00001134#ifdef CONFIG_FEC_MXC_PHYADDR
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001135int fecmxc_initialize(bd_t *bd)
1136{
Troy Kiskyeef24482012-10-22 16:40:42 +00001137 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1138 IMX_FEC_BASE);
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001139}
1140#endif
1141
Troy Kisky13947f42012-02-07 14:08:47 +00001142#ifndef CONFIG_PHYLIB
Marek Vasut2e5f4422011-09-11 18:05:36 +00001143int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1144{
1145 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1146 fec->mii_postcall = cb;
1147 return 0;
1148}
Troy Kisky13947f42012-02-07 14:08:47 +00001149#endif