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Tom Rix23b80982009-09-27 11:10:09 -05001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
Eric Benard95d50e52011-06-06 22:48:28 +00007 * (C) Copyright 2009-2011
Tom Rix23b80982009-09-27 11:10:09 -05008 * Eric Benard <eric@eukrea.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
Eric Benard95d50e52011-06-06 22:48:28 +000030#include <asm/io.h>
Tom Rix23b80982009-09-27 11:10:09 -050031#include <asm/arch/at91sam9260.h>
Tom Rix23b80982009-09-27 11:10:09 -050032#include <asm/arch/at91sam9_smc.h>
33#include <asm/arch/at91_common.h>
Eric Benard95d50e52011-06-06 22:48:28 +000034#include <asm/arch/at91_matrix.h>
Tom Rix23b80982009-09-27 11:10:09 -050035#include <asm/arch/at91_pmc.h>
36#include <asm/arch/at91_rstc.h>
Eric Benardc2b2a072011-04-03 06:35:54 +000037#include <asm/arch/at91_pio.h>
38#include <asm/arch/clk.h>
Tom Rix23b80982009-09-27 11:10:09 -050039#include <asm/arch/hardware.h>
40#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
41#include <net.h>
42#endif
43#include <netdev.h>
44
45DECLARE_GLOBAL_DATA_PTR;
46
47/* ------------------------------------------------------------------------- */
48/*
49 * Miscelaneous platform dependent initialisations
50 */
51
52#ifdef CONFIG_CMD_NAND
53static void cpu9260_nand_hw_init(void)
54{
55 unsigned long csa;
Eric Benard95d50e52011-06-06 22:48:28 +000056 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
57 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
58 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Tom Rix23b80982009-09-27 11:10:09 -050059
60 /* Enable CS3 */
Eric Benardc2b2a072011-04-03 06:35:54 +000061 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
62 writel(csa, &matrix->csa);
Tom Rix23b80982009-09-27 11:10:09 -050063
64 /* Configure SMC CS3 for NAND/SmartMedia */
65#if defined(CONFIG_CPU9G20)
Eric Benardc2b2a072011-04-03 06:35:54 +000066 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
67 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
68 &smc->cs[3].setup);
69 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
70 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
71 &smc->cs[3].pulse);
72 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
73 &smc->cs[3].cycle);
74 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
75 AT91_SMC_MODE_EXNW_DISABLE |
76 AT91_SMC_MODE_DBW_8 |
77 AT91_SMC_MODE_TDF_CYCLE(3),
78 &smc->cs[3].mode);
Tom Rix23b80982009-09-27 11:10:09 -050079#elif defined(CONFIG_CPU9260)
Eric Benardc2b2a072011-04-03 06:35:54 +000080 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
81 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
82 &smc->cs[3].setup);
83 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
84 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
85 &smc->cs[3].pulse);
86 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
87 &smc->cs[3].cycle);
88 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
89 AT91_SMC_MODE_EXNW_DISABLE |
90 AT91_SMC_MODE_DBW_8 |
91 AT91_SMC_MODE_TDF_CYCLE(2),
92 &smc->cs[3].mode);
Tom Rix23b80982009-09-27 11:10:09 -050093#endif
94
Eric Benard95d50e52011-06-06 22:48:28 +000095 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
Tom Rix23b80982009-09-27 11:10:09 -050096
97 /* Configure RDY/BSY */
Eric Benardc2b2a072011-04-03 06:35:54 +000098 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Tom Rix23b80982009-09-27 11:10:09 -050099
100 /* Enable NandFlash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000101 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Tom Rix23b80982009-09-27 11:10:09 -0500102}
103#endif
104
105#ifdef CONFIG_MACB
106static void cpu9260_macb_hw_init(void)
107{
Eric Benardc2b2a072011-04-03 06:35:54 +0000108 unsigned long rstcmr;
Eric Benard95d50e52011-06-06 22:48:28 +0000109 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
110 at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
Tom Rix23b80982009-09-27 11:10:09 -0500111
112 /* Enable clock */
Eric Benard95d50e52011-06-06 22:48:28 +0000113 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
Tom Rix23b80982009-09-27 11:10:09 -0500114
Eric Benardc2b2a072011-04-03 06:35:54 +0000115 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
Tom Rix23b80982009-09-27 11:10:09 -0500116
Eric Benardc2b2a072011-04-03 06:35:54 +0000117 rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
Tom Rix23b80982009-09-27 11:10:09 -0500118
119 /* Need to reset PHY -> 500ms reset */
Eric Benardc2b2a072011-04-03 06:35:54 +0000120 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
121 AT91_RSTC_MR_URSTEN, &rstc->mr);
Tom Rix23b80982009-09-27 11:10:09 -0500122
Eric Benardc2b2a072011-04-03 06:35:54 +0000123 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
Tom Rix23b80982009-09-27 11:10:09 -0500124
125 /* Wait for end hardware reset */
Eric Benardc2b2a072011-04-03 06:35:54 +0000126 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
Tom Rix23b80982009-09-27 11:10:09 -0500127 ;
128
129 /* Restore NRST value */
Eric Benardc2b2a072011-04-03 06:35:54 +0000130 writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
Tom Rix23b80982009-09-27 11:10:09 -0500131
132 at91_macb_hw_init();
133}
134#endif
135
Eric Benardc2b2a072011-04-03 06:35:54 +0000136int board_early_init_f(void)
137{
Eric Benard95d50e52011-06-06 22:48:28 +0000138 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Eric Benardc2b2a072011-04-03 06:35:54 +0000139
Eric Benard95d50e52011-06-06 22:48:28 +0000140 writel((1 << ATMEL_ID_PIOA) |
141 (1 << ATMEL_ID_PIOB) |
142 (1 << ATMEL_ID_PIOC),
Eric Benardc2b2a072011-04-03 06:35:54 +0000143 &pmc->pcer);
144
Eric Benard95d50e52011-06-06 22:48:28 +0000145 at91_seriald_hw_init();
Eric Benardc2b2a072011-04-03 06:35:54 +0000146
147 return 0;
148}
149
150
Tom Rix23b80982009-09-27 11:10:09 -0500151int board_init(void)
152{
Tom Rix23b80982009-09-27 11:10:09 -0500153 /* arch number of the board */
154#if defined(CONFIG_CPU9G20)
Eric Benard94d50c52009-10-12 10:08:20 +0200155 gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
Tom Rix23b80982009-09-27 11:10:09 -0500156#elif defined(CONFIG_CPU9260)
157 gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
158#endif
159
160 /* adress of boot parameters */
Eric Benardc2b2a072011-04-03 06:35:54 +0000161 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Tom Rix23b80982009-09-27 11:10:09 -0500162
Tom Rix23b80982009-09-27 11:10:09 -0500163#ifdef CONFIG_CMD_NAND
164 cpu9260_nand_hw_init();
165#endif
166#ifdef CONFIG_MACB
167 cpu9260_macb_hw_init();
168#endif
169#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
170 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
171#endif
172 return 0;
173}
174
175int dram_init(void)
176{
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000177 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
Eric Benardc2b2a072011-04-03 06:35:54 +0000178 CONFIG_SYS_SDRAM_SIZE);
Tom Rix23b80982009-09-27 11:10:09 -0500179 return 0;
180}
181
Tom Rix23b80982009-09-27 11:10:09 -0500182int board_eth_init(bd_t *bis)
183{
184 int rc = 0;
185#ifdef CONFIG_MACB
Eric Benard95d50e52011-06-06 22:48:28 +0000186 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
Tom Rix23b80982009-09-27 11:10:09 -0500187#endif
188 return rc;
189}