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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2004
5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk082acfd2005-01-10 00:01:04 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk8ed96042005-01-09 23:16:25 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
28#include <version.h>
29#include <asm/arch/omap2420.h>
30#include <asm/arch/mem.h>
31#include <asm/arch/clocks.h>
32
33_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +020034 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
wdenk8ed96042005-01-09 23:16:25 +000035
wdenk8ed96042005-01-09 23:16:25 +000036/**************************************************************************
37 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
38 * R1 = SRAM destination address.
39 *************************************************************************/
40.global cpy_clk_code
41 cpy_clk_code:
wdenk082acfd2005-01-10 00:01:04 +000042 /* Copy DPLL code into SRAM */
43 adr r0, go_to_speed /* get addr of clock setting code */
44 mov r2, #384 /* r2 size to copy (div by 32 bytes) */
45 mov r1, r1 /* r1 <- dest address (passed in) */
46 add r2, r2, r0 /* r2 <- source end address */
wdenk8ed96042005-01-09 23:16:25 +000047next2:
wdenk082acfd2005-01-10 00:01:04 +000048 ldmia r0!, {r3-r10} /* copy from source address [r0] */
49 stmia r1!, {r3-r10} /* copy to target address [r1] */
50 cmp r0, r2 /* until source end address [r2] */
51 bne next2
52 mov pc, lr /* back to caller */
wdenk8ed96042005-01-09 23:16:25 +000053
wdenk082acfd2005-01-10 00:01:04 +000054/* ****************************************************************************
wdenk8ed96042005-01-09 23:16:25 +000055 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
wdenk082acfd2005-01-10 00:01:04 +000056 * -executed from SRAM.
wdenk8ed96042005-01-09 23:16:25 +000057 * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
58 * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
59 * R2 = dpll value
60 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
wdenk082acfd2005-01-10 00:01:04 +000061 ******************************************************************************/
wdenk8ed96042005-01-09 23:16:25 +000062.global go_to_speed
63 go_to_speed:
wdenk082acfd2005-01-10 00:01:04 +000064 sub sp, sp, #0x4 /* get some stack space */
65 str r4, [sp] /* save r4's value */
wdenk8ed96042005-01-09 23:16:25 +000066
wdenk082acfd2005-01-10 00:01:04 +000067 /* move into fast relock bypass */
68 ldr r8, pll_ctl_add
69 mov r4, #0x2
70 str r4, [r8]
71 ldr r4, pll_stat
wdenk8ed96042005-01-09 23:16:25 +000072block:
wdenk082acfd2005-01-10 00:01:04 +000073 ldr r8, [r4] /* wait for bypass to take effect */
74 and r8, r8, #0x3
75 cmp r8, #0x1
76 bne block
wdenk8ed96042005-01-09 23:16:25 +000077
78 /* set new dpll dividers _after_ in bypass */
wdenk082acfd2005-01-10 00:01:04 +000079 ldr r4, pll_div_add
80 ldr r8, pll_div_val
81 str r8, [r4]
wdenk8ed96042005-01-09 23:16:25 +000082
wdenk082acfd2005-01-10 00:01:04 +000083 /* now prepare GPMC (flash) for new dpll speed */
84 /* flash needs to be stable when we jump back to it */
85 ldr r4, cfg3_0_addr
86 ldr r8, cfg3_0_val
87 str r8, [r4]
88 ldr r4, cfg4_0_addr
89 ldr r8, cfg4_0_val
90 str r8, [r4]
91 ldr r4, cfg1_0_addr
92 ldr r8, [r4]
93 orr r8, r8, #0x3 /* up gpmc divider */
94 str r8, [r4]
95
96 /* setup to 2x loop though code. The first loop pre-loads the
97 * icache, the 2nd commits the prcm config, and locks the dpll
98 */
99 mov r4, #0x1000 /* spin spin spin */
100 mov r8, #0x4 /* first pass condition & set registers */
101 cmp r8, #0x4
wdenk8ed96042005-01-09 23:16:25 +00001022:
wdenk082acfd2005-01-10 00:01:04 +0000103 ldrne r8, [r3] /* DPLL lock check */
104 and r8, r8, #0x7
105 cmp r8, #0x2
106 beq 4f
wdenk8ed96042005-01-09 23:16:25 +00001073:
wdenk082acfd2005-01-10 00:01:04 +0000108 subeq r8, r8, #0x1
109 streq r8, [r0] /* commit dividers (2nd time) */
110 nop
wdenk8ed96042005-01-09 23:16:25 +0000111lloop1:
wdenk082acfd2005-01-10 00:01:04 +0000112 sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
113 nop
114 cmp r4, #0x0
115 bne lloop1
116 mov r4, #0x40000
117 cmp r8, #0x1
118 nop
119 streq r2, [r1] /* lock dpll (2nd time) */
120 nop
wdenk8ed96042005-01-09 23:16:25 +0000121lloop2:
wdenk082acfd2005-01-10 00:01:04 +0000122 sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
123 nop
124 cmp r4, #0x0
125 bne lloop2
126 mov r4, #0x40000
127 cmp r8, #0x1
128 nop
129 ldreq r8, [r3] /* get lock condition for dpll */
130 cmp r8, #0x4 /* first time though? */
131 bne 2b
132 moveq r8, #0x2 /* set to dpll check condition. */
133 beq 3b /* if condition not true branch */
1344:
135 ldr r4, [sp]
136 add sp, sp, #0x4 /* return stack space */
137 mov pc, lr /* back to caller, locked */
wdenk8ed96042005-01-09 23:16:25 +0000138
139_go_to_speed: .word go_to_speed
140
141/* these constants need to be close for PIC code */
142cfg3_0_addr:
143 .word GPMC_CONFIG3_0
wdenk082acfd2005-01-10 00:01:04 +0000144cfg3_0_val:
wdenk8ed96042005-01-09 23:16:25 +0000145 .word H4_24XX_GPMC_CONFIG3_0
146cfg4_0_addr:
147 .word GPMC_CONFIG4_0
148cfg4_0_val:
149 .word H4_24XX_GPMC_CONFIG4_0
150cfg1_0_addr:
151 .word GPMC_CONFIG1_0
152pll_ctl_add:
153 .word CM_CLKEN_PLL
154pll_stat:
155 .word CM_IDLEST_CKGEN
156pll_div_add:
wdenk082acfd2005-01-10 00:01:04 +0000157 .word CM_CLKSEL1_PLL
wdenk8ed96042005-01-09 23:16:25 +0000158pll_div_val:
159 .word DPLL_VAL /* DPLL setting (300MHz default) */
wdenk8ed96042005-01-09 23:16:25 +0000160
Wolfgang Denk87cb6862005-10-06 17:08:18 +0200161.globl lowlevel_init
162lowlevel_init:
wdenk8ed96042005-01-09 23:16:25 +0000163 ldr sp, SRAM_STACK
wdenk082acfd2005-01-10 00:01:04 +0000164 str ip, [sp] /* stash old link register */
wdenk8ed96042005-01-09 23:16:25 +0000165 mov ip, lr /* save link reg across call */
wdenk082acfd2005-01-10 00:01:04 +0000166 bl s_init /* go setup pll,mux,memory */
167 ldr ip, [sp] /* restore save ip */
wdenk8ed96042005-01-09 23:16:25 +0000168 mov lr, ip /* restore link reg */
wdenk289f9322005-01-12 00:15:14 +0000169
wdenk8ed96042005-01-09 23:16:25 +0000170 /* map interrupt controller */
171 ldr r0, VAL_INTH_SETUP
172 mcr p15, 0, r0, c15, c2, 4
173
174 /* back to arch calling code */
175 mov pc, lr
176
177 /* the literal pools origin */
178 .ltorg
179
180REG_CONTROL_STATUS:
181 .word CONTROL_STATUS
182VAL_INTH_SETUP:
183 .word PERIFERAL_PORT_BASE
184SRAM_STACK:
185 .word LOW_LEVEL_SRAM_STACK