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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
Timur Tabi7a78f142007-01-31 15:54:29 -060024 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -060025
26 Memory map:
27
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060034 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060035 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060036 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060039
40 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010041 Align. Board
42 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060043 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010044 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060045
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010046 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060052
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
54*/
55
56#ifndef __CONFIG_H
57#define __CONFIG_H
58
Wolfgang Denk14d0a022010-10-07 21:51:12 +020059#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_LOWBOOT
Timur Tabi7a78f142007-01-31 15:54:29 -060061#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060062
63/*
64 * High Level Configuration Options
65 */
Kim Phillips1a2e2032010-04-20 19:37:54 -050066#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050067#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
Timur Tabi2ad6b512006-10-31 18:44:42 -060068#define CONFIG_MPC8349 /* MPC8349 specific */
69
Wolfgang Denk2ae18242010-10-06 09:05:45 +020070#ifndef CONFIG_SYS_TEXT_BASE
71#define CONFIG_SYS_TEXT_BASE 0xFEF00000
72#endif
73
Joe Hershberger396abba2011-10-11 23:57:15 -050074#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060075
Timur Tabi89c77842008-02-08 13:15:55 -060076#define CONFIG_MISC_INIT_F
77#define CONFIG_MISC_INIT_R
Timur Tabi7a78f142007-01-31 15:54:29 -060078
Timur Tabi89c77842008-02-08 13:15:55 -060079/*
80 * On-board devices
81 */
Timur Tabi7a78f142007-01-31 15:54:29 -060082
83#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -050084/* The CF card interface on the back of the board */
85#define CONFIG_COMPACT_FLASH
Timur Tabi89c77842008-02-08 13:15:55 -060086#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +020087#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +030088#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060089#endif
90
91#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060092#define CONFIG_RTC_DS1337
Timur Tabi7a78f142007-01-31 15:54:29 -060093#define CONFIG_HARD_I2C
94#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
95
96/*
97 * Device configurations
98 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060099
100/* I2C */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600101#ifdef CONFIG_HARD_I2C
102
Timur Tabibe5e6182006-11-03 19:15:00 -0600103#define CONFIG_FSL_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600104#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_I2C_OFFSET 0x3000
106#define CONFIG_SYS_I2C2_OFFSET 0x3100
107#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200108#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
111#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
112#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
113#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
114#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger396abba2011-10-11 23:57:15 -0500115#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
116#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600117
Joe Hershberger396abba2011-10-11 23:57:15 -0500118#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
119#define CONFIG_SYS_I2C_SLAVE 0x7F
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120
121/* Don't probe these addresses: */
Joe Hershberger396abba2011-10-11 23:57:15 -0500122#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
124 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger396abba2011-10-11 23:57:15 -0500125 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600126/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger396abba2011-10-11 23:57:15 -0500127 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
128#define I2C_8574_REVISION 0x03
Timur Tabi2ad6b512006-10-31 18:44:42 -0600129#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
130#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
131#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
132#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
133
134#undef CONFIG_SOFT_I2C
135
136#endif
137
Timur Tabi7a78f142007-01-31 15:54:29 -0600138/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600139#ifdef CONFIG_COMPACT_FLASH
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_IDE_MAXBUS 1
142#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
145#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
146#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
147#define CONFIG_SYS_ATA_REG_OFFSET 0
148#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
149#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600150
Joe Hershberger396abba2011-10-11 23:57:15 -0500151/* If a CF card is not inserted, time out quickly */
152#define ATA_RESET_TIME 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600153
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200154#endif
155
156/*
157 * SATA
158 */
159#ifdef CONFIG_SATA_SIL3114
160
161#define CONFIG_SYS_SATA_MAX_DEVICE 4
162#define CONFIG_LIBATA
163#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600164
Timur Tabi7a78f142007-01-31 15:54:29 -0600165#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600166
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300167#ifdef CONFIG_SYS_USB_HOST
168/*
169 * Support USB
170 */
171#define CONFIG_CMD_USB
172#define CONFIG_USB_STORAGE
173#define CONFIG_USB_EHCI
174#define CONFIG_USB_EHCI_FSL
175
176/* Current USB implementation supports the only USB controller,
177 * so we have to choose between the MPH or the DR ones */
178#if 1
179#define CONFIG_HAS_FSL_MPH_USB
180#else
181#define CONFIG_HAS_FSL_DR_USB
182#endif
183
184#endif
185
Timur Tabi7a78f142007-01-31 15:54:29 -0600186/*
187 * DDR Setup
188 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500189#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
191#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
192#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger396abba2011-10-11 23:57:15 -0500193#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600195
Joe Hershberger396abba2011-10-11 23:57:15 -0500196#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
197 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500198
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200199#define CONFIG_VERY_BIG_RAM
200#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
201
Timur Tabi7a78f142007-01-31 15:54:29 -0600202#ifdef CONFIG_HARD_I2C
203#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
204#endif
205
Joe Hershberger396abba2011-10-11 23:57:15 -0500206/* No SPD? Then manually set up DDR parameters */
207#ifndef CONFIG_SPD_EEPROM
208 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500209 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger396abba2011-10-11 23:57:15 -0500210 | CSCONFIG_ROW_BIT_13 \
211 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
214 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600215#endif
216
217/*
218 *Flash on the Local Bus
219 */
220
Joe Hershberger396abba2011-10-11 23:57:15 -0500221#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
222#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
224#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger396abba2011-10-11 23:57:15 -0500225/* 127 64KB sectors + 8 8KB sectors per device */
226#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
229#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600230
231/* The ITX has two flash chips, but the ITX-GP has only one. To support both
232boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger396abba2011-10-11 23:57:15 -0500234#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
235#define CONFIG_SYS_FLASH_BANKS_LIST \
236 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
237#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Joe Hershberger396abba2011-10-11 23:57:15 -0500238#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi7a78f142007-01-31 15:54:29 -0600239
Timur Tabi89c77842008-02-08 13:15:55 -0600240/* Vitesse 7385 */
241
242#ifdef CONFIG_VSC7385_ENET
243
244#define CONFIG_TSEC2
245
246/* The flash address and size of the VSC7385 firmware image */
247#define CONFIG_VSC7385_IMAGE 0xFEFFE000
248#define CONFIG_VSC7385_IMAGE_SIZE 8192
249
250#endif
251
Timur Tabi7a78f142007-01-31 15:54:29 -0600252/*
253 * BRx, ORx, LBLAWBARx, and LBLAWARx
254 */
255
256/* Flash */
257
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500258#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
259 | BR_PS_16 \
260 | BR_MS_GPCM \
261 | BR_V)
262#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500263 | OR_UPM_XAM \
264 | OR_GPCM_CSNT \
265 | OR_GPCM_ACS_DIV2 \
266 | OR_GPCM_XACS \
267 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500268 | OR_GPCM_TRLX_SET \
269 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500270 | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500272#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600273
274/* Vitesse 7385 */
275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600277
Timur Tabi89c77842008-02-08 13:15:55 -0600278#ifdef CONFIG_VSC7385_ENET
279
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500280#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
281 | BR_PS_8 \
282 | BR_MS_GPCM \
283 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500284#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
285 | OR_GPCM_CSNT \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_15 \
288 | OR_GPCM_SETA \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500289 | OR_GPCM_TRLX_SET \
290 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500291 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
294#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600295
296#endif
297
298/* LED */
299
Joe Hershberger396abba2011-10-11 23:57:15 -0500300#define CONFIG_SYS_LED_BASE 0xF9000000
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500301#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
302 | BR_PS_8 \
303 | BR_MS_GPCM \
304 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500305#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
306 | OR_GPCM_CSNT \
307 | OR_GPCM_ACS_DIV2 \
308 | OR_GPCM_XACS \
309 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500310 | OR_GPCM_TRLX_SET \
311 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500312 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600313
314/* Compact Flash */
315
316#ifdef CONFIG_COMPACT_FLASH
317
Joe Hershberger396abba2011-10-11 23:57:15 -0500318#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600319
Joe Hershberger396abba2011-10-11 23:57:15 -0500320#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
321 | BR_PS_16 \
322 | BR_MS_UPMA \
323 | BR_V)
324#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi7a78f142007-01-31 15:54:29 -0600325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
327#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600328
329#endif
330
331/*
332 * U-Boot memory configuration
333 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200334#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
337#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600338#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600340#endif
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger396abba2011-10-11 23:57:15 -0500343#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
344#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600345
Joe Hershberger396abba2011-10-11 23:57:15 -0500346#define CONFIG_SYS_GBL_DATA_OFFSET \
347 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger396abba2011-10-11 23:57:15 -0500351#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
352#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600353
354/*
355 * Local Bus LCRR and LBCR regs
356 * LCRR: DLL bypass, Clock divider is 4
357 * External Local Bus rate is
358 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
359 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500360#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
361#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600363
Joe Hershberger396abba2011-10-11 23:57:15 -0500364 /* LB sdram refresh timer, about 6us */
365#define CONFIG_SYS_LBC_LSRT 0x32000000
366 /* LB refresh timer prescal, 266MHz/32*/
367#define CONFIG_SYS_LBC_MRTPR 0x20000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600368
369/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600370 * Serial Port
371 */
372#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_NS16550
374#define CONFIG_SYS_NS16550_SERIAL
375#define CONFIG_SYS_NS16550_REG_SIZE 1
376#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger396abba2011-10-11 23:57:15 -0500379 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi7a78f142007-01-31 15:54:29 -0600380
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400381#define CONFIG_CONSOLE ttyS0
Timur Tabi7a78f142007-01-31 15:54:29 -0600382#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
385#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600386
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600387/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500388#define CONFIG_OF_LIBFDT 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600389#define CONFIG_OF_BOARD_SETUP 1
390#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600391
Timur Tabi7a78f142007-01-31 15:54:29 -0600392/*
393 * PCI
394 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600395#ifdef CONFIG_PCI
396
397#define CONFIG_MPC83XX_PCI2
398
399/*
400 * General PCI
401 * Addresses are mapped 1-1.
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
404#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
405#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500406#define CONFIG_SYS_PCI1_MMIO_BASE \
407 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
409#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500410#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
411#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
412#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600413
414#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500415#define CONFIG_SYS_PCI2_MEM_BASE \
416 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
418#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500419#define CONFIG_SYS_PCI2_MMIO_BASE \
420 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
422#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500423#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
424#define CONFIG_SYS_PCI2_IO_PHYS \
425 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
426#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600427#endif
428
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100429#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600430
Timur Tabi2ad6b512006-10-31 18:44:42 -0600431#ifndef CONFIG_PCI_PNP
432 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600434 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
435#endif
436
437#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
438
439#endif
440
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200441#define CONFIG_PCI_66M
442#ifdef CONFIG_PCI_66M
Timur Tabi7a78f142007-01-31 15:54:29 -0600443#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
444#else
445#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
446#endif
447
Timur Tabi2ad6b512006-10-31 18:44:42 -0600448/* TSEC */
449
450#ifdef CONFIG_TSEC_ENET
451
Timur Tabi2ad6b512006-10-31 18:44:42 -0600452#define CONFIG_MII
Jon Loeliger659e2f62007-07-10 09:10:49 -0500453#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600454
Kim Phillips255a35772007-05-16 16:52:19 -0500455#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600456
Kim Phillips255a35772007-05-16 16:52:19 -0500457#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500458#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500459#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100461#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600462#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500463#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600464#endif
465
Kim Phillips255a35772007-05-16 16:52:19 -0500466#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600467#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500468#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600470
Timur Tabi2ad6b512006-10-31 18:44:42 -0600471#define TSEC2_PHY_ADDR 4
472#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500473#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600474#endif
475
476#define CONFIG_ETHPRIME "Freescale TSEC"
477
478#endif
479
Timur Tabi2ad6b512006-10-31 18:44:42 -0600480/*
481 * Environment
482 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600483#define CONFIG_ENV_OVERWRITE
484
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200486 #define CONFIG_ENV_IS_IN_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500487 #define CONFIG_ENV_ADDR \
488 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200489 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
Joe Hershberger396abba2011-10-11 23:57:15 -0500490 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600491#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500492 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200493 #undef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200494 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Joe Hershberger396abba2011-10-11 23:57:15 -0500495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
496 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600497#endif
498
499#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600501
Jon Loeliger8ea54992007-07-04 22:30:06 -0500502/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500503 * BOOTP options
504 */
505#define CONFIG_BOOTP_BOOTFILESIZE
506#define CONFIG_BOOTP_BOOTPATH
507#define CONFIG_BOOTP_GATEWAY
508#define CONFIG_BOOTP_HOSTNAME
509
510
511/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500512 * Command line configuration.
513 */
514#include <config_cmd_default.h>
515
516#define CONFIG_CMD_CACHE
517#define CONFIG_CMD_DATE
518#define CONFIG_CMD_IRQ
519#define CONFIG_CMD_NET
520#define CONFIG_CMD_PING
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200521#define CONFIG_CMD_DHCP
Jon Loeliger8ea54992007-07-04 22:30:06 -0500522#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600523
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300524#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500525 || defined(CONFIG_USB_STORAGE)
526 #define CONFIG_DOS_PARTITION
527 #define CONFIG_CMD_FAT
528 #define CONFIG_SUPPORT_VFAT
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200529#endif
530
Timur Tabi2ad6b512006-10-31 18:44:42 -0600531#ifdef CONFIG_COMPACT_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500532 #define CONFIG_CMD_IDE
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200533#endif
534
535#ifdef CONFIG_SATA_SIL3114
Joe Hershberger396abba2011-10-11 23:57:15 -0500536 #define CONFIG_CMD_SATA
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300537#endif
538
539#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
Joe Hershberger396abba2011-10-11 23:57:15 -0500540 #define CONFIG_CMD_EXT2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600541#endif
542
543#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500544 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600545#endif
546
547#ifdef CONFIG_HARD_I2C
Joe Hershberger396abba2011-10-11 23:57:15 -0500548 #define CONFIG_CMD_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600549#endif
550
Timur Tabi2ad6b512006-10-31 18:44:42 -0600551/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600552#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600553
554/*
555 * Miscellaneous configurable options
556 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500557#define CONFIG_SYS_LONGHELP /* undef to save memory */
558#define CONFIG_CMDLINE_EDITING /* Command-line editing */
559#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
560#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Timur Tabi7a78f142007-01-31 15:54:29 -0600562
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips05f91a62009-08-26 21:27:37 -0500564#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600565
566#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500567#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600568#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500569#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600570#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600571
Jon Loeliger8ea54992007-07-04 22:30:06 -0500572#if defined(CONFIG_CMD_KGDB)
Joe Hershberger396abba2011-10-11 23:57:15 -0500573 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600574#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500575 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600576#endif
577
Joe Hershberger396abba2011-10-11 23:57:15 -0500578 /* Print Buffer Size */
579#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
580#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
581 /* Boot Argument Buffer Size */
582#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
583#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600584
585/*
586 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700587 * have to be in the first 256 MB of memory, since this is
Timur Tabi2ad6b512006-10-31 18:44:42 -0600588 * the maximum mapped by the Linux kernel during initialization.
589 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500590 /* Initial Memory map for Linux*/
591#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600592
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600594 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
595 HRCWL_DDR_TO_SCB_CLK_1X1 |\
596 HRCWL_CSB_TO_CLKIN_4X1 |\
597 HRCWL_VCO_1X2 |\
598 HRCWL_CORE_TO_CSB_2X1)
599
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#ifdef CONFIG_SYS_LOWBOOT
601#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600602 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600603 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600604 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600605 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600606 HRCWH_CORE_ENABLE |\
607 HRCWH_FROM_0X00000100 |\
608 HRCWH_BOOTSEQ_DISABLE |\
609 HRCWH_SW_WATCHDOG_DISABLE |\
610 HRCWH_ROM_LOC_LOCAL_16BIT |\
611 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500612 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600613#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600615 HRCWH_PCI_HOST |\
616 HRCWH_32_BIT_PCI |\
617 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600618 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600619 HRCWH_CORE_ENABLE |\
620 HRCWH_FROM_0XFFF00100 |\
621 HRCWH_BOOTSEQ_DISABLE |\
622 HRCWH_SW_WATCHDOG_DISABLE |\
623 HRCWH_ROM_LOC_LOCAL_16BIT |\
624 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500625 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600626#endif
627
Timur Tabi7a78f142007-01-31 15:54:29 -0600628/*
629 * System performance
630 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger396abba2011-10-11 23:57:15 -0500632#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
634#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
635#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
636#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300637#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
638#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600639
Timur Tabi7a78f142007-01-31 15:54:29 -0600640/*
641 * System IO Config
642 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500643/* Needed for gigabit to work on TSEC 1 */
644#define CONFIG_SYS_SICRH SICRH_TSOBI1
645 /* USB DR as device + USB MPH as host */
646#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600647
Kim Phillips1a2e2032010-04-20 19:37:54 -0500648#define CONFIG_SYS_HID0_INIT 0x00000000
649#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600650
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500652#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600653
Timur Tabi7a78f142007-01-31 15:54:29 -0600654/* DDR */
Joe Hershberger396abba2011-10-11 23:57:15 -0500655#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500656 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500657 | BATL_MEMCOHERENCE)
658#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
659 | BATU_BL_256M \
660 | BATU_VS \
661 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600662
Timur Tabi7a78f142007-01-31 15:54:29 -0600663/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600664#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500665#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500666 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500667 | BATL_MEMCOHERENCE)
668#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
669 | BATU_BL_256M \
670 | BATU_VS \
671 | BATU_VP)
672#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500673 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500674 | BATL_CACHEINHIBIT \
675 | BATL_GUARDEDSTORAGE)
676#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
677 | BATU_BL_256M \
678 | BATU_VS \
679 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600680#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681#define CONFIG_SYS_IBAT1L 0
682#define CONFIG_SYS_IBAT1U 0
683#define CONFIG_SYS_IBAT2L 0
684#define CONFIG_SYS_IBAT2U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600685#endif
686
687#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500688#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500689 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500690 | BATL_MEMCOHERENCE)
691#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
692 | BATU_BL_256M \
693 | BATU_VS \
694 | BATU_VP)
695#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500696 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500697 | BATL_CACHEINHIBIT \
698 | BATL_GUARDEDSTORAGE)
699#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
700 | BATU_BL_256M \
701 | BATU_VS \
702 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600703#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200704#define CONFIG_SYS_IBAT3L 0
705#define CONFIG_SYS_IBAT3U 0
706#define CONFIG_SYS_IBAT4L 0
707#define CONFIG_SYS_IBAT4U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600708#endif
709
710/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500711#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500712 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500713 | BATL_CACHEINHIBIT \
714 | BATL_GUARDEDSTORAGE)
715#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
716 | BATU_BL_256M \
717 | BATU_VS \
718 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600719
720/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500721#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500722 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500723 | BATL_MEMCOHERENCE \
724 | BATL_GUARDEDSTORAGE)
725#define CONFIG_SYS_IBAT6U (0xF0000000 \
726 | BATU_BL_256M \
727 | BATU_VS \
728 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600729
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200730#define CONFIG_SYS_IBAT7L 0
731#define CONFIG_SYS_IBAT7U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600732
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200733#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
734#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
735#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
736#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
737#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
738#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
739#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
740#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
741#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
742#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
743#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
744#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
745#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
746#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
747#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
748#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi2ad6b512006-10-31 18:44:42 -0600749
Jon Loeliger8ea54992007-07-04 22:30:06 -0500750#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600751#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
752#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
753#endif
754
755
756/*
757 * Environment Configuration
758 */
759#define CONFIG_ENV_OVERWRITE
760
Joe Hershberger396abba2011-10-11 23:57:15 -0500761#define CONFIG_NETDEV "eth0"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600762
Timur Tabi7a78f142007-01-31 15:54:29 -0600763#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500764#define CONFIG_HOSTNAME "mpc8349emitx"
Timur Tabi7a78f142007-01-31 15:54:29 -0600765#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500766#define CONFIG_HOSTNAME "mpc8349emitxgp"
Timur Tabi7a78f142007-01-31 15:54:29 -0600767#endif
768
769/* Default path and filenames */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000770#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000771#define CONFIG_BOOTFILE "uImage"
Joe Hershberger396abba2011-10-11 23:57:15 -0500772 /* U-Boot image on TFTP server */
773#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600774
Timur Tabi7a78f142007-01-31 15:54:29 -0600775#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500776#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600777#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500778#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600779#endif
780
Kim Phillips05f91a62009-08-26 21:27:37 -0500781#define CONFIG_BOOTDELAY 6
Timur Tabi7a78f142007-01-31 15:54:29 -0600782
Timur Tabi2ad6b512006-10-31 18:44:42 -0600783#define XMK_STR(x) #x
784#define MK_STR(x) XMK_STR(x)
785
Timur Tabi98883332006-10-31 19:14:41 -0600786#define CONFIG_BOOTARGS \
787 "root=/dev/nfs rw" \
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000788 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200789 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500790 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
791 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400792 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
Timur Tabi98883332006-10-31 19:14:41 -0600793
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100794#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200795 "console=" MK_STR(CONFIG_CONSOLE) "\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500796 "netdev=" CONFIG_NETDEV "\0" \
797 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200798 "tftpflash=tftpboot $loadaddr $uboot; " \
Joe Hershberger396abba2011-10-11 23:57:15 -0500799 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
800 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
801 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
802 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
803 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
Kim Phillips05f91a62009-08-26 21:27:37 -0500804 "fdtaddr=780000\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500805 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600806
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100807#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600808 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500809 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi7a78f142007-01-31 15:54:29 -0600810 " console=$console,$baudrate $othbootargs; " \
811 "tftp $loadaddr $bootfile;" \
812 "tftp $fdtaddr $fdtfile;" \
813 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600814
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100815#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600816 "setenv bootargs root=/dev/ram rw" \
817 " console=$console,$baudrate $othbootargs; " \
818 "tftp $ramdiskaddr $ramdiskfile;" \
819 "tftp $loadaddr $bootfile;" \
820 "tftp $fdtaddr $fdtfile;" \
821 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600822
823#undef MK_STR
824#undef XMK_STR
825
826#endif