blob: 6d45bb1e8d8ef2460694c192484e91e513a9a584 [file] [log] [blame]
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * P2041 RDB board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#define CONFIG_P2041RDB
31#define CONFIG_PHYS_64BIT
32#define CONFIG_PPC_P2041
33
34#ifdef CONFIG_RAMBOOT_PBL
35#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
37#endif
38
39/* High Level Configuration Options */
40#define CONFIG_BOOKE
41#define CONFIG_E500 /* BOOKE e500 family */
42#define CONFIG_E500MC /* BOOKE e500mc family */
43#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
45#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
46#define CONFIG_MP /* support multiple processors */
47
48#ifndef CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_TEXT_BASE 0xeff80000
50#endif
51
52#ifndef CONFIG_RESET_VECTOR_ADDRESS
53#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
54#endif
55
56#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
58#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
59#define CONFIG_PCI /* Enable PCI/PCIE */
60#define CONFIG_PCIE1 /* PCIE controler 1 */
61#define CONFIG_PCIE2 /* PCIE controler 2 */
62#define CONFIG_PCIE3 /* PCIE controler 3 */
63#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
65
66#define CONFIG_SYS_SRIO
67#define CONFIG_SRIO1 /* SRIO port 1 */
68#define CONFIG_SRIO2 /* SRIO port 2 */
Kumar Gala4d28db82011-10-14 13:28:52 -050069#define CONFIG_SYS_DPAA_RMAN /* RMan */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080070
71#define CONFIG_FSL_LAW /* Use common FSL init code */
72
73#define CONFIG_ENV_OVERWRITE
74
75#ifdef CONFIG_SYS_NO_FLASH
76#define CONFIG_ENV_IS_NOWHERE
77#else
78#define CONFIG_FLASH_CFI_DRIVER
79#define CONFIG_SYS_FLASH_CFI
80#endif
81
82#if defined(CONFIG_SPIFLASH)
83 #define CONFIG_SYS_EXTRA_ENV_RELOC
84 #define CONFIG_ENV_IS_IN_SPI_FLASH
85 #define CONFIG_ENV_SPI_BUS 0
86 #define CONFIG_ENV_SPI_CS 0
87 #define CONFIG_ENV_SPI_MAX_HZ 10000000
88 #define CONFIG_ENV_SPI_MODE 0
89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
91 #define CONFIG_ENV_SECT_SIZE 0x10000
92#elif defined(CONFIG_SDCARD)
93 #define CONFIG_SYS_EXTRA_ENV_RELOC
94 #define CONFIG_ENV_IS_IN_MMC
95 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (512 * 1097)
98#else
99 #define CONFIG_ENV_IS_IN_FLASH
100 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
101 - CONFIG_ENV_SECT_SIZE)
102 #define CONFIG_ENV_SIZE 0x2000
103 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
104#endif
105
Shaohui Xie44d50f02011-09-13 17:55:11 +0800106#ifndef __ASSEMBLY__
107unsigned long get_board_sys_clk(unsigned long dummy);
108#endif
109#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800110
111/*
112 * These can be toggled for performance analysis, otherwise use default.
113 */
114#define CONFIG_SYS_CACHE_STASHING
Mingkai Hucd420e02011-07-21 17:03:54 -0500115#define CONFIG_BACKSIDE_L2_CACHE
116#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800117#define CONFIG_BTB /* toggle branch predition */
118
119#define CONFIG_ENABLE_36BIT_PHYS
120
121#ifdef CONFIG_PHYS_64BIT
122#define CONFIG_ADDR_MAP
123#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
124#endif
125
126#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
127#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
128#define CONFIG_SYS_MEMTEST_END 0x00400000
129#define CONFIG_SYS_ALT_MEMTEST
130#define CONFIG_PANIC_HANG /* do not reset board on panic */
131
132/*
133 * Config the L3 Cache as L3 SRAM
134 */
135#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
136#ifdef CONFIG_PHYS_64BIT
137#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
138 CONFIG_RAMBOOT_TEXT_BASE)
139#else
140#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
141#endif
142#define CONFIG_SYS_L3_SIZE (1024 << 10)
143#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
144
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800145#ifdef CONFIG_PHYS_64BIT
146#define CONFIG_SYS_DCSRBAR 0xf0000000
147#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
148#endif
149
150/* EEPROM */
151#define CONFIG_ID_EEPROM
152#define CONFIG_SYS_I2C_EEPROM_NXID
153#define CONFIG_SYS_EEPROM_BUS_NUM 0
154#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
155#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
156
157/*
158 * DDR Setup
159 */
160#define CONFIG_VERY_BIG_RAM
161#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
163
164#define CONFIG_DIMM_SLOTS_PER_CTLR 1
165#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
166
167#define CONFIG_DDR_SPD
168#define CONFIG_FSL_DDR3
169
170#define CONFIG_SYS_SPD_BUS_NUM 0
171#define SPD_EEPROM_ADDRESS 0x52
172#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
173
174/*
175 * Local Bus Definitions
176 */
177
178/* Set the local bus clock 1/8 of platform clock */
179#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
180
181#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
182#ifdef CONFIG_PHYS_64BIT
183#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
184#else
185#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
186#endif
187
188#define CONFIG_SYS_BR0_PRELIM \
189 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
190#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
191 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
192
193#define CONFIG_FSL_CPLD
194#define CPLD_BASE 0xffdf0000 /* CPLD registers */
195#ifdef CONFIG_PHYS_64BIT
196#define CPLD_BASE_PHYS 0xfffdf0000ull
197#else
198#define CPLD_BASE_PHYS CPLD_BASE
199#endif
200
201#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
202#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
203
204#define PIXIS_LBMAP_SWITCH 7
205#define PIXIS_LBMAP_MASK 0xf0
206#define PIXIS_LBMAP_SHIFT 4
207#define PIXIS_LBMAP_ALTBANK 0x40
208
209#define CONFIG_SYS_FLASH_QUIET_TEST
210#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
211
212#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
213#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
214#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
215#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
216
217#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
218
219#if defined(CONFIG_RAMBOOT_PBL)
220#define CONFIG_SYS_RAMBOOT
221#endif
222
223#define CONFIG_SYS_FLASH_EMPTY_INFO
224#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
225#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
226
227#define CONFIG_BOARD_EARLY_INIT_F
228#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
229#define CONFIG_MISC_INIT_R
230
231#define CONFIG_HWCONFIG
232
233/* define to use L1 as initial stack */
234#define CONFIG_L1_INIT_RAM
235#define CONFIG_SYS_INIT_RAM_LOCK
236#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
237#ifdef CONFIG_PHYS_64BIT
238#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
239#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
240/* The assembler doesn't like typecast */
241#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
242 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
243 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
244#else
245#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
246#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
247#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
248#endif
249#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
250
251#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
252 GENERATED_GBL_DATA_SIZE)
253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
254
255#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
256#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
257
258/* Serial Port - controlled on board with jumper J8
259 * open - index 2
260 * shorted - index 1
261 */
262#define CONFIG_CONS_INDEX 1
263#define CONFIG_SYS_NS16550
264#define CONFIG_SYS_NS16550_SERIAL
265#define CONFIG_SYS_NS16550_REG_SIZE 1
266#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
267
268#define CONFIG_SYS_BAUDRATE_TABLE \
269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
270
271#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
272#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
273#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
274#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
275
276/* Use the HUSH parser */
277#define CONFIG_SYS_HUSH_PARSER
278#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
279
280/* pass open firmware flat tree */
281#define CONFIG_OF_LIBFDT
282#define CONFIG_OF_BOARD_SETUP
283#define CONFIG_OF_STDOUT_VIA_ALIAS
284
285/* new uImage format support */
286#define CONFIG_FIT
287#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
288
289/* I2C */
290#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
291#define CONFIG_HARD_I2C /* I2C with hardware support */
292#define CONFIG_I2C_MULTI_BUS
293#define CONFIG_I2C_CMD_TREE
294#define CONFIG_SYS_I2C_SPEED 400000
295#define CONFIG_SYS_I2C_SLAVE 0x7F
296#define CONFIG_SYS_I2C_OFFSET 0x118000
297#define CONFIG_SYS_I2C2_OFFSET 0x118100
298
299/*
300 * RapidIO
301 */
302#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
303#ifdef CONFIG_PHYS_64BIT
304#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
305#else
306#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
307#endif
308#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
309
310#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
311#ifdef CONFIG_PHYS_64BIT
312#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
313#else
314#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
315#endif
316#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
317
318/*
319 * eSPI - Enhanced SPI
320 */
321#define CONFIG_FSL_ESPI
322#define CONFIG_SPI_FLASH
323#define CONFIG_SPI_FLASH_SPANSION
324#define CONFIG_CMD_SF
325#define CONFIG_SF_DEFAULT_SPEED 10000000
326#define CONFIG_SF_DEFAULT_MODE 0
327
328/*
329 * General PCI
330 * Memory space is mapped 1-1, but I/O space must start from 0.
331 */
332
333/* controller 1, direct to uli, tgtid 3, Base address 20000 */
334#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
335#ifdef CONFIG_PHYS_64BIT
336#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
337#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
338#else
339#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
340#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
341#endif
342#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
343#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
344#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
345#ifdef CONFIG_PHYS_64BIT
346#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
347#else
348#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
349#endif
350#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
351
352/* controller 2, Slot 2, tgtid 2, Base address 201000 */
353#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
354#ifdef CONFIG_PHYS_64BIT
355#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
356#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
357#else
358#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
359#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
360#endif
361#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
362#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
363#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
364#ifdef CONFIG_PHYS_64BIT
365#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
366#else
367#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
368#endif
369#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
370
371/* controller 3, Slot 1, tgtid 1, Base address 202000 */
372#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
373#ifdef CONFIG_PHYS_64BIT
374#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
375#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
376#else
377#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
378#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
379#endif
380#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
381#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
382#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
383#ifdef CONFIG_PHYS_64BIT
384#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
385#else
386#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
387#endif
388#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
389
390/* Qman/Bman */
391#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
392#define CONFIG_SYS_BMAN_NUM_PORTALS 10
393#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
394#ifdef CONFIG_PHYS_64BIT
395#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
396#else
397#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
398#endif
399#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
400#define CONFIG_SYS_QMAN_NUM_PORTALS 10
401#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
402#ifdef CONFIG_PHYS_64BIT
403#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
404#else
405#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
406#endif
407#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
408
409#define CONFIG_SYS_DPAA_FMAN
410#define CONFIG_SYS_DPAA_PME
411/* Default address of microcode for the Linux Fman driver */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800412#if defined(CONFIG_SPIFLASH)
413/*
414 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
415 * env, so we got 0x110000.
416 */
417#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
418#elif defined(CONFIG_SDCARD)
419/*
420 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
421 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
422 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
423 */
424#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
425#elif defined(CONFIG_NAND)
426#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
427#else
428#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
429#endif
430#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
431#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
432
433#ifdef CONFIG_SYS_DPAA_FMAN
434#define CONFIG_FMAN_ENET
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800435#define CONFIG_PHYLIB_10G
436#define CONFIG_PHY_VITESSE
437#define CONFIG_PHY_TERANETICS
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800438#endif
439
440#ifdef CONFIG_PCI
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800441#define CONFIG_PCI_PNP /* do pci plug-and-play */
442#define CONFIG_E1000
443
444#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
445#define CONFIG_DOS_PARTITION
446#endif /* CONFIG_PCI */
447
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800448/* SATA */
449#define CONFIG_FSL_SATA_V2
450#ifdef CONFIG_FSL_SATA_V2
451#define CONFIG_LIBATA
452#define CONFIG_FSL_SATA
453
454#define CONFIG_SYS_SATA_MAX_DEVICE 2
455#define CONFIG_SATA1
456#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
457#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
458#define CONFIG_SATA2
459#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
460#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
461
462#define CONFIG_LBA48
463#define CONFIG_CMD_SATA
464#define CONFIG_DOS_PARTITION
465#define CONFIG_CMD_EXT2
466#endif
467
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800468#ifdef CONFIG_FMAN_ENET
469#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
470#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
471#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
472#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
473#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
474
475#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
476#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
477#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
478#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
479
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800480#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
481
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800482#define CONFIG_SYS_TBIPA_VALUE 8
483#define CONFIG_MII /* MII PHY management */
484#define CONFIG_ETHPRIME "FM1@DTSEC1"
485#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
486#endif
487
488/*
489 * Environment
490 */
491#define CONFIG_LOADS_ECHO /* echo on for serial download */
492#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
493
494/*
495 * Command line configuration.
496 */
497#include <config_cmd_default.h>
498
499#define CONFIG_CMD_DHCP
500#define CONFIG_CMD_ELF
501#define CONFIG_CMD_ERRATA
502#define CONFIG_CMD_GREPENV
503#define CONFIG_CMD_IRQ
504#define CONFIG_CMD_I2C
505#define CONFIG_CMD_MII
506#define CONFIG_CMD_PING
507#define CONFIG_CMD_SETEXPR
508
509#ifdef CONFIG_PCI
510#define CONFIG_CMD_PCI
511#define CONFIG_CMD_NET
512#endif
513
514/*
515* USB
516*/
517#define CONFIG_CMD_USB
518#define CONFIG_USB_STORAGE
519#define CONFIG_USB_EHCI
520#define CONFIG_USB_EHCI_FSL
521#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
522#define CONFIG_CMD_EXT2
523
524#define CONFIG_MMC
525
526#ifdef CONFIG_MMC
527#define CONFIG_FSL_ESDHC
528#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
529#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
530#define CONFIG_CMD_MMC
531#define CONFIG_GENERIC_MMC
532#define CONFIG_CMD_EXT2
533#define CONFIG_CMD_FAT
534#define CONFIG_DOS_PARTITION
535#endif
536
537/*
538 * Miscellaneous configurable options
539 */
540#define CONFIG_SYS_LONGHELP /* undef to save memory */
541#define CONFIG_CMDLINE_EDITING /* Command-line editing */
542#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
543#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
544#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
545#ifdef CONFIG_CMD_KGDB
546#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
547#else
548#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
549#endif
550/* Print Buffer Size */
551#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
552 sizeof(CONFIG_SYS_PROMPT)+16)
553#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
554/* Boot Argument Buffer Size */
555#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
556#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
557
558/*
559 * For booting Linux, the board info and command line data
560 * have to be in the first 64 MB of memory, since this is
561 * the maximum mapped by the Linux kernel during initialization.
562 */
563#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
564#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
565
566#ifdef CONFIG_CMD_KGDB
567#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
568#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
569#endif
570
571/*
572 * Environment Configuration
573 */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000574#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000575#define CONFIG_BOOTFILE "uImage"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800576#define CONFIG_UBOOTPATH u-boot.bin
577
578/* default location for tftp and bootm */
579#define CONFIG_LOADADDR 1000000
580
581#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
582
583#define CONFIG_BAUDRATE 115200
584
585#define __USB_PHY_TYPE utmi
586
587#define CONFIG_EXTRA_ENV_SETTINGS \
588 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
589 "bank_intlv=cs0_cs1\0" \
590 "netdev=eth0\0" \
591 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
592 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
593 "tftpflash=tftpboot $loadaddr $uboot && " \
594 "protect off $ubootaddr +$filesize && " \
595 "erase $ubootaddr +$filesize && " \
596 "cp.b $loadaddr $ubootaddr $filesize && " \
597 "protect on $ubootaddr +$filesize && " \
598 "cmp.b $loadaddr $ubootaddr $filesize\0" \
599 "consoledev=ttyS0\0" \
600 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
601 "usb_dr_mode=host\0" \
602 "ramdiskaddr=2000000\0" \
603 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
604 "fdtaddr=c00000\0" \
605 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
606 "bdev=sda3\0" \
607 "c=ffe\0"
608
609#define CONFIG_HDBOOT \
610 "setenv bootargs root=/dev/$bdev rw " \
611 "console=$consoledev,$baudrate $othbootargs;" \
612 "tftp $loadaddr $bootfile;" \
613 "tftp $fdtaddr $fdtfile;" \
614 "bootm $loadaddr - $fdtaddr"
615
616#define CONFIG_NFSBOOTCOMMAND \
617 "setenv bootargs root=/dev/nfs rw " \
618 "nfsroot=$serverip:$rootpath " \
619 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
620 "console=$consoledev,$baudrate $othbootargs;" \
621 "tftp $loadaddr $bootfile;" \
622 "tftp $fdtaddr $fdtfile;" \
623 "bootm $loadaddr - $fdtaddr"
624
625#define CONFIG_RAMBOOTCOMMAND \
626 "setenv bootargs root=/dev/ram rw " \
627 "console=$consoledev,$baudrate $othbootargs;" \
628 "tftp $ramdiskaddr $ramdiskfile;" \
629 "tftp $loadaddr $bootfile;" \
630 "tftp $fdtaddr $fdtfile;" \
631 "bootm $loadaddr $ramdiskaddr $fdtaddr"
632
633#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
634
635#ifdef CONFIG_SECURE_BOOT
636#include <asm/fsl_secure_boot.h>
637#endif
638
639#endif /* __CONFIG_H */