| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | |
| 2 | /******************************************************************************/ |
| 3 | /* */ |
| 4 | /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ |
| 5 | /* Corporation. */ |
| 6 | /* All rights reserved. */ |
| 7 | /* */ |
| 8 | /* This program is free software; you can redistribute it and/or modify */ |
| 9 | /* it under the terms of the GNU General Public License as published by */ |
| 10 | /* the Free Software Foundation, located in the file LICENSE. */ |
| 11 | /* */ |
| 12 | /* History: */ |
| 13 | /* */ |
| 14 | /******************************************************************************/ |
| 15 | |
| 16 | #ifndef TIGON3_H |
| 17 | #define TIGON3_H |
| 18 | |
| 19 | #include "bcm570x_lm.h" |
| 20 | #if INCLUDE_TBI_SUPPORT |
| 21 | #include "bcm570x_autoneg.h" |
| 22 | #endif |
| 23 | |
| 24 | |
| 25 | /* io defines */ |
| 26 | #if !defined(BIG_ENDIAN_HOST) |
| 27 | #define readl(addr) \ |
| 28 | (LONGSWAP((*(volatile unsigned int *)(addr)))) |
| 29 | #define writel(b,addr) \ |
| 30 | ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) |
| 31 | #else |
| 32 | #if 0 /* !defined(PPC603) */ |
| 33 | #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) |
| 34 | #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) |
| 35 | #else |
| 36 | #if 1 |
| 37 | #define readl(addr) (*(volatile unsigned int*)(addr)) |
| 38 | #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) |
| 39 | #else |
| 40 | extern int sprintf(char* buf, const char* f, ...); |
| 41 | static __inline unsigned int readl(void* addr){ |
| 42 | char buf[128]; |
| 43 | unsigned int tmp = (*(volatile unsigned int*)(addr)); |
| 44 | sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0); |
| 45 | sysSerialPrintString(buf); |
| 46 | return tmp; |
| 47 | } |
| 48 | static __inline void writel(unsigned int b, unsigned int addr){ |
| 49 | char buf[128]; |
| 50 | ((*(volatile unsigned int *) (addr)) = (b)); |
| 51 | sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0); |
| 52 | sysSerialPrintString(buf); |
| 53 | } |
| 54 | #endif |
| 55 | #endif /* PPC603 */ |
| 56 | #endif |
| 57 | |
| 58 | |
| 59 | |
| 60 | |
| 61 | /******************************************************************************/ |
| 62 | /* Constants. */ |
| 63 | /******************************************************************************/ |
| 64 | |
| 65 | /* Maxim number of packet descriptors used for sending packets. */ |
| 66 | #define MAX_TX_PACKET_DESC_COUNT 600 |
| 67 | #define DEFAULT_TX_PACKET_DESC_COUNT 2 |
| 68 | |
| 69 | /* Maximum number of packet descriptors used for receiving packets. */ |
| 70 | #if T3_JUMBO_RCB_ENTRY_COUNT |
| 71 | #define MAX_RX_PACKET_DESC_COUNT \ |
| 72 | (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) |
| 73 | #else |
| 74 | #define MAX_RX_PACKET_DESC_COUNT 800 |
| 75 | #endif |
| 76 | #define DEFAULT_RX_PACKET_DESC_COUNT 2 |
| 77 | |
| 78 | /* Threshhold for double copying small tx packets. 0 will disable double */ |
| 79 | /* copying of small Tx packets. */ |
| 80 | #define DEFAULT_TX_COPY_BUFFER_SIZE 0 |
| 81 | #define MIN_TX_COPY_BUFFER_SIZE 64 |
| 82 | #define MAX_TX_COPY_BUFFER_SIZE 512 |
| 83 | |
| 84 | /* Cache line. */ |
| 85 | #define COMMON_CACHE_LINE_SIZE 0x20 |
| 86 | #define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) |
| 87 | |
| 88 | /* Maximum number of fragment we can handle. */ |
| 89 | #ifndef MAX_FRAGMENT_COUNT |
| 90 | #define MAX_FRAGMENT_COUNT 32 |
| 91 | #endif |
| 92 | |
| 93 | /* B0 bug. */ |
| 94 | #define BCM5700_BX_MIN_FRAG_SIZE 10 |
| 95 | #define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ |
| 96 | #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) |
| 97 | #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ |
| 98 | MAX_FRAGMENT_COUNT) |
| 99 | |
| 100 | /* MAGIC number. */ |
| 101 | /* #define T3_MAGIC_NUM 'KevT' */ |
| 102 | #define T3_FIRMWARE_MAILBOX 0x0b50 |
| 103 | #define T3_MAGIC_NUM 0x4B657654 |
| 104 | #define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b |
| 105 | |
| 106 | #define T3_NIC_DATA_SIG_ADDR 0x0b54 |
| 107 | #define T3_NIC_DATA_SIG 0x4b657654 |
| 108 | |
| 109 | #define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 |
| 110 | #define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE |
| 111 | #define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2 |
| 112 | #define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3 |
| 113 | #define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2 |
| 114 | #define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3 |
| 115 | #define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) |
| 116 | #define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE |
| 117 | #define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 |
| 118 | #define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 |
| 119 | #define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) |
| 120 | #define T3_NIC_CFG_ENABLE_WOL BIT_6 |
| 121 | #define T3_NIC_CFG_ENABLE_ASF BIT_7 |
| 122 | #define T3_NIC_EEPROM_WP BIT_8 |
| 123 | |
| 124 | #define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 |
| 125 | #define T3_NIC_PHY_ID1_MASK 0xffff0000 |
| 126 | #define T3_NIC_PHY_ID2_MASK 0x0000ffff |
| 127 | |
| 128 | #define T3_CMD_MAILBOX 0x0b78 |
| 129 | #define T3_CMD_NICDRV_ALIVE 0x01 |
| 130 | #define T3_CMD_NICDRV_PAUSE_FW 0x02 |
| 131 | #define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 |
| 132 | #define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 |
| 133 | #define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 |
| 134 | #define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 |
| 135 | |
| 136 | #define T3_CMD_LENGTH_MAILBOX 0x0b7c |
| 137 | #define T3_CMD_DATA_MAILBOX 0x0b80 |
| 138 | |
| 139 | #define T3_ASF_FW_STATUS_MAILBOX 0x0c00 |
| 140 | |
| 141 | #define T3_DRV_STATE_MAILBOX 0x0c04 |
| 142 | #define T3_DRV_STATE_START 0x01 |
| 143 | #define T3_DRV_STATE_UNLOAD 0x02 |
| 144 | #define T3_DRV_STATE_WOL 0x03 |
| 145 | #define T3_DRV_STATE_SUSPEND 0x04 |
| 146 | |
| 147 | #define T3_FW_RESET_TYPE_MAILBOX 0x0c08 |
| 148 | |
| 149 | #define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 |
| 150 | #define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 |
| 151 | |
| 152 | /******************************************************************************/ |
| 153 | /* Hardware constants. */ |
| 154 | /******************************************************************************/ |
| 155 | |
| 156 | /* Number of entries in the send ring: must be 512. */ |
| 157 | #define T3_SEND_RCB_ENTRY_COUNT 512 |
| 158 | #define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) |
| 159 | |
| 160 | /* Number of send RCBs. May be 1-16 but for now, only support one. */ |
| 161 | #define T3_MAX_SEND_RCB_COUNT 16 |
| 162 | |
| 163 | /* Number of entries in the Standard Receive RCB. Must be 512 entries. */ |
| 164 | #define T3_STD_RCV_RCB_ENTRY_COUNT 512 |
| 165 | #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) |
| 166 | #define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ |
| 167 | #define MAX_STD_RCV_BUFFER_SIZE 0x600 |
| 168 | |
| 169 | /* Number of entries in the Mini Receive RCB. This value can either be */ |
| 170 | /* 0, 1024. Currently Mini Receive RCB is disabled. */ |
| 171 | #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT |
| 172 | #define T3_MINI_RCV_RCB_ENTRY_COUNT 0 |
| 173 | #endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ |
| 174 | #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) |
| 175 | #define MAX_MINI_RCV_BUFFER_SIZE 512 |
| 176 | #define DEFAULT_MINI_RCV_BUFFER_SIZE 64 |
| 177 | #define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ |
| 178 | |
| 179 | /* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ |
| 180 | /* Currently, Jumbo Receive RCB is disabled. */ |
| 181 | #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT |
| 182 | #define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 |
| 183 | #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ |
| 184 | #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) |
| 185 | |
| 186 | #define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ |
| 187 | #define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ |
| 188 | #define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ |
| 189 | |
| 190 | #define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ |
| 191 | #define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ |
| 192 | |
| 193 | /* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ |
| 194 | #define T3_MAX_RCV_RETURN_RCB_COUNT 16 |
| 195 | |
| 196 | /* Number of entries in a Receive Return ring. This value is either 1024 */ |
| 197 | /* or 2048. */ |
| 198 | #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT |
| 199 | #define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 |
| 200 | #endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ |
| 201 | #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) |
| 202 | |
| 203 | |
| 204 | /* Default coalescing parameters. */ |
| 205 | #define DEFAULT_RX_COALESCING_TICKS 100 |
| 206 | #define MAX_RX_COALESCING_TICKS 500 |
| 207 | #define DEFAULT_TX_COALESCING_TICKS 400 |
| 208 | #define MAX_TX_COALESCING_TICKS 500 |
| 209 | #define DEFAULT_RX_MAX_COALESCED_FRAMES 10 |
| 210 | #define MAX_RX_MAX_COALESCED_FRAMES 100 |
| 211 | #define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 |
| 212 | #define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42 |
| 213 | #define ADAPTIVE_LO_RX_COALESCING_TICKS 50 |
| 214 | #define ADAPTIVE_HI_RX_COALESCING_TICKS 300 |
| 215 | #define ADAPTIVE_LO_PKT_THRESH 30000 |
| 216 | #define ADAPTIVE_HI_PKT_THRESH 74000 |
| 217 | #define DEFAULT_TX_MAX_COALESCED_FRAMES 40 |
| 218 | #define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25 |
| 219 | #define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 |
| 220 | #define MAX_TX_MAX_COALESCED_FRAMES 100 |
| 221 | |
| 222 | #define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 |
| 223 | #define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 |
| 224 | #define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5 |
| 225 | #define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 |
| 226 | |
| 227 | #define BAD_DEFAULT_VALUE 0xffffffff |
| 228 | |
| 229 | #define DEFAULT_STATS_COALESCING_TICKS 1000000 |
| 230 | #define MAX_STATS_COALESCING_TICKS 3600000000U |
| 231 | |
| 232 | |
| 233 | /* Receive BD Replenish thresholds. */ |
| 234 | #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 |
| 235 | #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 |
| 236 | |
| 237 | #define SPLIT_MODE_DISABLE 0 |
| 238 | #define SPLIT_MODE_ENABLE 1 |
| 239 | |
| 240 | #define SPLIT_MODE_5704_MAX_REQ 3 |
| 241 | |
| 242 | /* Maximum physical fragment size. */ |
| 243 | #define MAX_FRAGMENT_SIZE (64 * 1024) |
| 244 | |
| 245 | |
| 246 | /* Standard view. */ |
| 247 | #define T3_STD_VIEW_SIZE (64 * 1024) |
| 248 | #define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) |
| 249 | |
| 250 | |
| 251 | /* Buffer descriptor base address on the NIC's memory. */ |
| 252 | |
| 253 | #define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 |
| 254 | #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 |
| 255 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 |
| 256 | |
| 257 | #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 |
| 258 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 |
| 259 | #define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 |
| 260 | |
| 261 | #define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ |
| 262 | sizeof(T3_SND_BD) / 4) |
| 263 | |
| 264 | #define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ |
| 265 | sizeof(T3_RCV_BD) / 4) |
| 266 | |
| 267 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ |
| 268 | sizeof(T3_EXT_RCV_BD) / 4) |
| 269 | |
| 270 | |
| 271 | /* MBUF pool. */ |
| 272 | #define T3_NIC_MBUF_POOL_ADDR 0x8000 |
| 273 | /* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ |
| 274 | #define T3_NIC_MBUF_POOL_SIZE96 0x18000 |
| 275 | #define T3_NIC_MBUF_POOL_SIZE64 0x10000 |
| 276 | |
| 277 | |
| 278 | #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 |
| 279 | |
| 280 | /* DMA descriptor pool */ |
| 281 | #define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 |
| 282 | #define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ |
| 283 | |
| 284 | #define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 |
| 285 | #define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 |
| 286 | #define T3_DEF_MBUF_HIGH_WMARK 0x60 |
| 287 | |
| 288 | #define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 |
| 289 | #define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 |
| 290 | #define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 |
| 291 | |
| 292 | #define T3_DEF_DMA_DESC_LOW_WMARK 5 |
| 293 | #define T3_DEF_DMA_DESC_HIGH_WMARK 10 |
| 294 | |
| 295 | /* Maximum size of giant TCP packet can be sent */ |
| 296 | #define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 |
| 297 | #define T3_TCP_SEG_MIN_NUM_SEG 20 |
| 298 | |
| 299 | #define T3_RX_CPU_ID 0x1 |
| 300 | #define T3_TX_CPU_ID 0x2 |
| 301 | #define T3_RX_CPU_SPAD_ADDR 0x30000 |
| 302 | #define T3_RX_CPU_SPAD_SIZE 0x4000 |
| 303 | #define T3_TX_CPU_SPAD_ADDR 0x34000 |
| 304 | #define T3_TX_CPU_SPAD_SIZE 0x4000 |
| 305 | |
| 306 | typedef struct T3_DIR_ENTRY |
| 307 | { |
| 308 | PLM_UINT8 Buffer; |
| 309 | LM_UINT32 Offset; |
| 310 | LM_UINT32 Length; |
| 311 | } T3_DIR_ENTRY,*PT3_DIR_ENTRY; |
| 312 | |
| 313 | typedef struct T3_FWIMG_INFO |
| 314 | { |
| 315 | LM_UINT32 StartAddress; |
| 316 | T3_DIR_ENTRY Text; |
| 317 | T3_DIR_ENTRY ROnlyData; |
| 318 | T3_DIR_ENTRY Data; |
| 319 | T3_DIR_ENTRY Sbss; |
| 320 | T3_DIR_ENTRY Bss; |
| 321 | } T3_FWIMG_INFO, *PT3_FWIMG_INFO; |
| 322 | |
| 323 | |
| 324 | |
| 325 | /******************************************************************************/ |
| 326 | /* Tigon3 PCI Registers. */ |
| 327 | /******************************************************************************/ |
| 328 | #define T3_PCI_ID_BCM5700 0x164414e4 |
| 329 | #define T3_PCI_ID_BCM5701 0x164514e4 |
| 330 | #define T3_PCI_ID_BCM5702 0x164614e4 |
| 331 | #define T3_PCI_ID_BCM5702x 0x16A614e4 |
| 332 | #define T3_PCI_ID_BCM5703 0x164714e4 |
| 333 | #define T3_PCI_ID_BCM5703x 0x16A714e4 |
| 334 | #define T3_PCI_ID_BCM5702FE 0x164D14e4 |
| 335 | #define T3_PCI_ID_BCM5704 0x164814e4 |
| 336 | |
| 337 | #define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff) |
| 338 | #define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16) |
| 339 | |
| 340 | #define T3_PCI_MISC_HOST_CTRL_REG 0x68 |
| 341 | |
| 342 | /* The most significant 16bit of register 0x68. */ |
| 343 | /* ChipId:4, ChipRev:4, MetalRev:8 */ |
| 344 | #define T3_CHIP_ID_5700_A0 0x7000 |
| 345 | #define T3_CHIP_ID_5700_A1 0x7001 |
| 346 | #define T3_CHIP_ID_5700_B0 0x7100 |
| 347 | #define T3_CHIP_ID_5700_B1 0x7101 |
| 348 | #define T3_CHIP_ID_5700_C0 0x7200 |
| 349 | |
| 350 | #define T3_CHIP_ID_5701_A0 0x0000 |
| 351 | #define T3_CHIP_ID_5701_B0 0x0100 |
| 352 | #define T3_CHIP_ID_5701_B2 0x0102 |
| 353 | #define T3_CHIP_ID_5701_B5 0x0105 |
| 354 | |
| 355 | #define T3_CHIP_ID_5703_A0 0x1000 |
| 356 | #define T3_CHIP_ID_5703_A1 0x1001 |
| 357 | #define T3_CHIP_ID_5703_A2 0x1002 |
| 358 | |
| 359 | #define T3_CHIP_ID_5704_A0 0x2000 |
| 360 | |
| 361 | /* Chip Id. */ |
| 362 | #define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) |
| 363 | #define T3_ASIC_REV_5700 0x07 |
| 364 | #define T3_ASIC_REV_5701 0x00 |
| 365 | #define T3_ASIC_REV_5703 0x01 |
| 366 | #define T3_ASIC_REV_5704 0x02 |
| 367 | |
| 368 | |
| 369 | /* Chip id and revision. */ |
| 370 | #define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) |
| 371 | #define T3_CHIP_REV_5700_AX 0x70 |
| 372 | #define T3_CHIP_REV_5700_BX 0x71 |
| 373 | #define T3_CHIP_REV_5700_CX 0x72 |
| 374 | #define T3_CHIP_REV_5701_AX 0x00 |
| 375 | |
| 376 | /* Metal revision. */ |
| 377 | #define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) |
| 378 | #define T3_METAL_REV_A0 0x00 |
| 379 | #define T3_METAL_REV_A1 0x01 |
| 380 | #define T3_METAL_REV_B0 0x00 |
| 381 | #define T3_METAL_REV_B1 0x01 |
| 382 | #define T3_METAL_REV_B2 0x02 |
| 383 | |
| 384 | #define T3_PCI_REG_CLOCK_CTRL 0x74 |
| 385 | |
| 386 | #define T3_PCI_DISABLE_RX_CLOCK BIT_10 |
| 387 | #define T3_PCI_DISABLE_TX_CLOCK BIT_11 |
| 388 | #define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 |
| 389 | #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 |
| 390 | #define T3_PCI_44MHZ_CORE_CLOCK BIT_18 |
| 391 | |
| 392 | |
| 393 | #define T3_PCI_REG_ADDR_REG 0x78 |
| 394 | #define T3_PCI_REG_DATA_REG 0x80 |
| 395 | |
| 396 | #define T3_PCI_MEM_WIN_ADDR_REG 0x7c |
| 397 | #define T3_PCI_MEM_WIN_DATA_REG 0x84 |
| 398 | |
| 399 | #define T3_PCI_PM_CAP_REG 0x48 |
| 400 | |
| 401 | #define T3_PCI_PM_CAP_PME_D3COLD BIT_31 |
| 402 | #define T3_PCI_PM_CAP_PME_D3HOT BIT_30 |
| 403 | |
| 404 | #define T3_PCI_PM_STATUS_CTRL_REG 0x4c |
| 405 | |
| 406 | #define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) |
| 407 | #define T3_PM_POWER_STATE_D0 BIT_NONE |
| 408 | #define T3_PM_POWER_STATE_D1 BIT_0 |
| 409 | #define T3_PM_POWER_STATE_D2 BIT_1 |
| 410 | #define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) |
| 411 | |
| 412 | #define T3_PM_PME_ENABLE BIT_8 |
| 413 | #define T3_PM_PME_ASSERTED BIT_15 |
| 414 | |
| 415 | |
| 416 | /* PCI state register. */ |
| 417 | #define T3_PCI_STATE_REG 0x70 |
| 418 | |
| 419 | #define T3_PCI_STATE_FORCE_RESET BIT_0 |
| 420 | #define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 |
| 421 | #define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 |
| 422 | #define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 |
| 423 | #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 |
| 424 | |
| 425 | |
| 426 | /* Broadcom subsystem/subvendor IDs. */ |
| 427 | #define T3_SVID_BROADCOM 0x14e4 |
| 428 | |
| 429 | #define T3_SSID_BROADCOM_BCM95700A6 0x1644 |
| 430 | #define T3_SSID_BROADCOM_BCM95701A5 0x0001 |
| 431 | #define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ |
| 432 | #define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ |
| 433 | #define T3_SSID_BROADCOM_BCM95701T1 0x0005 |
| 434 | #define T3_SSID_BROADCOM_BCM95701T8 0x0006 |
| 435 | #define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ |
| 436 | #define T3_SSID_BROADCOM_BCM95701A10 0x0008 |
| 437 | #define T3_SSID_BROADCOM_BCM95701A12 0x8008 |
| 438 | #define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 |
| 439 | #define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 |
| 440 | |
| 441 | /* 3COM subsystem/subvendor IDs. */ |
| 442 | #define T3_SVID_3COM 0x10b7 |
| 443 | |
| 444 | #define T3_SSID_3COM_3C996T 0x1000 |
| 445 | #define T3_SSID_3COM_3C996BT 0x1006 |
| 446 | #define T3_SSID_3COM_3C996CT 0x1002 |
| 447 | #define T3_SSID_3COM_3C997T 0x1003 |
| 448 | #define T3_SSID_3COM_3C1000T 0x1007 |
| 449 | #define T3_SSID_3COM_3C940BR01 0x1008 |
| 450 | |
| 451 | /* Fiber boards. */ |
| 452 | #define T3_SSID_3COM_3C996SX 0x1004 |
| 453 | #define T3_SSID_3COM_3C997SX 0x1005 |
| 454 | |
| 455 | |
| 456 | /* Dell subsystem/subvendor IDs. */ |
| 457 | |
| 458 | #define T3_SVID_DELL 0x1028 |
| 459 | |
| 460 | #define T3_SSID_DELL_VIPER 0x00d1 |
| 461 | #define T3_SSID_DELL_JAGUAR 0x0106 |
| 462 | #define T3_SSID_DELL_MERLOT 0x0109 |
| 463 | #define T3_SSID_DELL_SLIM_MERLOT 0x010a |
| 464 | |
| 465 | /* Compaq subsystem/subvendor IDs */ |
| 466 | |
| 467 | #define T3_SVID_COMPAQ 0x0e11 |
| 468 | |
| 469 | #define T3_SSID_COMPAQ_BANSHEE 0x007c |
| 470 | #define T3_SSID_COMPAQ_BANSHEE_2 0x009a |
| 471 | #define T3_SSID_COMPAQ_CHANGELING 0x007d |
| 472 | #define T3_SSID_COMPAQ_NC7780 0x0085 |
| 473 | #define T3_SSID_COMPAQ_NC7780_2 0x0099 |
| 474 | |
| 475 | |
| 476 | /******************************************************************************/ |
| 477 | /* MII registers. */ |
| 478 | /******************************************************************************/ |
| 479 | |
| 480 | /* Control register. */ |
| 481 | #define PHY_CTRL_REG 0x00 |
| 482 | |
| 483 | #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) |
| 484 | #define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE |
| 485 | #define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 |
| 486 | #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 |
| 487 | #define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 |
| 488 | #define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 |
| 489 | #define PHY_CTRL_RESTART_AUTO_NEG BIT_9 |
| 490 | #define PHY_CTRL_ISOLATE_PHY BIT_10 |
| 491 | #define PHY_CTRL_LOWER_POWER_MODE BIT_11 |
| 492 | #define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 |
| 493 | #define PHY_CTRL_LOOPBACK_MODE BIT_14 |
| 494 | #define PHY_CTRL_PHY_RESET BIT_15 |
| 495 | |
| 496 | |
| 497 | /* Status register. */ |
| 498 | #define PHY_STATUS_REG 0x01 |
| 499 | |
| 500 | #define PHY_STATUS_LINK_PASS BIT_2 |
| 501 | #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 |
| 502 | |
| 503 | |
| 504 | /* Phy Id registers. */ |
| 505 | #define PHY_ID1_REG 0x02 |
| 506 | #define PHY_ID1_OUI_MASK 0xffff |
| 507 | |
| 508 | #define PHY_ID2_REG 0x03 |
| 509 | #define PHY_ID2_REV_MASK 0x000f |
| 510 | #define PHY_ID2_MODEL_MASK 0x03f0 |
| 511 | #define PHY_ID2_OUI_MASK 0xfc00 |
| 512 | |
| 513 | |
| 514 | /* Auto-negotiation advertisement register. */ |
| 515 | #define PHY_AN_AD_REG 0x04 |
| 516 | |
| 517 | #define PHY_AN_AD_ASYM_PAUSE BIT_11 |
| 518 | #define PHY_AN_AD_PAUSE_CAPABLE BIT_10 |
| 519 | #define PHY_AN_AD_10BASET_HALF BIT_5 |
| 520 | #define PHY_AN_AD_10BASET_FULL BIT_6 |
| 521 | #define PHY_AN_AD_100BASETX_HALF BIT_7 |
| 522 | #define PHY_AN_AD_100BASETX_FULL BIT_8 |
| 523 | #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 |
| 524 | |
| 525 | |
| 526 | /* Auto-negotiation Link Partner Ability register. */ |
| 527 | #define PHY_LINK_PARTNER_ABILITY_REG 0x05 |
| 528 | |
| 529 | #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 |
| 530 | #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 |
| 531 | |
| 532 | |
| 533 | /* Auto-negotiation expansion register. */ |
| 534 | #define PHY_AN_EXPANSION_REG 0x06 |
| 535 | |
| 536 | |
| 537 | |
| 538 | /******************************************************************************/ |
| 539 | /* BCM5400 and BCM5401 phy info. */ |
| 540 | /******************************************************************************/ |
| 541 | |
| 542 | #define PHY_DEVICE_ID 1 |
| 543 | |
| 544 | /* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ |
| 545 | #define PHY_UNKNOWN_PHY 0x00000000 |
| 546 | #define PHY_BCM5400_PHY_ID 0x60008040 |
| 547 | #define PHY_BCM5401_PHY_ID 0x60008050 |
| 548 | #define PHY_BCM5411_PHY_ID 0x60008070 |
| 549 | #define PHY_BCM5701_PHY_ID 0x60008110 |
| 550 | #define PHY_BCM5703_PHY_ID 0x60008160 |
| 551 | #define PHY_BCM5704_PHY_ID 0x60008190 |
| 552 | #define PHY_BCM8002_PHY_ID 0x60010140 |
| 553 | |
| 554 | #define PHY_BCM5401_B0_REV 0x1 |
| 555 | #define PHY_BCM5401_B2_REV 0x3 |
| 556 | #define PHY_BCM5401_C0_REV 0x6 |
| 557 | |
| 558 | #define PHY_ID_OUI_MASK 0xfffffc00 |
| 559 | #define PHY_ID_MODEL_MASK 0x000003f0 |
| 560 | #define PHY_ID_REV_MASK 0x0000000f |
| 561 | #define PHY_ID_MASK (PHY_ID_OUI_MASK | \ |
| 562 | PHY_ID_MODEL_MASK) |
| 563 | |
| 564 | |
| 565 | #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ |
| 566 | (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ |
| 567 | (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ |
| 568 | (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ |
| 569 | (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ |
| 570 | (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ |
| 571 | (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) |
| 572 | |
| 573 | |
| 574 | |
| 575 | /* 1000Base-T control register. */ |
| 576 | #define BCM540X_1000BASET_CTRL_REG 0x09 |
| 577 | |
| 578 | #define BCM540X_AN_AD_1000BASET_HALF BIT_8 |
| 579 | #define BCM540X_AN_AD_1000BASET_FULL BIT_9 |
| 580 | #define BCM540X_CONFIG_AS_MASTER BIT_11 |
| 581 | #define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 |
| 582 | |
| 583 | |
| 584 | /* Extended control register. */ |
| 585 | #define BCM540X_EXT_CTRL_REG 0x10 |
| 586 | |
| 587 | #define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 |
| 588 | #define BCM540X_EXT_CTRL_TBI BIT_15 |
| 589 | |
| 590 | /* PHY extended status register. */ |
| 591 | #define BCM540X_EXT_STATUS_REG 0x11 |
| 592 | |
| 593 | #define BCM540X_EXT_STATUS_LINK_PASS BIT_8 |
| 594 | |
| 595 | |
| 596 | /* DSP Coefficient Read/Write Port. */ |
| 597 | #define BCM540X_DSP_RW_PORT 0x15 |
| 598 | |
| 599 | |
| 600 | /* DSP Coeficient Address Register. */ |
| 601 | #define BCM540X_DSP_ADDRESS_REG 0x17 |
| 602 | |
| 603 | #define BCM540X_DSP_TAP_NUMBER_MASK 0x00 |
| 604 | #define BCM540X_DSP_AGC_A 0x00 |
| 605 | #define BCM540X_DSP_AGC_B 0x01 |
| 606 | #define BCM540X_DSP_MSE_PAIR_STATUS 0x02 |
| 607 | #define BCM540X_DSP_SOFT_DECISION 0x03 |
| 608 | #define BCM540X_DSP_PHASE_REG 0x04 |
| 609 | #define BCM540X_DSP_SKEW 0x05 |
| 610 | #define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 |
| 611 | #define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 |
| 612 | #define BCM540X_DSP_LAST_ECHO 0x08 |
| 613 | #define BCM540X_DSP_FREQUENCY 0x09 |
| 614 | #define BCM540X_DSP_PLL_BANDWIDTH 0x0a |
| 615 | #define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b |
| 616 | |
| 617 | #define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) |
| 618 | #define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) |
| 619 | #define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) |
| 620 | #define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) |
| 621 | #define BCM540X_DSP_FILTER_FEXT0 BIT_11 |
| 622 | #define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) |
| 623 | #define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) |
| 624 | #define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) |
| 625 | #define BCM540X_DSP_FILTER_NEXT0 BIT_10 |
| 626 | #define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) |
| 627 | #define BCM540X_DSP_FILTER_DFE BIT_9 |
| 628 | #define BCM540X_DSP_FILTER_FFE BIT_8 |
| 629 | |
| 630 | #define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 |
| 631 | |
| 632 | #define BCM540X_DSP_SEL_CH_0 BIT_NONE |
| 633 | #define BCM540X_DSP_SEL_CH_1 BIT_13 |
| 634 | #define BCM540X_DSP_SEL_CH_2 BIT_14 |
| 635 | #define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) |
| 636 | |
| 637 | #define BCM540X_CONTROL_ALL_CHANNELS BIT_15 |
| 638 | |
| 639 | |
| 640 | /* Auxilliary Control Register (Shadow Register) */ |
| 641 | #define BCM5401_AUX_CTRL 0x18 |
| 642 | |
| 643 | #define BCM5401_SHADOW_SEL_MASK 0x7 |
| 644 | #define BCM5401_SHADOW_SEL_NORMAL 0x00 |
| 645 | #define BCM5401_SHADOW_SEL_10BASET 0x01 |
| 646 | #define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 |
| 647 | #define BCM5401_SHADOW_SEL_IP_PHONE 0x03 |
| 648 | #define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 |
| 649 | #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 |
| 650 | #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 |
| 651 | |
| 652 | |
| 653 | /* Shadow register selector == '000' */ |
| 654 | #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 |
| 655 | #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 |
| 656 | #define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 |
| 657 | #define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 |
| 658 | #define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 |
| 659 | #define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE |
| 660 | #define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 |
| 661 | #define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 |
| 662 | #define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) |
| 663 | #define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 |
| 664 | #define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 |
| 665 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE |
| 666 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 |
| 667 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 |
| 668 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) |
| 669 | #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 |
| 670 | #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 |
| 671 | |
| 672 | |
| 673 | /* Auxilliary status summary. */ |
| 674 | #define BCM540X_AUX_STATUS_REG 0x19 |
| 675 | |
| 676 | #define BCM540X_AUX_LINK_PASS BIT_2 |
| 677 | #define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) |
| 678 | #define BCM540X_AUX_10BASET_HD BIT_8 |
| 679 | #define BCM540X_AUX_10BASET_FD BIT_9 |
| 680 | #define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) |
| 681 | #define BCM540X_AUX_100BASET4 BIT_10 |
| 682 | #define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) |
| 683 | #define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) |
| 684 | #define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) |
| 685 | |
| 686 | |
| 687 | /* Interrupt status. */ |
| 688 | #define BCM540X_INT_STATUS_REG 0x1a |
| 689 | |
| 690 | #define BCM540X_INT_LINK_CHANGE BIT_1 |
| 691 | #define BCM540X_INT_SPEED_CHANGE BIT_2 |
| 692 | #define BCM540X_INT_DUPLEX_CHANGE BIT_3 |
| 693 | #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 |
| 694 | |
| 695 | |
| 696 | /* Interrupt mask register. */ |
| 697 | #define BCM540X_INT_MASK_REG 0x1b |
| 698 | |
| 699 | |
| 700 | |
| 701 | /******************************************************************************/ |
| 702 | /* Register definitions. */ |
| 703 | /******************************************************************************/ |
| 704 | |
| 705 | typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; |
| 706 | typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; |
| 707 | typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; |
| 708 | |
| 709 | typedef struct { |
| 710 | /* Big endian format. */ |
| 711 | T3_32BIT_REGISTER High; |
| 712 | T3_32BIT_REGISTER Low; |
| 713 | } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; |
| 714 | |
| 715 | typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; |
| 716 | |
| 717 | #define T3_NUM_OF_DMA_DESC 256 |
| 718 | #define T3_NUM_OF_MBUF 768 |
| 719 | |
| 720 | typedef struct |
| 721 | { |
| 722 | T3_64BIT_REGISTER host_addr; |
| 723 | T3_32BIT_REGISTER nic_mbuf; |
| 724 | T3_16BIT_REGISTER len; |
| 725 | T3_16BIT_REGISTER cqid_sqid; |
| 726 | T3_32BIT_REGISTER flags; |
| 727 | T3_32BIT_REGISTER opaque1; |
| 728 | T3_32BIT_REGISTER opaque2; |
| 729 | T3_32BIT_REGISTER opaque3; |
| 730 | }T3_DMA_DESC, *PT3_DMA_DESC; |
| 731 | |
| 732 | |
| 733 | |
| 734 | /******************************************************************************/ |
| 735 | /* Ring control block. */ |
| 736 | /******************************************************************************/ |
| 737 | |
| 738 | typedef struct { |
| 739 | T3_64BIT_REGISTER HostRingAddr; |
| 740 | |
| 741 | union { |
| 742 | struct { |
| 743 | #ifdef BIG_ENDIAN_HOST |
| 744 | T3_16BIT_REGISTER MaxLen; |
| 745 | T3_16BIT_REGISTER Flags; |
| 746 | #else /* BIG_ENDIAN_HOST */ |
| 747 | T3_16BIT_REGISTER Flags; |
| 748 | T3_16BIT_REGISTER MaxLen; |
| 749 | #endif |
| 750 | } s; |
| 751 | |
| 752 | T3_32BIT_REGISTER MaxLen_Flags; |
| 753 | } u; |
| 754 | |
| 755 | T3_32BIT_REGISTER NicRingAddr; |
| 756 | } T3_RCB, *PT3_RCB; |
| 757 | |
| 758 | #define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 |
| 759 | #define T3_RCB_FLAG_RING_DISABLED BIT_1 |
| 760 | |
| 761 | |
| 762 | |
| 763 | /******************************************************************************/ |
| 764 | /* Status block. */ |
| 765 | /******************************************************************************/ |
| 766 | |
| 767 | /* |
| 768 | * Size of status block is actually 0x50 bytes. Use 0x80 bytes for |
| 769 | * cache line alignment. |
| 770 | */ |
| 771 | #define T3_STATUS_BLOCK_SIZE 0x80 |
| 772 | |
| 773 | typedef struct { |
| 774 | volatile LM_UINT32 Status; |
| 775 | #define STATUS_BLOCK_UPDATED BIT_0 |
| 776 | #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 |
| 777 | #define STATUS_BLOCK_ERROR BIT_2 |
| 778 | |
| 779 | volatile LM_UINT32 StatusTag; |
| 780 | |
| 781 | #ifdef BIG_ENDIAN_HOST |
| 782 | volatile LM_UINT16 RcvStdConIdx; |
| 783 | volatile LM_UINT16 RcvJumboConIdx; |
| 784 | |
| 785 | volatile LM_UINT16 Reserved2; |
| 786 | volatile LM_UINT16 RcvMiniConIdx; |
| 787 | |
| 788 | struct { |
| 789 | volatile LM_UINT16 SendConIdx; /* Send consumer index. */ |
| 790 | volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ |
| 791 | } Idx[16]; |
| 792 | #else /* BIG_ENDIAN_HOST */ |
| 793 | volatile LM_UINT16 RcvJumboConIdx; |
| 794 | volatile LM_UINT16 RcvStdConIdx; |
| 795 | |
| 796 | volatile LM_UINT16 RcvMiniConIdx; |
| 797 | volatile LM_UINT16 Reserved2; |
| 798 | |
| 799 | struct { |
| 800 | volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ |
| 801 | volatile LM_UINT16 SendConIdx; /* Send consumer index. */ |
| 802 | } Idx[16]; |
| 803 | #endif |
| 804 | } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; |
| 805 | |
| 806 | |
| 807 | |
| 808 | /******************************************************************************/ |
| 809 | /* Receive buffer descriptors. */ |
| 810 | /******************************************************************************/ |
| 811 | |
| 812 | typedef struct { |
| 813 | T3_64BIT_HOST_ADDR HostAddr; |
| 814 | |
| 815 | #ifdef BIG_ENDIAN_HOST |
| 816 | volatile LM_UINT16 Index; |
| 817 | volatile LM_UINT16 Len; |
| 818 | |
| 819 | volatile LM_UINT16 Type; |
| 820 | volatile LM_UINT16 Flags; |
| 821 | |
| 822 | volatile LM_UINT16 IpCksum; |
| 823 | volatile LM_UINT16 TcpUdpCksum; |
| 824 | |
| 825 | volatile LM_UINT16 ErrorFlag; |
| 826 | volatile LM_UINT16 VlanTag; |
| 827 | #else /* BIG_ENDIAN_HOST */ |
| 828 | volatile LM_UINT16 Len; |
| 829 | volatile LM_UINT16 Index; |
| 830 | |
| 831 | volatile LM_UINT16 Flags; |
| 832 | volatile LM_UINT16 Type; |
| 833 | |
| 834 | volatile LM_UINT16 TcpUdpCksum; |
| 835 | volatile LM_UINT16 IpCksum; |
| 836 | |
| 837 | volatile LM_UINT16 VlanTag; |
| 838 | volatile LM_UINT16 ErrorFlag; |
| 839 | #endif |
| 840 | |
| 841 | volatile LM_UINT32 Reserved; |
| 842 | volatile LM_UINT32 Opaque; |
| 843 | } T3_RCV_BD, *PT3_RCV_BD; |
| 844 | |
| 845 | |
| 846 | typedef struct { |
| 847 | T3_64BIT_HOST_ADDR HostAddr[3]; |
| 848 | |
| 849 | #ifdef BIG_ENDIAN_HOST |
| 850 | LM_UINT16 Len1; |
| 851 | LM_UINT16 Len2; |
| 852 | |
| 853 | LM_UINT16 Len3; |
| 854 | LM_UINT16 Reserved1; |
| 855 | #else /* BIG_ENDIAN_HOST */ |
| 856 | LM_UINT16 Len2; |
| 857 | LM_UINT16 Len1; |
| 858 | |
| 859 | LM_UINT16 Reserved1; |
| 860 | LM_UINT16 Len3; |
| 861 | #endif |
| 862 | |
| 863 | T3_RCV_BD StdRcvBd; |
| 864 | } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; |
| 865 | |
| 866 | |
| 867 | /* Error flags. */ |
| 868 | #define RCV_BD_ERR_BAD_CRC 0x0001 |
| 869 | #define RCV_BD_ERR_COLL_DETECT 0x0002 |
| 870 | #define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 |
| 871 | #define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 |
| 872 | #define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 |
| 873 | #define RCV_BD_ERR_MAC_ABORT 0x0020 |
| 874 | #define RCV_BD_ERR_LEN_LT_64 0x0040 |
| 875 | #define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 |
| 876 | #define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 |
| 877 | |
| 878 | |
| 879 | /* Buffer descriptor flags. */ |
| 880 | #define RCV_BD_FLAG_END 0x0004 |
| 881 | #define RCV_BD_FLAG_JUMBO_RING 0x0020 |
| 882 | #define RCV_BD_FLAG_VLAN_TAG 0x0040 |
| 883 | #define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 |
| 884 | #define RCV_BD_FLAG_MINI_RING 0x0800 |
| 885 | #define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 |
| 886 | #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 |
| 887 | #define RCV_BD_FLAG_TCP_PACKET 0x4000 |
| 888 | |
| 889 | |
| 890 | |
| 891 | /******************************************************************************/ |
| 892 | /* Send buffer descriptor. */ |
| 893 | /******************************************************************************/ |
| 894 | |
| 895 | typedef struct { |
| 896 | T3_64BIT_HOST_ADDR HostAddr; |
| 897 | |
| 898 | union { |
| 899 | struct { |
| 900 | #ifdef BIG_ENDIAN_HOST |
| 901 | LM_UINT16 Len; |
| 902 | LM_UINT16 Flags; |
| 903 | #else /* BIG_ENDIAN_HOST */ |
| 904 | LM_UINT16 Flags; |
| 905 | LM_UINT16 Len; |
| 906 | #endif |
| 907 | } s1; |
| 908 | |
| 909 | LM_UINT32 Len_Flags; |
| 910 | } u1; |
| 911 | |
| 912 | union { |
| 913 | struct { |
| 914 | #ifdef BIG_ENDIAN_HOST |
| 915 | LM_UINT16 Reserved; |
| 916 | LM_UINT16 VlanTag; |
| 917 | #else /* BIG_ENDIAN_HOST */ |
| 918 | LM_UINT16 VlanTag; |
| 919 | LM_UINT16 Reserved; |
| 920 | #endif |
| 921 | } s2; |
| 922 | |
| 923 | LM_UINT32 VlanTag; |
| 924 | } u2; |
| 925 | } T3_SND_BD, *PT3_SND_BD; |
| 926 | |
| 927 | |
| 928 | /* Send buffer descriptor flags. */ |
| 929 | #define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 |
| 930 | #define SND_BD_FLAG_IP_CKSUM 0x0002 |
| 931 | #define SND_BD_FLAG_END 0x0004 |
| 932 | #define SND_BD_FLAG_IP_FRAG 0x0008 |
| 933 | #define SND_BD_FLAG_IP_FRAG_END 0x0010 |
| 934 | #define SND_BD_FLAG_VLAN_TAG 0x0040 |
| 935 | #define SND_BD_FLAG_COAL_NOW 0x0080 |
| 936 | #define SND_BD_FLAG_CPU_PRE_DMA 0x0100 |
| 937 | #define SND_BD_FLAG_CPU_POST_DMA 0x0200 |
| 938 | #define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 |
| 939 | #define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 |
| 940 | #define SND_BD_FLAG_DONT_GEN_CRC 0x8000 |
| 941 | |
| 942 | /* MBUFs */ |
| 943 | typedef struct T3_MBUF_FRAME_DESC { |
| 944 | #ifdef BIG_ENDIAN_HOST |
| 945 | LM_UINT32 status_control; |
| 946 | union { |
| 947 | struct { |
| 948 | LM_UINT8 cqid; |
| 949 | LM_UINT8 reserved1; |
| 950 | LM_UINT16 length; |
| 951 | }s1; |
| 952 | LM_UINT32 word; |
| 953 | }u1; |
| 954 | union { |
| 955 | struct |
| 956 | { |
| 957 | LM_UINT16 ip_hdr_start; |
| 958 | LM_UINT16 tcp_udp_hdr_start; |
| 959 | }s2; |
| 960 | |
| 961 | LM_UINT32 word; |
| 962 | }u2; |
| 963 | |
| 964 | union { |
| 965 | struct { |
| 966 | LM_UINT16 data_start; |
| 967 | LM_UINT16 vlan_id; |
| 968 | }s3; |
| 969 | |
| 970 | LM_UINT32 word; |
| 971 | }u3; |
| 972 | |
| 973 | union { |
| 974 | struct { |
| 975 | LM_UINT16 ip_checksum; |
| 976 | LM_UINT16 tcp_udp_checksum; |
| 977 | }s4; |
| 978 | |
| 979 | LM_UINT32 word; |
| 980 | }u4; |
| 981 | |
| 982 | union { |
| 983 | struct { |
| 984 | LM_UINT16 pseudo_checksum; |
| 985 | LM_UINT16 checksum_status; |
| 986 | }s5; |
| 987 | |
| 988 | LM_UINT32 word; |
| 989 | }u5; |
| 990 | |
| 991 | union { |
| 992 | struct { |
| 993 | LM_UINT16 rule_match; |
| 994 | LM_UINT8 class; |
| 995 | LM_UINT8 rupt; |
| 996 | }s6; |
| 997 | |
| 998 | LM_UINT32 word; |
| 999 | }u6; |
| 1000 | |
| 1001 | union { |
| 1002 | struct { |
| 1003 | LM_UINT16 reserved2; |
| 1004 | LM_UINT16 mbuf_num; |
| 1005 | }s7; |
| 1006 | |
| 1007 | LM_UINT32 word; |
| 1008 | }u7; |
| 1009 | |
| 1010 | LM_UINT32 reserved3; |
| 1011 | LM_UINT32 reserved4; |
| 1012 | #else |
| 1013 | LM_UINT32 status_control; |
| 1014 | union { |
| 1015 | struct { |
| 1016 | LM_UINT16 length; |
| 1017 | LM_UINT8 reserved1; |
| 1018 | LM_UINT8 cqid; |
| 1019 | }s1; |
| 1020 | LM_UINT32 word; |
| 1021 | }u1; |
| 1022 | union { |
| 1023 | struct |
| 1024 | { |
| 1025 | LM_UINT16 tcp_udp_hdr_start; |
| 1026 | LM_UINT16 ip_hdr_start; |
| 1027 | }s2; |
| 1028 | |
| 1029 | LM_UINT32 word; |
| 1030 | }u2; |
| 1031 | |
| 1032 | union { |
| 1033 | struct { |
| 1034 | LM_UINT16 vlan_id; |
| 1035 | LM_UINT16 data_start; |
| 1036 | }s3; |
| 1037 | |
| 1038 | LM_UINT32 word; |
| 1039 | }u3; |
| 1040 | |
| 1041 | union { |
| 1042 | struct { |
| 1043 | LM_UINT16 tcp_udp_checksum; |
| 1044 | LM_UINT16 ip_checksum; |
| 1045 | }s4; |
| 1046 | |
| 1047 | LM_UINT32 word; |
| 1048 | }u4; |
| 1049 | |
| 1050 | union { |
| 1051 | struct { |
| 1052 | LM_UINT16 checksum_status; |
| 1053 | LM_UINT16 pseudo_checksum; |
| 1054 | }s5; |
| 1055 | |
| 1056 | LM_UINT32 word; |
| 1057 | }u5; |
| 1058 | |
| 1059 | union { |
| 1060 | struct { |
| 1061 | LM_UINT8 rupt; |
| 1062 | LM_UINT8 class; |
| 1063 | LM_UINT16 rule_match; |
| 1064 | }s6; |
| 1065 | |
| 1066 | LM_UINT32 word; |
| 1067 | }u6; |
| 1068 | |
| 1069 | union { |
| 1070 | struct { |
| 1071 | LM_UINT16 mbuf_num; |
| 1072 | LM_UINT16 reserved2; |
| 1073 | }s7; |
| 1074 | |
| 1075 | LM_UINT32 word; |
| 1076 | }u7; |
| 1077 | |
| 1078 | LM_UINT32 reserved3; |
| 1079 | LM_UINT32 reserved4; |
| 1080 | #endif |
| 1081 | }T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; |
| 1082 | |
| 1083 | typedef struct T3_MBUF_HDR { |
| 1084 | union { |
| 1085 | struct { |
| 1086 | unsigned int C:1; |
| 1087 | unsigned int F:1; |
| 1088 | unsigned int reserved1:7; |
| 1089 | unsigned int next_mbuf:16; |
| 1090 | unsigned int length:7; |
| 1091 | }s1; |
| 1092 | |
| 1093 | LM_UINT32 word; |
| 1094 | }u1; |
| 1095 | |
| 1096 | LM_UINT32 next_frame_ptr; |
| 1097 | }T3_MBUF_HDR, *PT3_MBUF_HDR; |
| 1098 | |
| 1099 | typedef struct T3_MBUF |
| 1100 | { |
| 1101 | T3_MBUF_HDR hdr; |
| 1102 | union |
| 1103 | { |
| 1104 | struct { |
| 1105 | T3_MBUF_FRAME_DESC frame_hdr; |
| 1106 | LM_UINT32 data[20]; |
| 1107 | }s1; |
| 1108 | |
| 1109 | struct { |
| 1110 | LM_UINT32 data[30]; |
| 1111 | }s2; |
| 1112 | }body; |
| 1113 | }T3_MBUF, *PT3_MBUF; |
| 1114 | |
| 1115 | #define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) |
| 1116 | #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | /******************************************************************************/ |
| 1121 | /* Statistics block. */ |
| 1122 | /******************************************************************************/ |
| 1123 | |
| 1124 | typedef struct { |
| 1125 | LM_UINT8 Reserved0[0x400-0x300]; |
| 1126 | |
| 1127 | /* Statistics maintained by Receive MAC. */ |
| 1128 | T3_64BIT_REGISTER ifHCInOctets; |
| 1129 | T3_64BIT_REGISTER Reserved1; |
| 1130 | T3_64BIT_REGISTER etherStatsFragments; |
| 1131 | T3_64BIT_REGISTER ifHCInUcastPkts; |
| 1132 | T3_64BIT_REGISTER ifHCInMulticastPkts; |
| 1133 | T3_64BIT_REGISTER ifHCInBroadcastPkts; |
| 1134 | T3_64BIT_REGISTER dot3StatsFCSErrors; |
| 1135 | T3_64BIT_REGISTER dot3StatsAlignmentErrors; |
| 1136 | T3_64BIT_REGISTER xonPauseFramesReceived; |
| 1137 | T3_64BIT_REGISTER xoffPauseFramesReceived; |
| 1138 | T3_64BIT_REGISTER macControlFramesReceived; |
| 1139 | T3_64BIT_REGISTER xoffStateEntered; |
| 1140 | T3_64BIT_REGISTER dot3StatsFramesTooLong; |
| 1141 | T3_64BIT_REGISTER etherStatsJabbers; |
| 1142 | T3_64BIT_REGISTER etherStatsUndersizePkts; |
| 1143 | T3_64BIT_REGISTER inRangeLengthError; |
| 1144 | T3_64BIT_REGISTER outRangeLengthError; |
| 1145 | T3_64BIT_REGISTER etherStatsPkts64Octets; |
| 1146 | T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; |
| 1147 | T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; |
| 1148 | T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; |
| 1149 | T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; |
| 1150 | T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; |
| 1151 | T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; |
| 1152 | T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; |
| 1153 | T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; |
| 1154 | T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; |
| 1155 | |
| 1156 | T3_64BIT_REGISTER Unused1[37]; |
| 1157 | |
| 1158 | /* Statistics maintained by Transmit MAC. */ |
| 1159 | T3_64BIT_REGISTER ifHCOutOctets; |
| 1160 | T3_64BIT_REGISTER Reserved2; |
| 1161 | T3_64BIT_REGISTER etherStatsCollisions; |
| 1162 | T3_64BIT_REGISTER outXonSent; |
| 1163 | T3_64BIT_REGISTER outXoffSent; |
| 1164 | T3_64BIT_REGISTER flowControlDone; |
| 1165 | T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; |
| 1166 | T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; |
| 1167 | T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; |
| 1168 | T3_64BIT_REGISTER dot3StatsDeferredTransmissions; |
| 1169 | T3_64BIT_REGISTER Reserved3; |
| 1170 | T3_64BIT_REGISTER dot3StatsExcessiveCollisions; |
| 1171 | T3_64BIT_REGISTER dot3StatsLateCollisions; |
| 1172 | T3_64BIT_REGISTER dot3Collided2Times; |
| 1173 | T3_64BIT_REGISTER dot3Collided3Times; |
| 1174 | T3_64BIT_REGISTER dot3Collided4Times; |
| 1175 | T3_64BIT_REGISTER dot3Collided5Times; |
| 1176 | T3_64BIT_REGISTER dot3Collided6Times; |
| 1177 | T3_64BIT_REGISTER dot3Collided7Times; |
| 1178 | T3_64BIT_REGISTER dot3Collided8Times; |
| 1179 | T3_64BIT_REGISTER dot3Collided9Times; |
| 1180 | T3_64BIT_REGISTER dot3Collided10Times; |
| 1181 | T3_64BIT_REGISTER dot3Collided11Times; |
| 1182 | T3_64BIT_REGISTER dot3Collided12Times; |
| 1183 | T3_64BIT_REGISTER dot3Collided13Times; |
| 1184 | T3_64BIT_REGISTER dot3Collided14Times; |
| 1185 | T3_64BIT_REGISTER dot3Collided15Times; |
| 1186 | T3_64BIT_REGISTER ifHCOutUcastPkts; |
| 1187 | T3_64BIT_REGISTER ifHCOutMulticastPkts; |
| 1188 | T3_64BIT_REGISTER ifHCOutBroadcastPkts; |
| 1189 | T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; |
| 1190 | T3_64BIT_REGISTER ifOutDiscards; |
| 1191 | T3_64BIT_REGISTER ifOutErrors; |
| 1192 | |
| 1193 | T3_64BIT_REGISTER Unused2[31]; |
| 1194 | |
| 1195 | /* Statistics maintained by Receive List Placement. */ |
| 1196 | T3_64BIT_REGISTER COSIfHCInPkts[16]; |
| 1197 | T3_64BIT_REGISTER COSFramesDroppedDueToFilters; |
| 1198 | T3_64BIT_REGISTER nicDmaWriteQueueFull; |
| 1199 | T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; |
| 1200 | T3_64BIT_REGISTER nicNoMoreRxBDs; |
| 1201 | T3_64BIT_REGISTER ifInDiscards; |
| 1202 | T3_64BIT_REGISTER ifInErrors; |
| 1203 | T3_64BIT_REGISTER nicRecvThresholdHit; |
| 1204 | |
| 1205 | T3_64BIT_REGISTER Unused3[9]; |
| 1206 | |
| 1207 | /* Statistics maintained by Send Data Initiator. */ |
| 1208 | T3_64BIT_REGISTER COSIfHCOutPkts[16]; |
| 1209 | T3_64BIT_REGISTER nicDmaReadQueueFull; |
| 1210 | T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; |
| 1211 | T3_64BIT_REGISTER nicSendDataCompQueueFull; |
| 1212 | |
| 1213 | /* Statistics maintained by Host Coalescing. */ |
| 1214 | T3_64BIT_REGISTER nicRingSetSendProdIndex; |
| 1215 | T3_64BIT_REGISTER nicRingStatusUpdate; |
| 1216 | T3_64BIT_REGISTER nicInterrupts; |
| 1217 | T3_64BIT_REGISTER nicAvoidedInterrupts; |
| 1218 | T3_64BIT_REGISTER nicSendThresholdHit; |
| 1219 | |
| 1220 | LM_UINT8 Reserved4[0xb00-0x9c0]; |
| 1221 | } T3_STATS_BLOCK, *PT3_STATS_BLOCK; |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | /******************************************************************************/ |
| 1226 | /* PCI configuration registers. */ |
| 1227 | /******************************************************************************/ |
| 1228 | |
| 1229 | typedef struct { |
| 1230 | T3_16BIT_REGISTER VendorId; |
| 1231 | T3_16BIT_REGISTER DeviceId; |
| 1232 | |
| 1233 | T3_16BIT_REGISTER Command; |
| 1234 | T3_16BIT_REGISTER Status; |
| 1235 | |
| 1236 | T3_32BIT_REGISTER ClassCodeRevId; |
| 1237 | |
| 1238 | T3_8BIT_REGISTER CacheLineSize; |
| 1239 | T3_8BIT_REGISTER LatencyTimer; |
| 1240 | T3_8BIT_REGISTER HeaderType; |
| 1241 | T3_8BIT_REGISTER Bist; |
| 1242 | |
| 1243 | T3_32BIT_REGISTER MemBaseAddrLow; |
| 1244 | T3_32BIT_REGISTER MemBaseAddrHigh; |
| 1245 | |
| 1246 | LM_UINT8 Unused1[20]; |
| 1247 | |
| 1248 | T3_16BIT_REGISTER SubsystemVendorId; |
| 1249 | T3_16BIT_REGISTER SubsystemId; |
| 1250 | |
| 1251 | T3_32BIT_REGISTER RomBaseAddr; |
| 1252 | |
| 1253 | T3_8BIT_REGISTER PciXCapiblityPtr; |
| 1254 | LM_UINT8 Unused2[7]; |
| 1255 | |
| 1256 | T3_8BIT_REGISTER IntLine; |
| 1257 | T3_8BIT_REGISTER IntPin; |
| 1258 | T3_8BIT_REGISTER MinGnt; |
| 1259 | T3_8BIT_REGISTER MaxLat; |
| 1260 | |
| 1261 | T3_8BIT_REGISTER PciXCapabilities; |
| 1262 | T3_8BIT_REGISTER PmCapabilityPtr; |
| 1263 | T3_16BIT_REGISTER PciXCommand; |
| 1264 | |
| 1265 | T3_32BIT_REGISTER PciXStatus; |
| 1266 | |
| 1267 | T3_8BIT_REGISTER PmCapabilityId; |
| 1268 | T3_8BIT_REGISTER VpdCapabilityPtr; |
| 1269 | T3_16BIT_REGISTER PmCapabilities; |
| 1270 | |
| 1271 | T3_16BIT_REGISTER PmCtrlStatus; |
| 1272 | #define PM_CTRL_PME_STATUS BIT_15 |
| 1273 | #define PM_CTRL_PME_ENABLE BIT_8 |
| 1274 | #define PM_CTRL_PME_POWER_STATE_D0 0 |
| 1275 | #define PM_CTRL_PME_POWER_STATE_D1 1 |
| 1276 | #define PM_CTRL_PME_POWER_STATE_D2 2 |
| 1277 | #define PM_CTRL_PME_POWER_STATE_D3H 3 |
| 1278 | |
| 1279 | T3_8BIT_REGISTER BridgeSupportExt; |
| 1280 | T3_8BIT_REGISTER PmData; |
| 1281 | |
| 1282 | T3_8BIT_REGISTER VpdCapabilityId; |
| 1283 | T3_8BIT_REGISTER MsiCapabilityPtr; |
| 1284 | T3_16BIT_REGISTER VpdAddrFlag; |
| 1285 | #define VPD_FLAG_WRITE (1 << 15) |
| 1286 | #define VPD_FLAG_RW_MASK (1 << 15) |
| 1287 | #define VPD_FLAG_READ 0 |
| 1288 | |
| 1289 | |
| 1290 | T3_32BIT_REGISTER VpdData; |
| 1291 | |
| 1292 | T3_8BIT_REGISTER MsiCapabilityId; |
| 1293 | T3_8BIT_REGISTER NextCapabilityPtr; |
| 1294 | T3_16BIT_REGISTER MsiCtrl; |
| 1295 | #define MSI_CTRL_64BIT_CAP (1 << 7) |
| 1296 | #define MSI_CTRL_MSG_ENABLE(x) (x << 4) |
| 1297 | #define MSI_CTRL_MSG_CAP(x) (x << 1) |
| 1298 | #define MSI_CTRL_ENABLE (1 << 0) |
| 1299 | |
| 1300 | |
| 1301 | T3_32BIT_REGISTER MsiAddrLow; |
| 1302 | T3_32BIT_REGISTER MsiAddrHigh; |
| 1303 | |
| 1304 | T3_16BIT_REGISTER MsiData; |
| 1305 | T3_16BIT_REGISTER Unused3; |
| 1306 | |
| 1307 | T3_32BIT_REGISTER MiscHostCtrl; |
| 1308 | #define MISC_HOST_CTRL_CLEAR_INT BIT_0 |
| 1309 | #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 |
| 1310 | #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 |
| 1311 | #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 |
| 1312 | #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 |
| 1313 | #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 |
| 1314 | #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 |
| 1315 | #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 |
| 1316 | #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 |
| 1317 | #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 |
| 1318 | |
| 1319 | T3_32BIT_REGISTER DmaReadWriteCtrl; |
| 1320 | #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) |
| 1321 | #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 |
| 1322 | #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 |
| 1323 | #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 |
| 1324 | #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) |
| 1325 | #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 |
| 1326 | #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) |
| 1327 | #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) |
| 1328 | #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) |
| 1329 | #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 |
| 1330 | |
| 1331 | |
| 1332 | T3_32BIT_REGISTER PciState; |
| 1333 | #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 |
| 1334 | #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 |
| 1335 | #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 |
| 1336 | #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 |
| 1337 | #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 |
| 1338 | #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 |
| 1339 | #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 |
| 1340 | #define T3_PCI_STATE_FLAT_VIEW BIT_8 |
| 1341 | #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 |
| 1342 | |
| 1343 | T3_32BIT_REGISTER ClockCtrl; |
| 1344 | #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 |
| 1345 | #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 |
| 1346 | #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 |
| 1347 | |
| 1348 | T3_32BIT_REGISTER RegBaseAddr; |
| 1349 | |
| 1350 | T3_32BIT_REGISTER MemWindowBaseAddr; |
| 1351 | |
| 1352 | #ifdef NIC_CPU_VIEW |
| 1353 | /* These registers are ONLY visible to NIC CPU */ |
| 1354 | T3_32BIT_REGISTER PowerConsumed; |
| 1355 | T3_32BIT_REGISTER PowerDissipated; |
| 1356 | #else /* NIC_CPU_VIEW */ |
| 1357 | T3_32BIT_REGISTER RegData; |
| 1358 | T3_32BIT_REGISTER MemWindowData; |
| 1359 | #endif /* !NIC_CPU_VIEW */ |
| 1360 | |
| 1361 | T3_32BIT_REGISTER ModeCtrl; |
| 1362 | |
| 1363 | T3_32BIT_REGISTER MiscCfg; |
| 1364 | |
| 1365 | T3_32BIT_REGISTER MiscLocalCtrl; |
| 1366 | |
| 1367 | T3_32BIT_REGISTER Unused4; |
| 1368 | |
| 1369 | /* NOTE: Big/Little-endian clarification needed. Are these register */ |
| 1370 | /* in big or little endian formate. */ |
| 1371 | T3_64BIT_REGISTER StdRingProdIdx; |
| 1372 | T3_64BIT_REGISTER RcvRetRingConIdx; |
| 1373 | T3_64BIT_REGISTER SndProdIdx; |
| 1374 | |
| 1375 | LM_UINT8 Unused5[80]; |
| 1376 | } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; |
| 1377 | |
| 1378 | #define PCIX_CMD_MAX_SPLIT_MASK 0x0070 |
| 1379 | #define PCIX_CMD_MAX_SPLIT_SHL 4 |
| 1380 | #define PCIX_CMD_MAX_BURST_MASK 0x000c |
| 1381 | #define PCIX_CMD_MAX_BURST_SHL 2 |
| 1382 | #define PCIX_CMD_MAX_BURST_CPIOB 2 |
| 1383 | |
| 1384 | /******************************************************************************/ |
| 1385 | /* Mac control registers. */ |
| 1386 | /******************************************************************************/ |
| 1387 | |
| 1388 | typedef struct { |
| 1389 | /* MAC mode control. */ |
| 1390 | T3_32BIT_REGISTER Mode; |
| 1391 | #define MAC_MODE_GLOBAL_RESET BIT_0 |
| 1392 | #define MAC_MODE_HALF_DUPLEX BIT_1 |
| 1393 | #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) |
| 1394 | #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) |
| 1395 | #define MAC_MODE_PORT_MODE_GMII BIT_3 |
| 1396 | #define MAC_MODE_PORT_MODE_MII BIT_2 |
| 1397 | #define MAC_MODE_PORT_MODE_NONE BIT_NONE |
| 1398 | #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 |
| 1399 | #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 |
| 1400 | #define MAC_MODE_TX_BURSTING BIT_8 |
| 1401 | #define MAC_MODE_MAX_DEFER BIT_9 |
| 1402 | #define MAC_MODE_LINK_POLARITY BIT_10 |
| 1403 | #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 |
| 1404 | #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 |
| 1405 | #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 |
| 1406 | #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 |
| 1407 | #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 |
| 1408 | #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 |
| 1409 | #define MAC_MODE_SEND_CONFIGS BIT_17 |
| 1410 | #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 |
| 1411 | #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 |
| 1412 | #define MAC_MODE_ENABLE_MIP BIT_20 |
| 1413 | #define MAC_MODE_ENABLE_TDE BIT_21 |
| 1414 | #define MAC_MODE_ENABLE_RDE BIT_22 |
| 1415 | #define MAC_MODE_ENABLE_FHDE BIT_23 |
| 1416 | |
| 1417 | /* MAC status */ |
| 1418 | T3_32BIT_REGISTER Status; |
| 1419 | #define MAC_STATUS_PCS_SYNCED BIT_0 |
| 1420 | #define MAC_STATUS_SIGNAL_DETECTED BIT_1 |
| 1421 | #define MAC_STATUS_RECEIVING_CFG BIT_2 |
| 1422 | #define MAC_STATUS_CFG_CHANGED BIT_3 |
| 1423 | #define MAC_STATUS_SYNC_CHANGED BIT_4 |
| 1424 | #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 |
| 1425 | #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 |
| 1426 | #define MAC_STATUS_MI_COMPLETION BIT_22 |
| 1427 | #define MAC_STATUS_MI_INTERRUPT BIT_23 |
| 1428 | #define MAC_STATUS_AP_ERROR BIT_24 |
| 1429 | #define MAC_STATUS_ODI_ERROR BIT_25 |
| 1430 | #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 |
| 1431 | #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 |
| 1432 | |
| 1433 | /* Event Enable */ |
| 1434 | T3_32BIT_REGISTER MacEvent; |
| 1435 | #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 |
| 1436 | #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 |
| 1437 | #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 |
| 1438 | #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 |
| 1439 | #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 |
| 1440 | #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 |
| 1441 | #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 |
| 1442 | #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 |
| 1443 | |
| 1444 | /* Led control. */ |
| 1445 | T3_32BIT_REGISTER LedCtrl; |
| 1446 | #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 |
| 1447 | #define LED_CTRL_1000MBPS_LED_ON BIT_1 |
| 1448 | #define LED_CTRL_100MBPS_LED_ON BIT_2 |
| 1449 | #define LED_CTRL_10MBPS_LED_ON BIT_3 |
| 1450 | #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 |
| 1451 | #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 |
| 1452 | #define LED_CTRL_TRAFFIC_LED BIT_6 |
| 1453 | #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 |
| 1454 | #define LED_CTRL_100MBPS_LED_STATUS BIT_8 |
| 1455 | #define LED_CTRL_10MBPS_LED_STATUS BIT_9 |
| 1456 | #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 |
| 1457 | #define LED_CTRL_MAC_MODE BIT_NONE |
| 1458 | #define LED_CTRL_PHY_MODE_1 BIT_11 |
| 1459 | #define LED_CTRL_PHY_MODE_2 BIT_12 |
| 1460 | #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 |
| 1461 | #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 |
| 1462 | #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 |
| 1463 | |
| 1464 | /* MAC addresses. */ |
| 1465 | struct { |
| 1466 | T3_32BIT_REGISTER High; /* Upper 2 bytes. */ |
| 1467 | T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ |
| 1468 | } MacAddr[4]; |
| 1469 | |
| 1470 | /* ACPI Mbuf pointer. */ |
| 1471 | T3_32BIT_REGISTER AcpiMbufPtr; |
| 1472 | |
| 1473 | /* ACPI Length and Offset. */ |
| 1474 | T3_32BIT_REGISTER AcpiLengthOffset; |
| 1475 | #define ACPI_LENGTH_MASK 0xffff |
| 1476 | #define ACPI_OFFSET_MASK 0x0fff0000 |
| 1477 | #define ACPI_LENGTH(x) x |
| 1478 | #define ACPI_OFFSET(x) ((x) << 16) |
| 1479 | |
| 1480 | /* Transmit random backoff. */ |
| 1481 | T3_32BIT_REGISTER TxBackoffSeed; |
| 1482 | #define MAC_TX_BACKOFF_SEED_MASK 0x3ff |
| 1483 | |
| 1484 | /* Receive MTU */ |
| 1485 | T3_32BIT_REGISTER MtuSize; |
| 1486 | #define MAC_RX_MTU_MASK 0xffff |
| 1487 | |
| 1488 | /* Gigabit PCS Test. */ |
| 1489 | T3_32BIT_REGISTER PcsTest; |
| 1490 | #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff |
| 1491 | #define MAC_PCS_TEST_ENABLE BIT_20 |
| 1492 | |
| 1493 | /* Transmit Gigabit Auto-Negotiation. */ |
| 1494 | T3_32BIT_REGISTER TxAutoNeg; |
| 1495 | #define MAC_AN_TX_AN_DATA_MASK 0xffff |
| 1496 | |
| 1497 | /* Receive Gigabit Auto-Negotiation. */ |
| 1498 | T3_32BIT_REGISTER RxAutoNeg; |
| 1499 | #define MAC_AN_RX_AN_DATA_MASK 0xffff |
| 1500 | |
| 1501 | /* MI Communication. */ |
| 1502 | T3_32BIT_REGISTER MiCom; |
| 1503 | #define MI_COM_CMD_MASK (BIT_26 | BIT_27) |
| 1504 | #define MI_COM_CMD_WRITE BIT_26 |
| 1505 | #define MI_COM_CMD_READ BIT_27 |
| 1506 | #define MI_COM_READ_FAILED BIT_28 |
| 1507 | #define MI_COM_START BIT_29 |
| 1508 | #define MI_COM_BUSY BIT_29 |
| 1509 | |
| 1510 | #define MI_COM_PHY_ADDR_MASK 0x1f |
| 1511 | #define MI_COM_FIRST_PHY_ADDR_BIT 21 |
| 1512 | |
| 1513 | #define MI_COM_PHY_REG_ADDR_MASK 0x1f |
| 1514 | #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 |
| 1515 | |
| 1516 | #define MI_COM_PHY_DATA_MASK 0xffff |
| 1517 | |
| 1518 | /* MI Status. */ |
| 1519 | T3_32BIT_REGISTER MiStatus; |
| 1520 | #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 |
| 1521 | |
| 1522 | /* MI Mode. */ |
| 1523 | T3_32BIT_REGISTER MiMode; |
| 1524 | #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 |
| 1525 | #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 |
| 1526 | #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 |
| 1527 | #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 |
| 1528 | |
| 1529 | /* Auto-polling status. */ |
| 1530 | T3_32BIT_REGISTER AutoPollStatus; |
| 1531 | #define AUTO_POLL_ERROR BIT_0 |
| 1532 | |
| 1533 | /* Transmit MAC mode. */ |
| 1534 | T3_32BIT_REGISTER TxMode; |
| 1535 | #define TX_MODE_RESET BIT_0 |
| 1536 | #define TX_MODE_ENABLE BIT_1 |
| 1537 | #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 |
| 1538 | #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 |
| 1539 | #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 |
| 1540 | |
| 1541 | /* Transmit MAC status. */ |
| 1542 | T3_32BIT_REGISTER TxStatus; |
| 1543 | #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 |
| 1544 | #define TX_STATUS_SENT_XOFF BIT_1 |
| 1545 | #define TX_STATUS_SENT_XON BIT_2 |
| 1546 | #define TX_STATUS_LINK_UP BIT_3 |
| 1547 | #define TX_STATUS_ODI_UNDERRUN BIT_4 |
| 1548 | #define TX_STATUS_ODI_OVERRUN BIT_5 |
| 1549 | |
| 1550 | /* Transmit MAC length. */ |
| 1551 | T3_32BIT_REGISTER TxLengths; |
| 1552 | #define TX_LEN_SLOT_TIME_MASK 0xff |
| 1553 | #define TX_LEN_IPG_MASK 0x0f00 |
| 1554 | #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) |
| 1555 | |
| 1556 | /* Receive MAC mode. */ |
| 1557 | T3_32BIT_REGISTER RxMode; |
| 1558 | #define RX_MODE_RESET BIT_0 |
| 1559 | #define RX_MODE_ENABLE BIT_1 |
| 1560 | #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 |
| 1561 | #define RX_MODE_KEEP_MAC_CONTROL BIT_3 |
| 1562 | #define RX_MODE_KEEP_PAUSE BIT_4 |
| 1563 | #define RX_MODE_ACCEPT_OVERSIZED BIT_5 |
| 1564 | #define RX_MODE_ACCEPT_RUNTS BIT_6 |
| 1565 | #define RX_MODE_LENGTH_CHECK BIT_7 |
| 1566 | #define RX_MODE_PROMISCUOUS_MODE BIT_8 |
| 1567 | #define RX_MODE_NO_CRC_CHECK BIT_9 |
| 1568 | #define RX_MODE_KEEP_VLAN_TAG BIT_10 |
| 1569 | |
| 1570 | /* Receive MAC status. */ |
| 1571 | T3_32BIT_REGISTER RxStatus; |
| 1572 | #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 |
| 1573 | #define RX_STATUS_XOFF_RECEIVED BIT_1 |
| 1574 | #define RX_STATUS_XON_RECEIVED BIT_2 |
| 1575 | |
| 1576 | /* Hash registers. */ |
| 1577 | T3_32BIT_REGISTER HashReg[4]; |
| 1578 | |
| 1579 | /* Receive placement rules registers. */ |
| 1580 | struct { |
| 1581 | T3_32BIT_REGISTER Rule; |
| 1582 | T3_32BIT_REGISTER Value; |
| 1583 | } RcvRules[16]; |
| 1584 | |
| 1585 | #define RCV_DISABLE_RULE_MASK 0x7fffffff |
| 1586 | |
| 1587 | #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 |
| 1588 | #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 |
| 1589 | #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff |
| 1590 | |
| 1591 | #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 |
| 1592 | #define REJECT_BROADCAST_RULE2_RULE 0x86000004 |
| 1593 | #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff |
| 1594 | |
| 1595 | #if INCLUDE_5701_AX_FIX |
| 1596 | #define RCV_LAST_RULE_IDX 0x04 |
| 1597 | #else |
| 1598 | #define RCV_LAST_RULE_IDX 0x02 |
| 1599 | #endif |
| 1600 | |
| 1601 | T3_32BIT_REGISTER RcvRuleCfg; |
| 1602 | #define RX_RULE_DEFAULT_CLASS (1 << 3) |
| 1603 | |
| 1604 | LM_UINT8 Reserved1[140]; |
| 1605 | |
| 1606 | T3_32BIT_REGISTER SerdesCfg; |
| 1607 | T3_32BIT_REGISTER SerdesStatus; |
| 1608 | |
| 1609 | LM_UINT8 Reserved2[104]; |
| 1610 | |
| 1611 | volatile LM_UINT8 TxMacState[16]; |
| 1612 | volatile LM_UINT8 RxMacState[20]; |
| 1613 | |
| 1614 | LM_UINT8 Reserved3[476]; |
| 1615 | |
| 1616 | T3_32BIT_REGISTER RxStats[26]; |
| 1617 | |
| 1618 | LM_UINT8 Reserved4[24]; |
| 1619 | |
| 1620 | T3_32BIT_REGISTER TxStats[28]; |
| 1621 | |
| 1622 | LM_UINT8 Reserved5[784]; |
| 1623 | } T3_MAC_CONTROL, *PT3_MAC_CONTROL; |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | /******************************************************************************/ |
| 1628 | /* Send data initiator control registers. */ |
| 1629 | /******************************************************************************/ |
| 1630 | |
| 1631 | typedef struct { |
| 1632 | T3_32BIT_REGISTER Mode; |
| 1633 | #define T3_SND_DATA_IN_MODE_RESET BIT_0 |
| 1634 | #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 |
| 1635 | #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 |
| 1636 | |
| 1637 | T3_32BIT_REGISTER Status; |
| 1638 | #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 |
| 1639 | |
| 1640 | T3_32BIT_REGISTER StatsCtrl; |
| 1641 | #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 |
| 1642 | #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 |
| 1643 | #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 |
| 1644 | #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 |
| 1645 | #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 |
| 1646 | |
| 1647 | T3_32BIT_REGISTER StatsEnableMask; |
| 1648 | T3_32BIT_REGISTER StatsIncMask; |
| 1649 | |
| 1650 | LM_UINT8 Reserved[108]; |
| 1651 | |
| 1652 | T3_32BIT_REGISTER ClassOfServCnt[16]; |
| 1653 | T3_32BIT_REGISTER DmaReadQFullCnt; |
| 1654 | T3_32BIT_REGISTER DmaPriorityReadQFullCnt; |
| 1655 | T3_32BIT_REGISTER SdcQFullCnt; |
| 1656 | |
| 1657 | T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; |
| 1658 | T3_32BIT_REGISTER StatusUpdatedCnt; |
| 1659 | T3_32BIT_REGISTER InterruptsCnt; |
| 1660 | T3_32BIT_REGISTER AvoidInterruptsCnt; |
| 1661 | T3_32BIT_REGISTER SendThresholdHitCnt; |
| 1662 | |
| 1663 | /* Unused space. */ |
| 1664 | LM_UINT8 Unused[800]; |
| 1665 | } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | /******************************************************************************/ |
| 1670 | /* Send data completion control registers. */ |
| 1671 | /******************************************************************************/ |
| 1672 | |
| 1673 | typedef struct { |
| 1674 | T3_32BIT_REGISTER Mode; |
| 1675 | #define SND_DATA_COMP_MODE_RESET BIT_0 |
| 1676 | #define SND_DATA_COMP_MODE_ENABLE BIT_1 |
| 1677 | |
| 1678 | /* Unused space. */ |
| 1679 | LM_UINT8 Unused[1020]; |
| 1680 | } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; |
| 1681 | |
| 1682 | |
| 1683 | |
| 1684 | /******************************************************************************/ |
| 1685 | /* Send BD Ring Selector Control Registers. */ |
| 1686 | /******************************************************************************/ |
| 1687 | |
| 1688 | typedef struct { |
| 1689 | T3_32BIT_REGISTER Mode; |
| 1690 | #define SND_BD_SEL_MODE_RESET BIT_0 |
| 1691 | #define SND_BD_SEL_MODE_ENABLE BIT_1 |
| 1692 | #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 |
| 1693 | |
| 1694 | T3_32BIT_REGISTER Status; |
| 1695 | #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 |
| 1696 | |
| 1697 | T3_32BIT_REGISTER HwDiag; |
| 1698 | |
| 1699 | /* Unused space. */ |
| 1700 | LM_UINT8 Unused1[52]; |
| 1701 | |
| 1702 | /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ |
| 1703 | T3_32BIT_REGISTER NicSendBdSelConIdx[16]; |
| 1704 | |
| 1705 | /* Unused space. */ |
| 1706 | LM_UINT8 Unused2[896]; |
| 1707 | } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | /******************************************************************************/ |
| 1712 | /* Send BD initiator control registers. */ |
| 1713 | /******************************************************************************/ |
| 1714 | |
| 1715 | typedef struct { |
| 1716 | T3_32BIT_REGISTER Mode; |
| 1717 | #define SND_BD_IN_MODE_RESET BIT_0 |
| 1718 | #define SND_BD_IN_MODE_ENABLE BIT_1 |
| 1719 | #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 |
| 1720 | |
| 1721 | T3_32BIT_REGISTER Status; |
| 1722 | #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 |
| 1723 | |
| 1724 | /* Send BD initiator local NIC send BD producer index. */ |
| 1725 | T3_32BIT_REGISTER NicSendBdInProdIdx[16]; |
| 1726 | |
| 1727 | /* Unused space. */ |
| 1728 | LM_UINT8 Unused2[952]; |
| 1729 | } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; |
| 1730 | |
| 1731 | |
| 1732 | |
| 1733 | /******************************************************************************/ |
| 1734 | /* Send BD Completion Control. */ |
| 1735 | /******************************************************************************/ |
| 1736 | |
| 1737 | typedef struct { |
| 1738 | T3_32BIT_REGISTER Mode; |
| 1739 | #define SND_BD_COMP_MODE_RESET BIT_0 |
| 1740 | #define SND_BD_COMP_MODE_ENABLE BIT_1 |
| 1741 | #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 |
| 1742 | |
| 1743 | /* Unused space. */ |
| 1744 | LM_UINT8 Unused2[1020]; |
| 1745 | } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | /******************************************************************************/ |
| 1750 | /* Receive list placement control registers. */ |
| 1751 | /******************************************************************************/ |
| 1752 | |
| 1753 | typedef struct { |
| 1754 | /* Mode. */ |
| 1755 | T3_32BIT_REGISTER Mode; |
| 1756 | #define RCV_LIST_PLMT_MODE_RESET BIT_0 |
| 1757 | #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 |
| 1758 | #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 |
| 1759 | #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 |
| 1760 | #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 |
| 1761 | |
| 1762 | /* Status. */ |
| 1763 | T3_32BIT_REGISTER Status; |
| 1764 | #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 |
| 1765 | #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 |
| 1766 | #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 |
| 1767 | |
| 1768 | /* Receive selector list lock register. */ |
| 1769 | T3_32BIT_REGISTER Lock; |
| 1770 | #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff |
| 1771 | #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 |
| 1772 | |
| 1773 | /* Selector non-empty bits. */ |
| 1774 | T3_32BIT_REGISTER NonEmptyBits; |
| 1775 | #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff |
| 1776 | |
| 1777 | /* Receive list placement configuration register. */ |
| 1778 | T3_32BIT_REGISTER Config; |
| 1779 | |
| 1780 | /* Receive List Placement statistics Control. */ |
| 1781 | T3_32BIT_REGISTER StatsCtrl; |
| 1782 | #define RCV_LIST_STATS_ENABLE BIT_0 |
| 1783 | #define RCV_LIST_STATS_FAST_UPDATE BIT_1 |
| 1784 | |
| 1785 | /* Receive List Placement statistics Enable Mask. */ |
| 1786 | T3_32BIT_REGISTER StatsEnableMask; |
| 1787 | |
| 1788 | /* Receive List Placement statistics Increment Mask. */ |
| 1789 | T3_32BIT_REGISTER StatsIncMask; |
| 1790 | |
| 1791 | /* Unused space. */ |
| 1792 | LM_UINT8 Unused1[224]; |
| 1793 | |
| 1794 | struct { |
| 1795 | T3_32BIT_REGISTER Head; |
| 1796 | T3_32BIT_REGISTER Tail; |
| 1797 | T3_32BIT_REGISTER Count; |
| 1798 | |
| 1799 | /* Unused space. */ |
| 1800 | LM_UINT8 Unused[4]; |
| 1801 | } RcvSelectorList[16]; |
| 1802 | |
| 1803 | /* Local statistics counter. */ |
| 1804 | T3_32BIT_REGISTER ClassOfServCnt[16]; |
| 1805 | |
| 1806 | T3_32BIT_REGISTER DropDueToFilterCnt; |
| 1807 | T3_32BIT_REGISTER DmaWriteQFullCnt; |
| 1808 | T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; |
| 1809 | T3_32BIT_REGISTER NoMoreReceiveBdCnt; |
| 1810 | T3_32BIT_REGISTER IfInDiscardsCnt; |
| 1811 | T3_32BIT_REGISTER IfInErrorsCnt; |
| 1812 | T3_32BIT_REGISTER RcvThresholdHitCnt; |
| 1813 | |
| 1814 | /* Another unused space. */ |
| 1815 | LM_UINT8 Unused2[420]; |
| 1816 | } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; |
| 1817 | |
| 1818 | |
| 1819 | |
| 1820 | /******************************************************************************/ |
| 1821 | /* Receive Data and Receive BD Initiator Control. */ |
| 1822 | /******************************************************************************/ |
| 1823 | |
| 1824 | typedef struct { |
| 1825 | /* Mode. */ |
| 1826 | T3_32BIT_REGISTER Mode; |
| 1827 | #define RCV_DATA_BD_IN_MODE_RESET BIT_0 |
| 1828 | #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 |
| 1829 | #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 |
| 1830 | #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 |
| 1831 | #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 |
| 1832 | |
| 1833 | /* Status. */ |
| 1834 | T3_32BIT_REGISTER Status; |
| 1835 | #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 |
| 1836 | #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 |
| 1837 | #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 |
| 1838 | |
| 1839 | /* Split frame minium size. */ |
| 1840 | T3_32BIT_REGISTER SplitFrameMinSize; |
| 1841 | |
| 1842 | /* Unused space. */ |
| 1843 | LM_UINT8 Unused1[0x2440-0x240c]; |
| 1844 | |
| 1845 | /* Receive RCBs. */ |
| 1846 | T3_RCB JumboRcvRcb; |
| 1847 | T3_RCB StdRcvRcb; |
| 1848 | T3_RCB MiniRcvRcb; |
| 1849 | |
| 1850 | /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ |
| 1851 | /* BD Consumber Index. */ |
| 1852 | T3_32BIT_REGISTER NicJumboConIdx; |
| 1853 | T3_32BIT_REGISTER NicStdConIdx; |
| 1854 | T3_32BIT_REGISTER NicMiniConIdx; |
| 1855 | |
| 1856 | /* Unused space. */ |
| 1857 | LM_UINT8 Unused2[4]; |
| 1858 | |
| 1859 | /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ |
| 1860 | T3_32BIT_REGISTER RcvDataBdProdIdx[16]; |
| 1861 | |
| 1862 | /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ |
| 1863 | T3_32BIT_REGISTER HwDiag; |
| 1864 | |
| 1865 | /* Unused space. */ |
| 1866 | LM_UINT8 Unused3[828]; |
| 1867 | } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; |
| 1868 | |
| 1869 | |
| 1870 | |
| 1871 | /******************************************************************************/ |
| 1872 | /* Receive Data Completion Control Registes. */ |
| 1873 | /******************************************************************************/ |
| 1874 | |
| 1875 | typedef struct { |
| 1876 | T3_32BIT_REGISTER Mode; |
| 1877 | #define RCV_DATA_COMP_MODE_RESET BIT_0 |
| 1878 | #define RCV_DATA_COMP_MODE_ENABLE BIT_1 |
| 1879 | #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 |
| 1880 | |
| 1881 | /* Unused spaced. */ |
| 1882 | LM_UINT8 Unused[1020]; |
| 1883 | } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | /******************************************************************************/ |
| 1888 | /* Receive BD Initiator Control. */ |
| 1889 | /******************************************************************************/ |
| 1890 | |
| 1891 | typedef struct { |
| 1892 | T3_32BIT_REGISTER Mode; |
| 1893 | #define RCV_BD_IN_MODE_RESET BIT_0 |
| 1894 | #define RCV_BD_IN_MODE_ENABLE BIT_1 |
| 1895 | #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 |
| 1896 | |
| 1897 | T3_32BIT_REGISTER Status; |
| 1898 | #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 |
| 1899 | |
| 1900 | T3_32BIT_REGISTER NicJumboRcvProdIdx; |
| 1901 | T3_32BIT_REGISTER NicStdRcvProdIdx; |
| 1902 | T3_32BIT_REGISTER NicMiniRcvProdIdx; |
| 1903 | |
| 1904 | T3_32BIT_REGISTER MiniRcvThreshold; |
| 1905 | T3_32BIT_REGISTER StdRcvThreshold; |
| 1906 | T3_32BIT_REGISTER JumboRcvThreshold; |
| 1907 | |
| 1908 | /* Unused space. */ |
| 1909 | LM_UINT8 Unused[992]; |
| 1910 | } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | /******************************************************************************/ |
| 1915 | /* Receive BD Completion Control Registers. */ |
| 1916 | /******************************************************************************/ |
| 1917 | |
| 1918 | typedef struct { |
| 1919 | T3_32BIT_REGISTER Mode; |
| 1920 | #define RCV_BD_COMP_MODE_RESET BIT_0 |
| 1921 | #define RCV_BD_COMP_MODE_ENABLE BIT_1 |
| 1922 | #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 |
| 1923 | |
| 1924 | T3_32BIT_REGISTER Status; |
| 1925 | #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 |
| 1926 | |
| 1927 | T3_32BIT_REGISTER NicJumboRcvBdProdIdx; |
| 1928 | T3_32BIT_REGISTER NicStdRcvBdProdIdx; |
| 1929 | T3_32BIT_REGISTER NicMiniRcvBdProdIdx; |
| 1930 | |
| 1931 | /* Unused space. */ |
| 1932 | LM_UINT8 Unused[1004]; |
| 1933 | } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | /******************************************************************************/ |
| 1938 | /* Receive list selector control register. */ |
| 1939 | /******************************************************************************/ |
| 1940 | |
| 1941 | typedef struct { |
| 1942 | T3_32BIT_REGISTER Mode; |
| 1943 | #define RCV_LIST_SEL_MODE_RESET BIT_0 |
| 1944 | #define RCV_LIST_SEL_MODE_ENABLE BIT_1 |
| 1945 | #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 |
| 1946 | |
| 1947 | T3_32BIT_REGISTER Status; |
| 1948 | #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 |
| 1949 | |
| 1950 | /* Unused space. */ |
| 1951 | LM_UINT8 Unused[1016]; |
| 1952 | } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | /******************************************************************************/ |
| 1957 | /* Mbuf cluster free registers. */ |
| 1958 | /******************************************************************************/ |
| 1959 | |
| 1960 | typedef struct { |
| 1961 | T3_32BIT_REGISTER Mode; |
| 1962 | #define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 |
| 1963 | #define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 |
| 1964 | |
| 1965 | T3_32BIT_REGISTER Status; |
| 1966 | |
| 1967 | /* Unused space. */ |
| 1968 | LM_UINT8 Unused[1016]; |
| 1969 | } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; |
| 1970 | |
| 1971 | |
| 1972 | |
| 1973 | /******************************************************************************/ |
| 1974 | /* Host coalescing control registers. */ |
| 1975 | /******************************************************************************/ |
| 1976 | |
| 1977 | typedef struct { |
| 1978 | /* Mode. */ |
| 1979 | T3_32BIT_REGISTER Mode; |
| 1980 | #define HOST_COALESCE_RESET BIT_0 |
| 1981 | #define HOST_COALESCE_ENABLE BIT_1 |
| 1982 | #define HOST_COALESCE_ATTN BIT_2 |
| 1983 | #define HOST_COALESCE_NOW BIT_3 |
| 1984 | #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE |
| 1985 | #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 |
| 1986 | #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 |
| 1987 | #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 |
| 1988 | #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 |
| 1989 | #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 |
| 1990 | #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 |
| 1991 | |
| 1992 | /* Status. */ |
| 1993 | T3_32BIT_REGISTER Status; |
| 1994 | #define HOST_COALESCE_ERROR_ATTN BIT_2 |
| 1995 | |
| 1996 | /* Receive coalescing ticks. */ |
| 1997 | T3_32BIT_REGISTER RxCoalescingTicks; |
| 1998 | |
| 1999 | /* Send coalescing ticks. */ |
| 2000 | T3_32BIT_REGISTER TxCoalescingTicks; |
| 2001 | |
| 2002 | /* Receive max coalesced frames. */ |
| 2003 | T3_32BIT_REGISTER RxMaxCoalescedFrames; |
| 2004 | |
| 2005 | /* Send max coalesced frames. */ |
| 2006 | T3_32BIT_REGISTER TxMaxCoalescedFrames; |
| 2007 | |
| 2008 | /* Receive coalescing ticks during interrupt. */ |
| 2009 | T3_32BIT_REGISTER RxCoalescedTickDuringInt; |
| 2010 | |
| 2011 | /* Send coalescing ticks during interrupt. */ |
| 2012 | T3_32BIT_REGISTER TxCoalescedTickDuringInt; |
| 2013 | |
| 2014 | /* Receive max coalesced frames during interrupt. */ |
| 2015 | T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; |
| 2016 | |
| 2017 | /* Send max coalesced frames during interrupt. */ |
| 2018 | T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; |
| 2019 | |
| 2020 | /* Statistics tick. */ |
| 2021 | T3_32BIT_REGISTER StatsCoalescingTicks; |
| 2022 | |
| 2023 | /* Unused space. */ |
| 2024 | LM_UINT8 Unused2[4]; |
| 2025 | |
| 2026 | /* Statistics host address. */ |
| 2027 | T3_64BIT_REGISTER StatsBlkHostAddr; |
| 2028 | |
| 2029 | /* Status block host address.*/ |
| 2030 | T3_64BIT_REGISTER StatusBlkHostAddr; |
| 2031 | |
| 2032 | /* Statistics NIC address. */ |
| 2033 | T3_32BIT_REGISTER StatsBlkNicAddr; |
| 2034 | |
| 2035 | /* Statust block NIC address. */ |
| 2036 | T3_32BIT_REGISTER StatusBlkNicAddr; |
| 2037 | |
| 2038 | /* Flow attention registers. */ |
| 2039 | T3_32BIT_REGISTER FlowAttn; |
| 2040 | |
| 2041 | /* Unused space. */ |
| 2042 | LM_UINT8 Unused3[4]; |
| 2043 | |
| 2044 | T3_32BIT_REGISTER NicJumboRcvBdConIdx; |
| 2045 | T3_32BIT_REGISTER NicStdRcvBdConIdx; |
| 2046 | T3_32BIT_REGISTER NicMiniRcvBdConIdx; |
| 2047 | |
| 2048 | /* Unused space. */ |
| 2049 | LM_UINT8 Unused4[36]; |
| 2050 | |
| 2051 | T3_32BIT_REGISTER NicRetProdIdx[16]; |
| 2052 | T3_32BIT_REGISTER NicSndBdConIdx[16]; |
| 2053 | |
| 2054 | /* Unused space. */ |
| 2055 | LM_UINT8 Unused5[768]; |
| 2056 | } T3_HOST_COALESCING, *PT3_HOST_COALESCING; |
| 2057 | |
| 2058 | |
| 2059 | |
| 2060 | /******************************************************************************/ |
| 2061 | /* Memory arbiter registers. */ |
| 2062 | /******************************************************************************/ |
| 2063 | |
| 2064 | typedef struct { |
| 2065 | T3_32BIT_REGISTER Mode; |
| 2066 | #define T3_MEM_ARBITER_MODE_RESET BIT_0 |
| 2067 | #define T3_MEM_ARBITER_MODE_ENABLE BIT_1 |
| 2068 | |
| 2069 | T3_32BIT_REGISTER Status; |
| 2070 | |
| 2071 | T3_32BIT_REGISTER ArbTrapAddrLow; |
| 2072 | T3_32BIT_REGISTER ArbTrapAddrHigh; |
| 2073 | |
| 2074 | /* Unused space. */ |
| 2075 | LM_UINT8 Unused[1008]; |
| 2076 | } T3_MEM_ARBITER, *PT3_MEM_ARBITER; |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | /******************************************************************************/ |
| 2081 | /* Buffer manager control register. */ |
| 2082 | /******************************************************************************/ |
| 2083 | |
| 2084 | typedef struct { |
| 2085 | T3_32BIT_REGISTER Mode; |
| 2086 | #define BUFMGR_MODE_RESET BIT_0 |
| 2087 | #define BUFMGR_MODE_ENABLE BIT_1 |
| 2088 | #define BUFMGR_MODE_ATTN_ENABLE BIT_2 |
| 2089 | #define BUFMGR_MODE_BM_TEST BIT_3 |
| 2090 | #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 |
| 2091 | |
| 2092 | T3_32BIT_REGISTER Status; |
| 2093 | #define BUFMGR_STATUS_ERROR BIT_2 |
| 2094 | #define BUFMGR_STATUS_MBUF_LOW BIT_4 |
| 2095 | |
| 2096 | T3_32BIT_REGISTER MbufPoolAddr; |
| 2097 | T3_32BIT_REGISTER MbufPoolSize; |
| 2098 | T3_32BIT_REGISTER MbufReadDmaLowWaterMark; |
| 2099 | T3_32BIT_REGISTER MbufMacRxLowWaterMark; |
| 2100 | T3_32BIT_REGISTER MbufHighWaterMark; |
| 2101 | |
| 2102 | T3_32BIT_REGISTER RxCpuMbufAllocReq; |
| 2103 | #define BUFMGR_MBUF_ALLOC_BIT BIT_31 |
| 2104 | T3_32BIT_REGISTER RxCpuMbufAllocResp; |
| 2105 | T3_32BIT_REGISTER TxCpuMbufAllocReq; |
| 2106 | T3_32BIT_REGISTER TxCpuMbufAllocResp; |
| 2107 | |
| 2108 | T3_32BIT_REGISTER DmaDescPoolAddr; |
| 2109 | T3_32BIT_REGISTER DmaDescPoolSize; |
| 2110 | T3_32BIT_REGISTER DmaLowWaterMark; |
| 2111 | T3_32BIT_REGISTER DmaHighWaterMark; |
| 2112 | |
| 2113 | T3_32BIT_REGISTER RxCpuDmaAllocReq; |
| 2114 | T3_32BIT_REGISTER RxCpuDmaAllocResp; |
| 2115 | T3_32BIT_REGISTER TxCpuDmaAllocReq; |
| 2116 | T3_32BIT_REGISTER TxCpuDmaAllocResp; |
| 2117 | |
| 2118 | T3_32BIT_REGISTER Hwdiag[3]; |
| 2119 | |
| 2120 | /* Unused space. */ |
| 2121 | LM_UINT8 Unused[936]; |
| 2122 | } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | /******************************************************************************/ |
| 2127 | /* Read DMA control registers. */ |
| 2128 | /******************************************************************************/ |
| 2129 | |
| 2130 | typedef struct { |
| 2131 | T3_32BIT_REGISTER Mode; |
| 2132 | #define DMA_READ_MODE_RESET BIT_0 |
| 2133 | #define DMA_READ_MODE_ENABLE BIT_1 |
| 2134 | #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 |
| 2135 | #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 |
| 2136 | #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 |
| 2137 | #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 |
| 2138 | #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 |
| 2139 | #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 |
| 2140 | #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 |
| 2141 | #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 |
| 2142 | #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 |
| 2143 | #define DMA_READ_MODE_SPLIT_RESET BIT_12 |
| 2144 | |
| 2145 | T3_32BIT_REGISTER Status; |
| 2146 | #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 |
| 2147 | #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 |
| 2148 | #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 |
| 2149 | #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 |
| 2150 | #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 |
| 2151 | #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 |
| 2152 | #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 |
| 2153 | #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 |
| 2154 | |
| 2155 | /* Unused space. */ |
| 2156 | LM_UINT8 Unused[1016]; |
| 2157 | } T3_DMA_READ, *PT3_DMA_READ; |
| 2158 | |
| 2159 | typedef union T3_CPU |
| 2160 | { |
| 2161 | struct |
| 2162 | { |
| 2163 | T3_32BIT_REGISTER mode; |
| 2164 | #define CPU_MODE_HALT BIT_10 |
| 2165 | #define CPU_MODE_RESET BIT_0 |
| 2166 | T3_32BIT_REGISTER state; |
| 2167 | T3_32BIT_REGISTER EventMask; |
| 2168 | T3_32BIT_REGISTER reserved1[4]; |
| 2169 | T3_32BIT_REGISTER PC; |
| 2170 | T3_32BIT_REGISTER Instruction; |
| 2171 | T3_32BIT_REGISTER SpadUnderflow; |
| 2172 | T3_32BIT_REGISTER WatchdogClear; |
| 2173 | T3_32BIT_REGISTER WatchdogVector; |
| 2174 | T3_32BIT_REGISTER WatchdogSavedPC; |
| 2175 | T3_32BIT_REGISTER HardwareBp; |
| 2176 | T3_32BIT_REGISTER reserved2[3]; |
| 2177 | T3_32BIT_REGISTER WatchdogSavedState; |
| 2178 | T3_32BIT_REGISTER LastBrchAddr; |
| 2179 | T3_32BIT_REGISTER SpadUnderflowSet; |
| 2180 | T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; |
| 2181 | T3_32BIT_REGISTER Regs[32]; |
| 2182 | T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; |
| 2183 | }reg; |
| 2184 | }T3_CPU, *PT3_CPU; |
| 2185 | |
| 2186 | /******************************************************************************/ |
| 2187 | /* Write DMA control registers. */ |
| 2188 | /******************************************************************************/ |
| 2189 | |
| 2190 | typedef struct { |
| 2191 | T3_32BIT_REGISTER Mode; |
| 2192 | #define DMA_WRITE_MODE_RESET BIT_0 |
| 2193 | #define DMA_WRITE_MODE_ENABLE BIT_1 |
| 2194 | #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 |
| 2195 | #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 |
| 2196 | #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 |
| 2197 | #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 |
| 2198 | #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 |
| 2199 | #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 |
| 2200 | #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 |
| 2201 | #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 |
| 2202 | |
| 2203 | T3_32BIT_REGISTER Status; |
| 2204 | #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 |
| 2205 | #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 |
| 2206 | #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 |
| 2207 | #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 |
| 2208 | #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 |
| 2209 | #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 |
| 2210 | #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 |
| 2211 | #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 |
| 2212 | |
| 2213 | /* Unused space. */ |
| 2214 | LM_UINT8 Unused[1016]; |
| 2215 | } T3_DMA_WRITE, *PT3_DMA_WRITE; |
| 2216 | |
| 2217 | |
| 2218 | |
| 2219 | /******************************************************************************/ |
| 2220 | /* Mailbox registers. */ |
| 2221 | /******************************************************************************/ |
| 2222 | |
| 2223 | typedef struct { |
| 2224 | /* Interrupt mailbox registers. */ |
| 2225 | T3_64BIT_REGISTER Interrupt[4]; |
| 2226 | |
| 2227 | /* General mailbox registers. */ |
| 2228 | T3_64BIT_REGISTER General[8]; |
| 2229 | |
| 2230 | /* Reload statistics mailbox. */ |
| 2231 | T3_64BIT_REGISTER ReloadStat; |
| 2232 | |
| 2233 | /* Receive BD ring producer index registers. */ |
| 2234 | T3_64BIT_REGISTER RcvStdProdIdx; |
| 2235 | T3_64BIT_REGISTER RcvJumboProdIdx; |
| 2236 | T3_64BIT_REGISTER RcvMiniProdIdx; |
| 2237 | |
| 2238 | /* Receive return ring consumer index registers. */ |
| 2239 | T3_64BIT_REGISTER RcvRetConIdx[16]; |
| 2240 | |
| 2241 | /* Send BD ring host producer index registers. */ |
| 2242 | T3_64BIT_REGISTER SendHostProdIdx[16]; |
| 2243 | |
| 2244 | /* Send BD ring nic producer index registers. */ |
| 2245 | T3_64BIT_REGISTER SendNicProdIdx[16]; |
| 2246 | }T3_MAILBOX, *PT3_MAILBOX; |
| 2247 | |
| 2248 | typedef struct { |
| 2249 | T3_MAILBOX Mailbox; |
| 2250 | |
| 2251 | /* Priority mailbox registers. */ |
| 2252 | T3_32BIT_REGISTER HighPriorityEventVector; |
| 2253 | T3_32BIT_REGISTER HighPriorityEventMask; |
| 2254 | T3_32BIT_REGISTER LowPriorityEventVector; |
| 2255 | T3_32BIT_REGISTER LowPriorityEventMask; |
| 2256 | |
| 2257 | /* Unused space. */ |
| 2258 | LM_UINT8 Unused[496]; |
| 2259 | } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; |
| 2260 | |
| 2261 | |
| 2262 | /******************************************************************************/ |
| 2263 | /* Flow through queues. */ |
| 2264 | /******************************************************************************/ |
| 2265 | |
| 2266 | typedef struct { |
| 2267 | T3_32BIT_REGISTER Reset; |
| 2268 | |
| 2269 | LM_UINT8 Unused[12]; |
| 2270 | |
| 2271 | T3_32BIT_REGISTER DmaNormalReadFtqCtrl; |
| 2272 | T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; |
| 2273 | T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; |
| 2274 | T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; |
| 2275 | |
| 2276 | T3_32BIT_REGISTER DmaHighReadFtqCtrl; |
| 2277 | T3_32BIT_REGISTER DmaHighReadFtqFullCnt; |
| 2278 | T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; |
| 2279 | T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; |
| 2280 | |
| 2281 | T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; |
| 2282 | T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; |
| 2283 | T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; |
| 2284 | T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; |
| 2285 | |
| 2286 | T3_32BIT_REGISTER SendBdCompFtqCtrl; |
| 2287 | T3_32BIT_REGISTER SendBdCompFtqFullCnt; |
| 2288 | T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; |
| 2289 | T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; |
| 2290 | |
| 2291 | T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; |
| 2292 | T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; |
| 2293 | T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; |
| 2294 | T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; |
| 2295 | |
| 2296 | T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; |
| 2297 | T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; |
| 2298 | T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; |
| 2299 | T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; |
| 2300 | |
| 2301 | T3_32BIT_REGISTER DmaHighWriteFtqCtrl; |
| 2302 | T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; |
| 2303 | T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; |
| 2304 | T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; |
| 2305 | |
| 2306 | T3_32BIT_REGISTER SwType1FtqCtrl; |
| 2307 | T3_32BIT_REGISTER SwType1FtqFullCnt; |
| 2308 | T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; |
| 2309 | T3_32BIT_REGISTER SwType1FtqFifoWritePeek; |
| 2310 | |
| 2311 | T3_32BIT_REGISTER SendDataCompFtqCtrl; |
| 2312 | T3_32BIT_REGISTER SendDataCompFtqFullCnt; |
| 2313 | T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; |
| 2314 | T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; |
| 2315 | |
| 2316 | T3_32BIT_REGISTER HostCoalesceFtqCtrl; |
| 2317 | T3_32BIT_REGISTER HostCoalesceFtqFullCnt; |
| 2318 | T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; |
| 2319 | T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; |
| 2320 | |
| 2321 | T3_32BIT_REGISTER MacTxFtqCtrl; |
| 2322 | T3_32BIT_REGISTER MacTxFtqFullCnt; |
| 2323 | T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; |
| 2324 | T3_32BIT_REGISTER MacTxFtqFifoWritePeek; |
| 2325 | |
| 2326 | T3_32BIT_REGISTER MbufClustFreeFtqCtrl; |
| 2327 | T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; |
| 2328 | T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; |
| 2329 | T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; |
| 2330 | |
| 2331 | T3_32BIT_REGISTER RcvBdCompFtqCtrl; |
| 2332 | T3_32BIT_REGISTER RcvBdCompFtqFullCnt; |
| 2333 | T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; |
| 2334 | T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; |
| 2335 | |
| 2336 | T3_32BIT_REGISTER RcvListPlmtFtqCtrl; |
| 2337 | T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; |
| 2338 | T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; |
| 2339 | T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; |
| 2340 | |
| 2341 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; |
| 2342 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; |
| 2343 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; |
| 2344 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; |
| 2345 | |
| 2346 | T3_32BIT_REGISTER RcvDataCompFtqCtrl; |
| 2347 | T3_32BIT_REGISTER RcvDataCompFtqFullCnt; |
| 2348 | T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; |
| 2349 | T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; |
| 2350 | |
| 2351 | T3_32BIT_REGISTER SwType2FtqCtrl; |
| 2352 | T3_32BIT_REGISTER SwType2FtqFullCnt; |
| 2353 | T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; |
| 2354 | T3_32BIT_REGISTER SwType2FtqFifoWritePeek; |
| 2355 | |
| 2356 | /* Unused space. */ |
| 2357 | LM_UINT8 Unused2[736]; |
| 2358 | } T3_FTQ, *PT3_FTQ; |
| 2359 | |
| 2360 | |
| 2361 | |
| 2362 | /******************************************************************************/ |
| 2363 | /* Message signaled interrupt registers. */ |
| 2364 | /******************************************************************************/ |
| 2365 | |
| 2366 | typedef struct { |
| 2367 | T3_32BIT_REGISTER Mode; |
| 2368 | #define MSI_MODE_RESET BIT_0 |
| 2369 | #define MSI_MODE_ENABLE BIT_1 |
| 2370 | T3_32BIT_REGISTER Status; |
| 2371 | |
| 2372 | T3_32BIT_REGISTER MsiFifoAccess; |
| 2373 | |
| 2374 | /* Unused space. */ |
| 2375 | LM_UINT8 Unused[1012]; |
| 2376 | } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; |
| 2377 | |
| 2378 | |
| 2379 | |
| 2380 | /******************************************************************************/ |
| 2381 | /* DMA Completion registes. */ |
| 2382 | /******************************************************************************/ |
| 2383 | |
| 2384 | typedef struct { |
| 2385 | T3_32BIT_REGISTER Mode; |
| 2386 | #define DMA_COMP_MODE_RESET BIT_0 |
| 2387 | #define DMA_COMP_MODE_ENABLE BIT_1 |
| 2388 | |
| 2389 | /* Unused space. */ |
| 2390 | LM_UINT8 Unused[1020]; |
| 2391 | } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; |
| 2392 | |
| 2393 | |
| 2394 | |
| 2395 | /******************************************************************************/ |
| 2396 | /* GRC registers. */ |
| 2397 | /******************************************************************************/ |
| 2398 | |
| 2399 | typedef struct { |
| 2400 | /* Mode control register. */ |
| 2401 | T3_32BIT_REGISTER Mode; |
| 2402 | #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 |
| 2403 | #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 |
| 2404 | #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 |
| 2405 | #define GRC_MODE_BYTE_SWAP_DATA BIT_4 |
| 2406 | #define GRC_MODE_WORD_SWAP_DATA BIT_5 |
| 2407 | #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 |
| 2408 | #define GRC_MODE_NO_FRAME_CRACKING BIT_9 |
| 2409 | #define GRC_MODE_INCLUDE_CRC BIT_10 |
| 2410 | #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 |
| 2411 | #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 |
| 2412 | #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 |
| 2413 | #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 |
| 2414 | #define GRC_MODE_HOST_STACK_UP BIT_16 |
| 2415 | #define GRC_MODE_HOST_SEND_BDS BIT_17 |
| 2416 | #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 |
| 2417 | #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 |
| 2418 | #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 |
| 2419 | #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 |
| 2420 | #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 |
| 2421 | #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 |
| 2422 | #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 |
| 2423 | #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 |
| 2424 | #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 |
| 2425 | |
| 2426 | /* Misc configuration register. */ |
| 2427 | T3_32BIT_REGISTER MiscCfg; |
| 2428 | #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 |
| 2429 | #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe |
| 2430 | #define GRC_MISC_BD_ID_MASK 0x0001e000 |
| 2431 | #define GRC_MISC_BD_ID_5700 0x0001e000 |
| 2432 | #define GRC_MISC_BD_ID_5701 0x00000000 |
| 2433 | #define GRC_MISC_BD_ID_5703 0x00000000 |
| 2434 | #define GRC_MISC_BD_ID_5703S 0x00002000 |
| 2435 | #define GRC_MISC_BD_ID_5702FE 0x00004000 |
| 2436 | #define GRC_MISC_BD_ID_5704 0x00000000 |
| 2437 | #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 |
| 2438 | |
| 2439 | /* Miscellaneous local control register. */ |
| 2440 | T3_32BIT_REGISTER LocalCtrl; |
| 2441 | #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 |
| 2442 | #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 |
| 2443 | #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 |
| 2444 | #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 |
| 2445 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 |
| 2446 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 |
| 2447 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 |
| 2448 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 |
| 2449 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 |
| 2450 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 |
| 2451 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 |
| 2452 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 |
| 2453 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 |
| 2454 | #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 |
| 2455 | #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 |
| 2456 | #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 |
| 2457 | |
| 2458 | #define GRC_MISC_MEMSIZE_256K 0 |
| 2459 | #define GRC_MISC_MEMSIZE_512K (1 << 18) |
| 2460 | #define GRC_MISC_MEMSIZE_1024K (2 << 18) |
| 2461 | #define GRC_MISC_MEMSIZE_2048K (3 << 18) |
| 2462 | #define GRC_MISC_MEMSIZE_4096K (4 << 18) |
| 2463 | #define GRC_MISC_MEMSIZE_8192K (5 << 18) |
| 2464 | #define GRC_MISC_MEMSIZE_16M (6 << 18) |
| 2465 | #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 |
| 2466 | |
| 2467 | |
| 2468 | T3_32BIT_REGISTER Timer; |
| 2469 | |
| 2470 | T3_32BIT_REGISTER RxCpuEvent; |
| 2471 | T3_32BIT_REGISTER RxTimerRef; |
| 2472 | T3_32BIT_REGISTER RxCpuSemaphore; |
| 2473 | T3_32BIT_REGISTER RemoteRxCpuAttn; |
| 2474 | |
| 2475 | T3_32BIT_REGISTER TxCpuEvent; |
| 2476 | T3_32BIT_REGISTER TxTimerRef; |
| 2477 | T3_32BIT_REGISTER TxCpuSemaphore; |
| 2478 | T3_32BIT_REGISTER RemoteTxCpuAttn; |
| 2479 | |
| 2480 | T3_64BIT_REGISTER MemoryPowerUp; |
| 2481 | |
| 2482 | T3_32BIT_REGISTER EepromAddr; |
| 2483 | #define SEEPROM_ADDR_WRITE 0 |
| 2484 | #define SEEPROM_ADDR_READ (1 << 31) |
| 2485 | #define SEEPROM_ADDR_RW_MASK 0x80000000 |
| 2486 | #define SEEPROM_ADDR_COMPLETE (1 << 30) |
| 2487 | #define SEEPROM_ADDR_FSM_RESET (1 << 29) |
| 2488 | #define SEEPROM_ADDR_DEV_ID(x) (x << 26) |
| 2489 | #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 |
| 2490 | #define SEEPROM_ADDR_START (1 << 25) |
| 2491 | #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) |
| 2492 | #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) |
| 2493 | #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff |
| 2494 | |
| 2495 | #define SEEPROM_CLOCK_PERIOD 60 |
| 2496 | #define SEEPROM_CHIP_SIZE (64 * 1024) |
| 2497 | |
| 2498 | T3_32BIT_REGISTER EepromData; |
| 2499 | T3_32BIT_REGISTER EepromCtrl; |
| 2500 | |
| 2501 | T3_32BIT_REGISTER MdiCtrl; |
| 2502 | T3_32BIT_REGISTER SepromDelay; |
| 2503 | |
| 2504 | /* Unused space. */ |
| 2505 | LM_UINT8 Unused[948]; |
| 2506 | } T3_GRC, *PT3_GRC; |
| 2507 | |
| 2508 | |
| 2509 | /******************************************************************************/ |
| 2510 | /* NVRAM control registers. */ |
| 2511 | /******************************************************************************/ |
| 2512 | |
| 2513 | typedef struct |
| 2514 | { |
| 2515 | T3_32BIT_REGISTER Cmd; |
| 2516 | #define NVRAM_CMD_RESET BIT_0 |
| 2517 | #define NVRAM_CMD_DONE BIT_3 |
| 2518 | #define NVRAM_CMD_DO_IT BIT_4 |
| 2519 | #define NVRAM_CMD_WR BIT_5 |
| 2520 | #define NVRAM_CMD_RD BIT_NONE |
| 2521 | #define NVRAM_CMD_ERASE BIT_6 |
| 2522 | #define NVRAM_CMD_FIRST BIT_7 |
| 2523 | #define NVRAM_CMD_LAST BIT_8 |
| 2524 | |
| 2525 | T3_32BIT_REGISTER Status; |
| 2526 | T3_32BIT_REGISTER WriteData; |
| 2527 | |
| 2528 | T3_32BIT_REGISTER Addr; |
| 2529 | #define NVRAM_ADDRESS_MASK 0xffffff |
| 2530 | |
| 2531 | T3_32BIT_REGISTER ReadData; |
| 2532 | |
| 2533 | /* Flash config 1 register. */ |
| 2534 | T3_32BIT_REGISTER Config1; |
| 2535 | #define FLASH_INTERFACE_ENABLE BIT_0 |
| 2536 | #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 |
| 2537 | #define FLASH_PASS_THRU_MODE BIT_2 |
| 2538 | #define FLASH_BIT_BANG_MODE BIT_3 |
| 2539 | #define FLASH_COMPAT_BYPASS BIT_31 |
| 2540 | |
| 2541 | /* Buffered flash (Atmel: AT45DB011B) specific information */ |
| 2542 | #define BUFFERED_FLASH_PAGE_POS 9 |
| 2543 | #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1) |
| 2544 | #define BUFFERED_FLASH_PAGE_SIZE 264 |
| 2545 | #define BUFFERED_FLASH_PHY_PAGE_SIZE 512 |
| 2546 | |
| 2547 | T3_32BIT_REGISTER Config2; |
| 2548 | T3_32BIT_REGISTER Config3; |
| 2549 | T3_32BIT_REGISTER SwArb; |
| 2550 | #define SW_ARB_REQ_SET0 BIT_0 |
| 2551 | #define SW_ARB_REQ_SET1 BIT_1 |
| 2552 | #define SW_ARB_REQ_SET2 BIT_2 |
| 2553 | #define SW_ARB_REQ_SET3 BIT_3 |
| 2554 | #define SW_ARB_REQ_CLR0 BIT_4 |
| 2555 | #define SW_ARB_REQ_CLR1 BIT_5 |
| 2556 | #define SW_ARB_REQ_CLR2 BIT_6 |
| 2557 | #define SW_ARB_REQ_CLR3 BIT_7 |
| 2558 | #define SW_ARB_GNT0 BIT_8 |
| 2559 | #define SW_ARB_GNT1 BIT_9 |
| 2560 | #define SW_ARB_GNT2 BIT_10 |
| 2561 | #define SW_ARB_GNT3 BIT_11 |
| 2562 | #define SW_ARB_REQ0 BIT_12 |
| 2563 | #define SW_ARB_REQ1 BIT_13 |
| 2564 | #define SW_ARB_REQ2 BIT_14 |
| 2565 | #define SW_ARB_REQ3 BIT_15 |
| 2566 | |
| 2567 | /* Unused space. */ |
| 2568 | LM_UINT8 Unused[988]; |
| 2569 | } T3_NVRAM, *PT3_NVRAM; |
| 2570 | |
| 2571 | |
| 2572 | /******************************************************************************/ |
| 2573 | /* NIC's internal memory. */ |
| 2574 | /******************************************************************************/ |
| 2575 | |
| 2576 | typedef struct { |
| 2577 | /* Page zero for the internal CPUs. */ |
| 2578 | LM_UINT8 PageZero[0x100]; /* 0x0000 */ |
| 2579 | |
| 2580 | /* Send RCBs. */ |
| 2581 | T3_RCB SendRcb[16]; /* 0x0100 */ |
| 2582 | |
| 2583 | /* Receive Return RCBs. */ |
| 2584 | T3_RCB RcvRetRcb[16]; /* 0x0200 */ |
| 2585 | |
| 2586 | /* Statistics block. */ |
| 2587 | T3_STATS_BLOCK StatsBlk; /* 0x0300 */ |
| 2588 | |
| 2589 | /* Status block. */ |
| 2590 | T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */ |
| 2591 | |
| 2592 | /* Reserved for software. */ |
| 2593 | LM_UINT8 Reserved[1200]; /* 0x0b50 */ |
| 2594 | |
| 2595 | /* Unmapped region. */ |
| 2596 | LM_UINT8 Unmapped[4096]; /* 0x1000 */ |
| 2597 | |
| 2598 | /* DMA descriptors. */ |
| 2599 | LM_UINT8 DmaDesc[8192]; /* 0x2000 */ |
| 2600 | |
| 2601 | /* Buffer descriptors. */ |
| 2602 | LM_UINT8 BufferDesc[16384]; /* 0x4000 */ |
| 2603 | } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM; |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | /******************************************************************************/ |
| 2608 | /* Memory layout. */ |
| 2609 | /******************************************************************************/ |
| 2610 | |
| 2611 | typedef struct { |
| 2612 | /* PCI configuration registers. */ |
| 2613 | T3_PCI_CONFIGURATION PciCfg; |
| 2614 | |
| 2615 | /* Unused. */ |
| 2616 | LM_UINT8 Unused1[0x100]; /* 0x0100 */ |
| 2617 | |
| 2618 | /* Mailbox . */ |
| 2619 | T3_MAILBOX Mailbox; /* 0x0200 */ |
| 2620 | |
| 2621 | /* MAC control registers. */ |
| 2622 | T3_MAC_CONTROL MacCtrl; /* 0x0400 */ |
| 2623 | |
| 2624 | /* Send data initiator control registers. */ |
| 2625 | T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */ |
| 2626 | |
| 2627 | /* Send data completion Control registers. */ |
| 2628 | T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */ |
| 2629 | |
| 2630 | /* Send BD ring selector. */ |
| 2631 | T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */ |
| 2632 | |
| 2633 | /* Send BD initiator control registers. */ |
| 2634 | T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */ |
| 2635 | |
| 2636 | /* Send BD completion control registers. */ |
| 2637 | T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */ |
| 2638 | |
| 2639 | /* Receive list placement control registers. */ |
| 2640 | T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */ |
| 2641 | |
| 2642 | /* Receive Data and Receive BD Initiator Control. */ |
| 2643 | T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */ |
| 2644 | |
| 2645 | /* Receive Data Completion Control */ |
| 2646 | T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */ |
| 2647 | |
| 2648 | /* Receive BD Initiator Control Registers. */ |
| 2649 | T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */ |
| 2650 | |
| 2651 | /* Receive BD Completion Control Registers. */ |
| 2652 | T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */ |
| 2653 | |
| 2654 | /* Receive list selector control registers. */ |
| 2655 | T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */ |
| 2656 | |
| 2657 | /* Mbuf cluster free registers. */ |
| 2658 | T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */ |
| 2659 | |
| 2660 | /* Host coalescing control registers. */ |
| 2661 | T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */ |
| 2662 | |
| 2663 | /* Memory arbiter control registers. */ |
| 2664 | T3_MEM_ARBITER MemArbiter; /* 0x4000 */ |
| 2665 | |
| 2666 | /* Buffer manger control registers. */ |
| 2667 | T3_BUFFER_MANAGER BufMgr; /* 0x4400 */ |
| 2668 | |
| 2669 | /* Read DMA control registers. */ |
| 2670 | T3_DMA_READ DmaRead; /* 0x4800 */ |
| 2671 | |
| 2672 | /* Write DMA control registers. */ |
| 2673 | T3_DMA_WRITE DmaWrite; /* 0x4c00 */ |
| 2674 | |
| 2675 | T3_CPU rxCpu; /* 0x5000 */ |
| 2676 | T3_CPU txCpu; /* 0x5400 */ |
| 2677 | |
| 2678 | /* Mailboxes. */ |
| 2679 | T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */ |
| 2680 | |
| 2681 | /* Flow Through queues. */ |
| 2682 | T3_FTQ Ftq; /* 0x5c00 */ |
| 2683 | |
| 2684 | /* Message signaled interrupt registes. */ |
| 2685 | T3_MSG_SIGNALED_INT Msi; /* 0x6000 */ |
| 2686 | |
| 2687 | /* DMA completion registers. */ |
| 2688 | T3_DMA_COMPLETION DmaComp; /* 0x6400 */ |
| 2689 | |
| 2690 | /* GRC registers. */ |
| 2691 | T3_GRC Grc; /* 0x6800 */ |
| 2692 | |
| 2693 | /* Unused space. */ |
| 2694 | LM_UINT8 Unused2[1024]; /* 0x6c00 */ |
| 2695 | |
| 2696 | /* NVRAM registers. */ |
| 2697 | T3_NVRAM Nvram; /* 0x7000 */ |
| 2698 | |
| 2699 | /* Unused space. */ |
| 2700 | LM_UINT8 Unused3[3072]; /* 0x7400 */ |
| 2701 | |
| 2702 | /* The 32k memory window into the NIC's */ |
| 2703 | /* internal memory. The memory window is */ |
| 2704 | /* controlled by the Memory Window Base */ |
| 2705 | /* Address register. This register is located */ |
| 2706 | /* in the PCI configuration space. */ |
| 2707 | union { /* 0x8000 */ |
| 2708 | T3_FIRST_32K_SRAM First32k; |
| 2709 | |
| 2710 | /* Use the memory window base address register to determine the */ |
| 2711 | /* MBUF segment. */ |
| 2712 | LM_UINT32 Mbuf[32768/4]; |
| 2713 | LM_UINT32 MemBlock32K[32768/4]; |
| 2714 | } uIntMem; |
| 2715 | } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP; |
| 2716 | |
| 2717 | |
| 2718 | /******************************************************************************/ |
| 2719 | /* Adapter info. */ |
| 2720 | /******************************************************************************/ |
| 2721 | |
| 2722 | typedef struct |
| 2723 | { |
| 2724 | LM_UINT16 Svid; |
| 2725 | LM_UINT16 Ssid; |
| 2726 | LM_UINT32 PhyId; |
| 2727 | LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */ |
| 2728 | } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO; |
| 2729 | |
| 2730 | |
| 2731 | /******************************************************************************/ |
| 2732 | /* Packet queues. */ |
| 2733 | /******************************************************************************/ |
| 2734 | |
| 2735 | DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT); |
| 2736 | DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT); |
| 2737 | |
| 2738 | |
| 2739 | |
| 2740 | /******************************************************************************/ |
| 2741 | /* Tx counters. */ |
| 2742 | /******************************************************************************/ |
| 2743 | |
| 2744 | typedef struct { |
| 2745 | LM_COUNTER TxPacketGoodCnt; |
| 2746 | LM_COUNTER TxBytesGoodCnt; |
| 2747 | LM_COUNTER TxPacketAbortedCnt; |
| 2748 | LM_COUNTER NoSendBdLeftCnt; |
| 2749 | LM_COUNTER NoMapRegisterLeftCnt; |
| 2750 | LM_COUNTER TooManyFragmentsCnt; |
| 2751 | LM_COUNTER NoTxPacketDescCnt; |
| 2752 | } LM_TX_COUNTERS, *PLM_TX_COUNTERS; |
| 2753 | |
| 2754 | |
| 2755 | |
| 2756 | /******************************************************************************/ |
| 2757 | /* Rx counters. */ |
| 2758 | /******************************************************************************/ |
| 2759 | |
| 2760 | typedef struct { |
| 2761 | LM_COUNTER RxPacketGoodCnt; |
| 2762 | LM_COUNTER RxBytesGoodCnt; |
| 2763 | LM_COUNTER RxPacketErrCnt; |
| 2764 | LM_COUNTER RxErrCrcCnt; |
| 2765 | LM_COUNTER RxErrCollCnt; |
| 2766 | LM_COUNTER RxErrLinkLostCnt; |
| 2767 | LM_COUNTER RxErrPhyDecodeCnt; |
| 2768 | LM_COUNTER RxErrOddNibbleCnt; |
| 2769 | LM_COUNTER RxErrMacAbortCnt; |
| 2770 | LM_COUNTER RxErrShortPacketCnt; |
| 2771 | LM_COUNTER RxErrNoResourceCnt; |
| 2772 | LM_COUNTER RxErrLargePacketCnt; |
| 2773 | } LM_RX_COUNTERS, *PLM_RX_COUNTERS; |
| 2774 | |
| 2775 | |
| 2776 | |
| 2777 | /******************************************************************************/ |
| 2778 | /* Receive producer rings. */ |
| 2779 | /******************************************************************************/ |
| 2780 | |
| 2781 | typedef enum { |
| 2782 | T3_UNKNOWN_RCV_PROD_RING = 0, |
| 2783 | T3_STD_RCV_PROD_RING = 1, |
| 2784 | T3_MINI_RCV_PROD_RING = 2, |
| 2785 | T3_JUMBO_RCV_PROD_RING = 3 |
| 2786 | } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING; |
| 2787 | |
| 2788 | |
| 2789 | |
| 2790 | /******************************************************************************/ |
| 2791 | /* Packet descriptor. */ |
| 2792 | /******************************************************************************/ |
| 2793 | |
| 2794 | #define LM_PACKET_SIGNATURE_TX 0x6861766b |
| 2795 | #define LM_PACKET_SIGNATURE_RX 0x6b766168 |
| 2796 | |
| 2797 | typedef struct _LM_PACKET { |
| 2798 | /* Set in LM. */ |
| 2799 | LM_STATUS PacketStatus; |
| 2800 | |
| 2801 | /* Set in LM for Rx, in UM for Tx. */ |
| 2802 | LM_UINT32 PacketSize; |
| 2803 | |
| 2804 | LM_UINT16 Flags; |
| 2805 | |
| 2806 | LM_UINT16 VlanTag; |
| 2807 | |
| 2808 | union { |
| 2809 | /* Send info. */ |
| 2810 | struct { |
| 2811 | /* Set up by UM. */ |
| 2812 | LM_UINT32 FragCount; |
| 2813 | |
| 2814 | } Tx; |
| 2815 | |
| 2816 | /* Receive info. */ |
| 2817 | struct { |
| 2818 | /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ |
| 2819 | T3_RCV_PROD_RING RcvProdRing; |
| 2820 | |
| 2821 | /* Receive buffer size */ |
| 2822 | LM_UINT32 RxBufferSize; |
| 2823 | |
| 2824 | /* Checksum information. */ |
| 2825 | LM_UINT16 IpChecksum; |
| 2826 | LM_UINT16 TcpUdpChecksum; |
| 2827 | |
| 2828 | } Rx; |
| 2829 | } u; |
| 2830 | } LM_PACKET; |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | /******************************************************************************/ |
| 2835 | /* Tigon3 device block. */ |
| 2836 | /******************************************************************************/ |
| 2837 | |
| 2838 | typedef struct _LM_DEVICE_BLOCK { |
| 2839 | int index; /* Device ID */ |
| 2840 | /* Memory view. */ |
| 2841 | PT3_STD_MEM_MAP pMemView; |
| 2842 | |
| 2843 | /* Base address of the block of memory in which the LM_PACKET descriptors */ |
| 2844 | /* are allocated from. */ |
| 2845 | PLM_VOID pPacketDescBase; |
| 2846 | |
| 2847 | LM_UINT32 MiscHostCtrl; |
| 2848 | LM_UINT32 GrcLocalCtrl; |
| 2849 | LM_UINT32 DmaReadWriteCtrl; |
| 2850 | LM_UINT32 PciState; |
| 2851 | |
| 2852 | /* Rx info */ |
| 2853 | LM_UINT32 RxStdDescCnt; |
| 2854 | LM_UINT32 RxStdQueuedCnt; |
| 2855 | LM_UINT32 RxStdProdIdx; |
| 2856 | |
| 2857 | PT3_RCV_BD pRxStdBdVirt; |
| 2858 | LM_PHYSICAL_ADDRESS RxStdBdPhy; |
| 2859 | |
| 2860 | LM_UINT32 RxPacketDescCnt; |
| 2861 | LM_RX_PACKET_Q RxPacketFreeQ; |
| 2862 | LM_RX_PACKET_Q RxPacketReceivedQ; |
| 2863 | |
| 2864 | /* Receive info. */ |
| 2865 | PT3_RCV_BD pRcvRetBdVirt; |
| 2866 | LM_PHYSICAL_ADDRESS RcvRetBdPhy; |
| 2867 | LM_UINT32 RcvRetConIdx; |
| 2868 | |
| 2869 | #if T3_JUMBO_RCV_RCB_ENTRY_COUNT |
| 2870 | LM_UINT32 RxJumboDescCnt; |
| 2871 | LM_UINT32 RxJumboBufferSize; |
| 2872 | LM_UINT32 RxJumboQueuedCnt; |
| 2873 | |
| 2874 | LM_UINT32 RxJumboProdIdx; |
| 2875 | |
| 2876 | PT3_RCV_BD pRxJumboBdVirt; |
| 2877 | LM_PHYSICAL_ADDRESS RxJumboBdPhy; |
| 2878 | #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ |
| 2879 | |
| 2880 | /* These values are used by the upper module to inform the protocol */ |
| 2881 | /* of the maximum transmit/receive packet size. */ |
| 2882 | LM_UINT32 TxMtu; /* Does not include CRC. */ |
| 2883 | LM_UINT32 RxMtu; /* Does not include CRC. */ |
| 2884 | |
| 2885 | /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */ |
| 2886 | /* we may have problems reading any MAC registers in 10mb mode. */ |
| 2887 | LM_UINT32 MacMode; |
| 2888 | LM_UINT32 RxMode; |
| 2889 | LM_UINT32 TxMode; |
| 2890 | |
| 2891 | /* MiMode register. */ |
| 2892 | LM_UINT32 MiMode; |
| 2893 | |
| 2894 | /* Host coalesce mode register. */ |
| 2895 | LM_UINT32 CoalesceMode; |
| 2896 | |
| 2897 | /* Send info. */ |
| 2898 | LM_UINT32 TxPacketDescCnt; |
| 2899 | |
| 2900 | /* Tx info. */ |
| 2901 | LM_TX_PACKET_Q TxPacketFreeQ; |
| 2902 | LM_TX_PACKET_Q TxPacketActiveQ; |
| 2903 | LM_TX_PACKET_Q TxPacketXmittedQ; |
| 2904 | |
| 2905 | /* Pointers to SendBd. */ |
| 2906 | PT3_SND_BD pSendBdVirt; |
| 2907 | LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */ |
| 2908 | |
| 2909 | /* Send producer and consumer indices. */ |
| 2910 | LM_UINT32 SendProdIdx; |
| 2911 | LM_UINT32 SendConIdx; |
| 2912 | |
| 2913 | /* Number of BD left. */ |
| 2914 | atomic_t SendBdLeft; |
| 2915 | |
| 2916 | T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT]; |
| 2917 | |
| 2918 | /* Counters. */ |
| 2919 | LM_RX_COUNTERS RxCounters; |
| 2920 | LM_TX_COUNTERS TxCounters; |
| 2921 | |
| 2922 | /* Host coalescing parameters. */ |
| 2923 | LM_UINT32 RxCoalescingTicks; |
| 2924 | LM_UINT32 TxCoalescingTicks; |
| 2925 | LM_UINT32 RxMaxCoalescedFrames; |
| 2926 | LM_UINT32 TxMaxCoalescedFrames; |
| 2927 | LM_UINT32 StatsCoalescingTicks; |
| 2928 | LM_UINT32 RxCoalescingTicksDuringInt; |
| 2929 | LM_UINT32 TxCoalescingTicksDuringInt; |
| 2930 | LM_UINT32 RxMaxCoalescedFramesDuringInt; |
| 2931 | LM_UINT32 TxMaxCoalescedFramesDuringInt; |
| 2932 | |
| 2933 | /* DMA water marks. */ |
| 2934 | LM_UINT32 DmaMbufLowMark; |
| 2935 | LM_UINT32 RxMacMbufLowMark; |
| 2936 | LM_UINT32 MbufHighMark; |
| 2937 | |
| 2938 | /* Status block. */ |
| 2939 | PT3_STATUS_BLOCK pStatusBlkVirt; |
| 2940 | LM_PHYSICAL_ADDRESS StatusBlkPhy; |
| 2941 | |
| 2942 | /* Statistics block. */ |
| 2943 | PT3_STATS_BLOCK pStatsBlkVirt; |
| 2944 | LM_PHYSICAL_ADDRESS StatsBlkPhy; |
| 2945 | |
| 2946 | /* Current receive mask. */ |
| 2947 | LM_UINT32 ReceiveMask; |
| 2948 | |
| 2949 | /* Task offload capabilities. */ |
| 2950 | LM_TASK_OFFLOAD TaskOffloadCap; |
| 2951 | |
| 2952 | /* Task offload selected. */ |
| 2953 | LM_TASK_OFFLOAD TaskToOffload; |
| 2954 | |
| 2955 | /* Wake up capability. */ |
| 2956 | LM_WAKE_UP_MODE WakeUpModeCap; |
| 2957 | |
| 2958 | /* Wake up capability. */ |
| 2959 | LM_WAKE_UP_MODE WakeUpMode; |
| 2960 | |
| 2961 | /* Flow control. */ |
| 2962 | LM_FLOW_CONTROL FlowControlCap; |
| 2963 | LM_FLOW_CONTROL FlowControl; |
| 2964 | |
| 2965 | /* Enable or disable PCI MWI. */ |
| 2966 | LM_UINT32 EnableMWI; |
| 2967 | |
| 2968 | /* Enable 5701 tagged status mode. */ |
| 2969 | LM_UINT32 UseTaggedStatus; |
| 2970 | |
| 2971 | /* NIC will not compute the pseudo header checksum. The driver or OS */ |
| 2972 | /* must seed the checksum field with the pseudo checksum. */ |
| 2973 | LM_UINT32 NoTxPseudoHdrChksum; |
| 2974 | |
| 2975 | /* The receive checksum in the BD does not include the pseudo checksum. */ |
| 2976 | /* The OS or the driver must calculate the pseudo checksum and add it to */ |
| 2977 | /* the checksum in the BD. */ |
| 2978 | LM_UINT32 NoRxPseudoHdrChksum; |
| 2979 | |
| 2980 | /* Current node address. */ |
| 2981 | LM_UINT8 NodeAddress[8]; |
| 2982 | |
| 2983 | /* The adapter's node address. */ |
| 2984 | LM_UINT8 PermanentNodeAddress[8]; |
| 2985 | |
| 2986 | /* Adapter info. */ |
| 2987 | LM_UINT16 BusNum; |
| 2988 | LM_UINT8 DevNum; |
| 2989 | LM_UINT8 FunctNum; |
| 2990 | LM_UINT16 PciVendorId; |
| 2991 | LM_UINT16 PciDeviceId; |
| 2992 | LM_UINT32 BondId; |
| 2993 | LM_UINT8 Irq; |
| 2994 | LM_UINT8 IntPin; |
| 2995 | LM_UINT8 CacheLineSize; |
| 2996 | LM_UINT8 PciRevId; |
| 2997 | #if PCIX_TARGET_WORKAROUND |
| 2998 | LM_UINT32 EnablePciXFix; |
| 2999 | #endif |
| 3000 | LM_UINT32 UndiFix; /* new, jimmy */ |
| 3001 | LM_UINT32 PciCommandStatusWords; |
| 3002 | LM_UINT32 ChipRevId; |
| 3003 | LM_UINT16 SubsystemVendorId; |
| 3004 | LM_UINT16 SubsystemId; |
| 3005 | #if 0 /* Jimmy, deleted in new driver */ |
| 3006 | LM_UINT32 MemBaseLow; |
| 3007 | LM_UINT32 MemBaseHigh; |
| 3008 | LM_UINT32 MemBaseSize; |
| 3009 | #endif |
| 3010 | PLM_UINT8 pMappedMemBase; |
| 3011 | |
| 3012 | /* Saved PCI configuration registers for restoring after a reset. */ |
| 3013 | LM_UINT32 SavedCacheLineReg; |
| 3014 | |
| 3015 | /* Phy info. */ |
| 3016 | LM_UINT32 PhyAddr; |
| 3017 | LM_UINT32 PhyId; |
| 3018 | |
| 3019 | /* Requested phy settings. */ |
| 3020 | LM_REQUESTED_MEDIA_TYPE RequestedMediaType; |
| 3021 | |
| 3022 | /* Disable auto-negotiation. */ |
| 3023 | LM_UINT32 DisableAutoNeg; |
| 3024 | |
| 3025 | /* Ways for the MAC to get link change interrupt. */ |
| 3026 | LM_UINT32 PhyIntMode; |
| 3027 | #define T3_PHY_INT_MODE_AUTO 0 |
| 3028 | #define T3_PHY_INT_MODE_MI_INTERRUPT 1 |
| 3029 | #define T3_PHY_INT_MODE_LINK_READY 2 |
| 3030 | #define T3_PHY_INT_MODE_AUTO_POLLING 3 |
| 3031 | |
| 3032 | /* Ways to determine link change status. */ |
| 3033 | LM_UINT32 LinkChngMode; |
| 3034 | #define T3_LINK_CHNG_MODE_AUTO 0 |
| 3035 | #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1 |
| 3036 | #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2 |
| 3037 | |
| 3038 | |
| 3039 | /* LED mode. */ |
| 3040 | LM_UINT32 LedMode; |
| 3041 | |
| 3042 | #define LED_MODE_AUTO 0 |
| 3043 | |
| 3044 | /* 5700/01 LED mode. */ |
| 3045 | #define LED_MODE_THREE_LINK 1 |
| 3046 | #define LED_MODE_LINK10 2 |
| 3047 | |
| 3048 | /* 5703/02/04 LED mode. */ |
| 3049 | #define LED_MODE_OPEN_DRAIN 1 |
| 3050 | #define LED_MODE_OUTPUT 2 |
| 3051 | |
| 3052 | /* WOL Speed */ |
| 3053 | LM_UINT32 WolSpeed; |
| 3054 | #define WOL_SPEED_10MB 1 |
| 3055 | #define WOL_SPEED_100MB 2 |
| 3056 | |
| 3057 | /* Reset the PHY on initialization. */ |
| 3058 | LM_UINT32 ResetPhyOnInit; |
| 3059 | |
| 3060 | LM_UINT32 RestoreOnWakeUp; |
| 3061 | LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType; |
| 3062 | LM_UINT32 WakeUpDisableAutoNeg; |
| 3063 | |
| 3064 | /* Current phy settings. */ |
| 3065 | LM_MEDIA_TYPE MediaType; |
| 3066 | LM_LINE_SPEED LineSpeed; |
| 3067 | LM_LINE_SPEED OldLineSpeed; |
| 3068 | LM_DUPLEX_MODE DuplexMode; |
| 3069 | LM_STATUS LinkStatus; |
| 3070 | LM_UINT32 advertising; /* Jimmy, new! */ |
| 3071 | LM_UINT32 advertising1000; /* Jimmy, new! */ |
| 3072 | |
| 3073 | /* Multicast address list. */ |
| 3074 | LM_UINT32 McEntryCount; |
| 3075 | LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE]; |
| 3076 | |
| 3077 | /* Use NIC or Host based send BD. */ |
| 3078 | LM_UINT32 NicSendBd; |
| 3079 | |
| 3080 | /* Athlon fix. */ |
| 3081 | LM_UINT32 DelayPciGrant; |
| 3082 | |
| 3083 | /* Enable OneDmaAtOnce */ |
| 3084 | LM_UINT32 OneDmaAtOnce; |
| 3085 | |
| 3086 | /* Split Mode flags, Jimmy new */ |
| 3087 | LM_UINT32 SplitModeEnable; |
| 3088 | LM_UINT32 SplitModeMaxReq; |
| 3089 | |
| 3090 | /* Init flag. */ |
| 3091 | LM_BOOL InitDone; |
| 3092 | |
| 3093 | /* Shutdown flag. Set by the upper module. */ |
| 3094 | LM_BOOL ShuttingDown; |
| 3095 | |
| 3096 | /* Flag to determine whether to call LM_QueueRxPackets or not in */ |
| 3097 | /* LM_ResetAdapter routine. */ |
| 3098 | LM_BOOL QueueRxPackets; |
| 3099 | |
| 3100 | LM_UINT32 MbufBase; |
| 3101 | LM_UINT32 MbufSize; |
| 3102 | |
| 3103 | /* TRUE if we have a SERDES PHY. */ |
| 3104 | LM_UINT32 EnableTbi; |
| 3105 | |
| 3106 | /* Ethernet@WireSpeed. */ |
| 3107 | LM_UINT32 EnableWireSpeed; |
| 3108 | |
| 3109 | LM_UINT32 EepromWp; |
| 3110 | |
| 3111 | #if INCLUDE_TBI_SUPPORT |
| 3112 | /* Autoneg state info. */ |
| 3113 | AN_STATE_INFO AnInfo; |
| 3114 | LM_UINT32 PollTbiLink; |
| 3115 | LM_UINT32 IgnoreTbiLinkChange; |
| 3116 | #endif |
| 3117 | char PartNo[24]; |
| 3118 | char BootCodeVer[16]; |
| 3119 | char BusSpeedStr[24]; /* Jimmy, new! */ |
| 3120 | LM_UINT32 PhyCrcCount; |
| 3121 | } LM_DEVICE_BLOCK; |
| 3122 | |
| 3123 | |
| 3124 | #define T3_REG_CPU_VIEW 0xc0000000 |
| 3125 | |
| 3126 | #define T3_BLOCK_DMA_RD (1 << 0) |
| 3127 | #define T3_BLOCK_DMA_COMP (1 << 1) |
| 3128 | #define T3_BLOCK_RX_BD_INITIATOR (1 << 2) |
| 3129 | #define T3_BLOCK_RX_BD_COMP (1 << 3) |
| 3130 | #define T3_BLOCK_DMA_WR (1 << 4) |
| 3131 | #define T3_BLOCK_MSI_HANDLER (1 << 5) |
| 3132 | #define T3_BLOCK_RX_LIST_PLMT (1 << 6) |
| 3133 | #define T3_BLOCK_RX_LIST_SELECTOR (1 << 7) |
| 3134 | #define T3_BLOCK_RX_DATA_INITIATOR (1 << 8) |
| 3135 | #define T3_BLOCK_RX_DATA_COMP (1 << 9) |
| 3136 | #define T3_BLOCK_HOST_COALESING (1 << 10) |
| 3137 | #define T3_BLOCK_MAC_RX_ENGINE (1 << 11) |
| 3138 | #define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12) |
| 3139 | #define T3_BLOCK_SEND_BD_INITIATOR (1 << 13) |
| 3140 | #define T3_BLOCK_SEND_BD_COMP (1 << 14) |
| 3141 | #define T3_BLOCK_SEND_BD_SELECTOR (1 << 15) |
| 3142 | #define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16) |
| 3143 | #define T3_BLOCK_SEND_DATA_COMP (1 << 17) |
| 3144 | #define T3_BLOCK_MAC_TX_ENGINE (1 << 18) |
| 3145 | #define T3_BLOCK_MEM_ARBITOR (1 << 19) |
| 3146 | #define T3_BLOCK_MBUF_MANAGER (1 << 20) |
| 3147 | #define T3_BLOCK_MAC_GLOBAL (1 << 21) |
| 3148 | |
| 3149 | #define LM_ENABLE 1 |
| 3150 | #define LM_DISABLE 2 |
| 3151 | |
| 3152 | #define RX_CPU_EVT_SW0 0 |
| 3153 | #define RX_CPU_EVT_SW1 1 |
| 3154 | #define RX_CPU_EVT_RLP 2 |
| 3155 | #define RX_CPU_EVT_SW3 3 |
| 3156 | #define RX_CPU_EVT_RLS 4 |
| 3157 | #define RX_CPU_EVT_SW4 5 |
| 3158 | #define RX_CPU_EVT_RX_BD_COMP 6 |
| 3159 | #define RX_CPU_EVT_SW5 7 |
| 3160 | #define RX_CPU_EVT_RDI 8 |
| 3161 | #define RX_CPU_EVT_DMA_WR 9 |
| 3162 | #define RX_CPU_EVT_DMA_RD 10 |
| 3163 | #define RX_CPU_EVT_SWQ 11 |
| 3164 | #define RX_CPU_EVT_SW6 12 |
| 3165 | #define RX_CPU_EVT_RDC 13 |
| 3166 | #define RX_CPU_EVT_SW7 14 |
| 3167 | #define RX_CPU_EVT_HOST_COALES 15 |
| 3168 | #define RX_CPU_EVT_SW8 16 |
| 3169 | #define RX_CPU_EVT_HIGH_DMA_WR 17 |
| 3170 | #define RX_CPU_EVT_HIGH_DMA_RD 18 |
| 3171 | #define RX_CPU_EVT_SW9 19 |
| 3172 | #define RX_CPU_EVT_DMA_ATTN 20 |
| 3173 | #define RX_CPU_EVT_LOW_P_MBOX 21 |
| 3174 | #define RX_CPU_EVT_HIGH_P_MBOX 22 |
| 3175 | #define RX_CPU_EVT_SW10 23 |
| 3176 | #define RX_CPU_EVT_TX_CPU_ATTN 24 |
| 3177 | #define RX_CPU_EVT_MAC_ATTN 25 |
| 3178 | #define RX_CPU_EVT_RX_CPU_ATTN 26 |
| 3179 | #define RX_CPU_EVT_FLOW_ATTN 27 |
| 3180 | #define RX_CPU_EVT_SW11 28 |
| 3181 | #define RX_CPU_EVT_TIMER 29 |
| 3182 | #define RX_CPU_EVT_SW12 30 |
| 3183 | #define RX_CPU_EVT_SW13 31 |
| 3184 | |
| 3185 | /* RX-CPU event */ |
| 3186 | #define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0) |
| 3187 | #define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1) |
| 3188 | #define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP) |
| 3189 | #define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3) |
| 3190 | #define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS) |
| 3191 | #define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4) |
| 3192 | #define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP) |
| 3193 | #define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5) |
| 3194 | #define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI) |
| 3195 | #define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR) |
| 3196 | #define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD) |
| 3197 | #define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ) |
| 3198 | #define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6) |
| 3199 | #define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC) |
| 3200 | #define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7) |
| 3201 | #define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES) |
| 3202 | #define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8) |
| 3203 | #define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR) |
| 3204 | #define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD) |
| 3205 | #define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9) |
| 3206 | #define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN) |
| 3207 | #define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX) |
| 3208 | #define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX) |
| 3209 | #define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10) |
| 3210 | #define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN) |
| 3211 | #define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN) |
| 3212 | #define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN) |
| 3213 | #define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN) |
| 3214 | #define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11) |
| 3215 | #define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER) |
| 3216 | #define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12) |
| 3217 | #define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13) |
| 3218 | |
| 3219 | #define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \ |
| 3220 | RX_CPU_EVENT_RLP | \ |
| 3221 | RX_CPU_EVENT_RDI | \ |
| 3222 | RX_CPU_EVENT_RDC) |
| 3223 | |
| 3224 | #define TX_CPU_EVT_SW0 0 |
| 3225 | #define TX_CPU_EVT_SW1 1 |
| 3226 | #define TX_CPU_EVT_SW2 2 |
| 3227 | #define TX_CPU_EVT_SW3 3 |
| 3228 | #define TX_CPU_EVT_TX_MAC 4 |
| 3229 | #define TX_CPU_EVT_SW4 5 |
| 3230 | #define TX_CPU_EVT_SBDC 6 |
| 3231 | #define TX_CPU_EVT_SW5 7 |
| 3232 | #define TX_CPU_EVT_SDI 8 |
| 3233 | #define TX_CPU_EVT_DMA_WR 9 |
| 3234 | #define TX_CPU_EVT_DMA_RD 10 |
| 3235 | #define TX_CPU_EVT_SWQ 11 |
| 3236 | #define TX_CPU_EVT_SW6 12 |
| 3237 | #define TX_CPU_EVT_SDC 13 |
| 3238 | #define TX_CPU_EVT_SW7 14 |
| 3239 | #define TX_CPU_EVT_HOST_COALES 15 |
| 3240 | #define TX_CPU_EVT_SW8 16 |
| 3241 | #define TX_CPU_EVT_HIGH_DMA_WR 17 |
| 3242 | #define TX_CPU_EVT_HIGH_DMA_RD 18 |
| 3243 | #define TX_CPU_EVT_SW9 19 |
| 3244 | #define TX_CPU_EVT_DMA_ATTN 20 |
| 3245 | #define TX_CPU_EVT_LOW_P_MBOX 21 |
| 3246 | #define TX_CPU_EVT_HIGH_P_MBOX 22 |
| 3247 | #define TX_CPU_EVT_SW10 23 |
| 3248 | #define TX_CPU_EVT_RX_CPU_ATTN 24 |
| 3249 | #define TX_CPU_EVT_MAC_ATTN 25 |
| 3250 | #define TX_CPU_EVT_TX_CPU_ATTN 26 |
| 3251 | #define TX_CPU_EVT_FLOW_ATTN 27 |
| 3252 | #define TX_CPU_EVT_SW11 28 |
| 3253 | #define TX_CPU_EVT_TIMER 29 |
| 3254 | #define TX_CPU_EVT_SW12 30 |
| 3255 | #define TX_CPU_EVT_SW13 31 |
| 3256 | |
| 3257 | |
| 3258 | /* TX-CPU event */ |
| 3259 | #define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0) |
| 3260 | #define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1) |
| 3261 | #define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2) |
| 3262 | #define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3) |
| 3263 | #define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC) |
| 3264 | #define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4) |
| 3265 | #define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC) |
| 3266 | #define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5) |
| 3267 | #define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI) |
| 3268 | #define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR) |
| 3269 | #define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD) |
| 3270 | #define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ) |
| 3271 | #define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6) |
| 3272 | #define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC) |
| 3273 | #define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7) |
| 3274 | #define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES) |
| 3275 | #define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8) |
| 3276 | #define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR) |
| 3277 | #define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD) |
| 3278 | #define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9) |
| 3279 | #define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN) |
| 3280 | #define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX) |
| 3281 | #define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX) |
| 3282 | #define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10) |
| 3283 | #define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN) |
| 3284 | #define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN) |
| 3285 | #define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN) |
| 3286 | #define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN) |
| 3287 | #define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11) |
| 3288 | #define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER) |
| 3289 | #define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12) |
| 3290 | #define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13) |
| 3291 | |
| 3292 | |
| 3293 | #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \ |
| 3294 | TX_CPU_EVENT_SDI | \ |
| 3295 | TX_CPU_EVENT_SDC) |
| 3296 | |
| 3297 | |
| 3298 | #define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29) |
| 3299 | #define T3_FTQ_TYPE1_PASS_BIT (1 << 30) |
| 3300 | #define T3_FTQ_TYPE1_SKIP_BIT (1 << 31) |
| 3301 | |
| 3302 | #define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13) |
| 3303 | #define T3_FTQ_TYPE2_PASS_BIT (1 << 14) |
| 3304 | #define T3_FTQ_TYPE2_SKIP_BIT (1 << 15) |
| 3305 | |
| 3306 | #define T3_QID_DMA_READ 1 |
| 3307 | #define T3_QID_DMA_HIGH_PRI_READ 2 |
| 3308 | #define T3_QID_DMA_COMP_DX 3 |
| 3309 | #define T3_QID_SEND_BD_COMP 4 |
| 3310 | #define T3_QID_SEND_DATA_INITIATOR 5 |
| 3311 | #define T3_QID_DMA_WRITE 6 |
| 3312 | #define T3_QID_DMA_HIGH_PRI_WRITE 7 |
| 3313 | #define T3_QID_SW_TYPE_1 8 |
| 3314 | #define T3_QID_SEND_DATA_COMP 9 |
| 3315 | #define T3_QID_HOST_COALESCING 10 |
| 3316 | #define T3_QID_MAC_TX 11 |
| 3317 | #define T3_QID_MBUF_CLUSTER_FREE 12 |
| 3318 | #define T3_QID_RX_BD_COMP 13 |
| 3319 | #define T3_QID_RX_LIST_PLM 14 |
| 3320 | #define T3_QID_RX_DATA_BD_INITIATOR 15 |
| 3321 | #define T3_QID_RX_DATA_COMP 16 |
| 3322 | #define T3_QID_SW_TYPE2 17 |
| 3323 | |
| 3324 | LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, |
| 3325 | PT3_FWIMG_INFO pFwImg, |
| 3326 | LM_UINT32 LoadCpu, |
| 3327 | LM_UINT32 StartCpu); |
| 3328 | |
| 3329 | /******************************************************************************/ |
| 3330 | /* NIC register read/write macros. */ |
| 3331 | /******************************************************************************/ |
| 3332 | |
| 3333 | #if 0 /* Jimmy */ |
| 3334 | /* MAC register access. */ |
| 3335 | LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); |
| 3336 | LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, |
| 3337 | LM_UINT32 Value32); |
| 3338 | |
| 3339 | /* MAC memory access. */ |
| 3340 | LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); |
| 3341 | LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, |
| 3342 | LM_UINT32 Value32); |
| 3343 | |
| 3344 | #if PCIX_TARGET_WORKAROUND |
| 3345 | |
| 3346 | /* use memory-mapped accesses for mailboxes and reads, UNDI accesses |
| 3347 | for writes to all other registers */ |
| 3348 | #define REG_RD(pDevice, OffsetName) \ |
| 3349 | readl(&((pDevice)->pMemView->OffsetName)) |
| 3350 | |
| 3351 | #define REG_WR(pDevice, OffsetName, Value32) \ |
| 3352 | (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \ |
| 3353 | (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \ |
| 3354 | ((pDevice)->EnablePciXFix == FALSE)) ? \ |
| 3355 | (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ |
| 3356 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) |
| 3357 | |
| 3358 | #define MB_REG_RD(pDevice, OffsetName) \ |
| 3359 | readl(&((pDevice)->pMemView->OffsetName)) |
| 3360 | |
| 3361 | #define MB_REG_WR(pDevice, OffsetName, Value32) \ |
| 3362 | writel(Value32, &((pDevice)->pMemView->OffsetName)) |
| 3363 | |
| 3364 | #define REG_RD_OFFSET(pDevice, Offset) \ |
| 3365 | readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset)) |
| 3366 | |
| 3367 | #define REG_WR_OFFSET(pDevice, Offset, Value32) \ |
| 3368 | (((Offset >=0x200 ) && (Offset < 0x400)) || \ |
| 3369 | ((pDevice)->EnablePciXFix == FALSE)) ? \ |
| 3370 | (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \ |
| 3371 | LM_RegWrInd(pDevice, Offset, Value32) |
| 3372 | |
| 3373 | #define MEM_RD(pDevice, AddrName) \ |
| 3374 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) |
| 3375 | #define MEM_WR(pDevice, AddrName, Value32) \ |
| 3376 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) |
| 3377 | |
| 3378 | #define MEM_RD_OFFSET(pDevice, Offset) \ |
| 3379 | LM_MemRdInd(pDevice, Offset) |
| 3380 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ |
| 3381 | LM_MemWrInd(pDevice, Offset, Value32) |
| 3382 | |
| 3383 | #else /* normal target access path below */ |
| 3384 | |
| 3385 | /* Register access. */ |
| 3386 | #define REG_RD(pDevice, OffsetName) \ |
| 3387 | readl(&((pDevice)->pMemView->OffsetName)) |
| 3388 | #define REG_WR(pDevice, OffsetName, Value32) \ |
| 3389 | writel(Value32, &((pDevice)->pMemView->OffsetName)) |
| 3390 | |
| 3391 | #define REG_RD_OFFSET(pDevice, Offset) \ |
| 3392 | readl(((LM_UINT8 *) (pDevice)->pMemView + Offset)) |
| 3393 | #define REG_WR_OFFSET(pDevice, Offset, Value32) \ |
| 3394 | writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) |
| 3395 | |
| 3396 | |
| 3397 | /* There could be problem access the memory window directly. For now, */ |
| 3398 | /* we have to go through the PCI configuration register. */ |
| 3399 | #define MEM_RD(pDevice, AddrName) \ |
| 3400 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) |
| 3401 | #define MEM_WR(pDevice, AddrName, Value32) \ |
| 3402 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) |
| 3403 | |
| 3404 | #define MEM_RD_OFFSET(pDevice, Offset) \ |
| 3405 | LM_MemRdInd(pDevice, Offset) |
| 3406 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ |
| 3407 | LM_MemWrInd(pDevice, Offset, Value32) |
| 3408 | |
| 3409 | #endif /* PCIX_TARGET_WORKAROUND */ |
| 3410 | |
| 3411 | #endif /* Jimmy, merging */ |
| 3412 | |
| 3413 | /* Jimmy...rest of file is new stuff! */ |
| 3414 | /******************************************************************************/ |
| 3415 | /* NIC register read/write macros. */ |
| 3416 | /******************************************************************************/ |
| 3417 | |
| 3418 | /* MAC register access. */ |
| 3419 | LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); |
| 3420 | LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, |
| 3421 | LM_UINT32 Value32); |
| 3422 | |
| 3423 | /* MAC memory access. */ |
| 3424 | LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); |
| 3425 | LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, |
| 3426 | LM_UINT32 Value32); |
| 3427 | |
| 3428 | #define MB_REG_WR(pDevice, OffsetName, Value32) \ |
| 3429 | ((pDevice)->UndiFix) ? \ |
| 3430 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ |
| 3431 | Value32) : \ |
| 3432 | (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) |
| 3433 | |
| 3434 | #define MB_REG_RD(pDevice, OffsetName) \ |
| 3435 | (((pDevice)->UndiFix) ? \ |
| 3436 | LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ |
| 3437 | __raw_readl(&((pDevice)->pMemView->OffsetName))) |
| 3438 | |
| 3439 | #define REG_RD(pDevice, OffsetName) \ |
| 3440 | (((pDevice)->UndiFix) ? \ |
| 3441 | LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ |
| 3442 | __raw_readl(&((pDevice)->pMemView->OffsetName))) |
| 3443 | |
| 3444 | #if PCIX_TARGET_WORKAROUND |
| 3445 | |
| 3446 | #define REG_WR(pDevice, OffsetName, Value32) \ |
| 3447 | ((pDevice)->EnablePciXFix == FALSE) ? \ |
| 3448 | (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ |
| 3449 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) |
| 3450 | |
| 3451 | #else |
| 3452 | |
| 3453 | #define REG_WR(pDevice, OffsetName, Value32) \ |
| 3454 | __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) |
| 3455 | |
| 3456 | #endif |
| 3457 | |
| 3458 | #define MEM_RD(pDevice, AddrName) \ |
| 3459 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) |
| 3460 | #define MEM_WR(pDevice, AddrName, Value32) \ |
| 3461 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) |
| 3462 | |
| 3463 | #define MEM_RD_OFFSET(pDevice, Offset) \ |
| 3464 | LM_MemRdInd(pDevice, Offset) |
| 3465 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ |
| 3466 | LM_MemWrInd(pDevice, Offset, Value32) |
| 3467 | |
| 3468 | #endif /* TIGON3_H */ |
| 3469 | |