blob: dc8fa8891be6b95200d95ca696215bd04e36bdd8 [file] [log] [blame]
Simon Glass291391b2011-06-13 16:13:09 -07001/*
Simon Glass0990fcb2015-07-07 20:53:42 -06002 * Copyright (c) 2015 Google, Inc
Simon Glass291391b2011-06-13 16:13:09 -07003 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (C) 2009 NVIDIA, Corporation
Simon Glassad6e48e2014-09-08 13:44:14 -06005 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
Simon Glass291391b2011-06-13 16:13:09 -07006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glass291391b2011-06-13 16:13:09 -07008 */
9
10#include <common.h>
Simon Glass0990fcb2015-07-07 20:53:42 -060011#include <dm.h>
Simon Glassa2692592015-07-07 20:53:38 -060012#include <errno.h>
13#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060014#include <memalign.h>
Simon Glass291391b2011-06-13 16:13:09 -070015#include <usb.h>
Simon Glassa2692592015-07-07 20:53:38 -060016#include <asm/unaligned.h>
Simon Glass291391b2011-06-13 16:13:09 -070017#include <linux/mii.h>
18#include "usb_ether.h"
19
20/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
21
Suriyan Ramasami98f686c2013-10-07 20:30:58 -070022/* LED defines */
23#define LED_GPIO_CFG (0x24)
24#define LED_GPIO_CFG_SPD_LED (0x01000000)
25#define LED_GPIO_CFG_LNK_LED (0x00100000)
26#define LED_GPIO_CFG_FDX_LED (0x00010000)
27
Simon Glass291391b2011-06-13 16:13:09 -070028/* Tx command words */
29#define TX_CMD_A_FIRST_SEG_ 0x00002000
30#define TX_CMD_A_LAST_SEG_ 0x00001000
31
32/* Rx status word */
33#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
34#define RX_STS_ES_ 0x00008000 /* Error Summary */
35
36/* SCSRs */
37#define ID_REV 0x00
38
39#define INT_STS 0x08
40
41#define TX_CFG 0x10
42#define TX_CFG_ON_ 0x00000004
43
44#define HW_CFG 0x14
45#define HW_CFG_BIR_ 0x00001000
46#define HW_CFG_RXDOFF_ 0x00000600
47#define HW_CFG_MEF_ 0x00000020
48#define HW_CFG_BCE_ 0x00000002
49#define HW_CFG_LRST_ 0x00000008
50
51#define PM_CTRL 0x20
52#define PM_CTL_PHY_RST_ 0x00000010
53
54#define AFC_CFG 0x2C
55
56/*
57 * Hi watermark = 15.5Kb (~10 mtu pkts)
58 * low watermark = 3k (~2 mtu pkts)
59 * backpressure duration = ~ 350us
60 * Apply FC on any frame.
61 */
62#define AFC_CFG_DEFAULT 0x00F830A1
63
64#define E2P_CMD 0x30
65#define E2P_CMD_BUSY_ 0x80000000
66#define E2P_CMD_READ_ 0x00000000
67#define E2P_CMD_TIMEOUT_ 0x00000400
68#define E2P_CMD_LOADED_ 0x00000200
69#define E2P_CMD_ADDR_ 0x000001FF
70
71#define E2P_DATA 0x34
72
73#define BURST_CAP 0x38
74
75#define INT_EP_CTL 0x68
76#define INT_EP_CTL_PHY_INT_ 0x00008000
77
78#define BULK_IN_DLY 0x6C
79
80/* MAC CSRs */
81#define MAC_CR 0x100
82#define MAC_CR_MCPAS_ 0x00080000
83#define MAC_CR_PRMS_ 0x00040000
84#define MAC_CR_HPFILT_ 0x00002000
85#define MAC_CR_TXEN_ 0x00000008
86#define MAC_CR_RXEN_ 0x00000004
87
88#define ADDRH 0x104
89
90#define ADDRL 0x108
91
92#define MII_ADDR 0x114
93#define MII_WRITE_ 0x02
94#define MII_BUSY_ 0x01
95#define MII_READ_ 0x00 /* ~of MII Write bit */
96
97#define MII_DATA 0x118
98
99#define FLOW 0x11C
100
101#define VLAN1 0x120
102
103#define COE_CR 0x130
104#define Tx_COE_EN_ 0x00010000
105#define Rx_COE_EN_ 0x00000001
106
107/* Vendor-specific PHY Definitions */
108#define PHY_INT_SRC 29
109
110#define PHY_INT_MASK 30
111#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
112#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
113#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
114 PHY_INT_MASK_LINK_DOWN_)
115
116/* USB Vendor Requests */
117#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
118#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
119
120/* Some extra defines */
121#define HS_USB_PKT_SIZE 512
122#define FS_USB_PKT_SIZE 64
123#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
124#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
125#define DEFAULT_BULK_IN_DELAY 0x00002000
126#define MAX_SINGLE_PACKET_SIZE 2048
127#define EEPROM_MAC_OFFSET 0x01
128#define SMSC95XX_INTERNAL_PHY_ID 1
129#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
130
131/* local defines */
132#define SMSC95XX_BASE_NAME "sms"
133#define USB_CTRL_SET_TIMEOUT 5000
134#define USB_CTRL_GET_TIMEOUT 5000
135#define USB_BULK_SEND_TIMEOUT 5000
136#define USB_BULK_RECV_TIMEOUT 5000
137
Simon Glassd62a1dc2015-07-07 20:53:39 -0600138#define RX_URB_SIZE 2048
Simon Glass291391b2011-06-13 16:13:09 -0700139#define PHY_CONNECT_TIMEOUT 5000
140
141#define TURBO_MODE
142
Simon Glass0990fcb2015-07-07 20:53:42 -0600143#ifndef CONFIG_DM_ETH
Simon Glass291391b2011-06-13 16:13:09 -0700144/* local vars */
145static int curr_eth_dev; /* index for name of next device detected */
Simon Glass0990fcb2015-07-07 20:53:42 -0600146#endif
Simon Glass291391b2011-06-13 16:13:09 -0700147
Lucas Stache1dbdf92012-08-22 11:04:57 +0000148/* driver private */
149struct smsc95xx_private {
Simon Glass0990fcb2015-07-07 20:53:42 -0600150#ifdef CONFIG_DM_ETH
151 struct ueth_data ueth;
152#endif
Lucas Stache1dbdf92012-08-22 11:04:57 +0000153 size_t rx_urb_size; /* maximum USB URB size */
154 u32 mac_cr; /* MAC control register value */
155 int have_hwaddr; /* 1 if we have a hardware MAC address */
156};
Simon Glass291391b2011-06-13 16:13:09 -0700157
158/*
159 * Smsc95xx infrastructure commands
160 */
Simon Glass527298c2015-07-07 20:53:41 -0600161static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
Simon Glass291391b2011-06-13 16:13:09 -0700162{
163 int len;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000164 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass291391b2011-06-13 16:13:09 -0700165
166 cpu_to_le32s(&data);
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000167 tmpbuf[0] = data;
Simon Glass291391b2011-06-13 16:13:09 -0700168
Simon Glass527298c2015-07-07 20:53:41 -0600169 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
170 USB_VENDOR_REQUEST_WRITE_REGISTER,
171 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
172 0, index, tmpbuf, sizeof(data),
173 USB_CTRL_SET_TIMEOUT);
Simon Glass291391b2011-06-13 16:13:09 -0700174 if (len != sizeof(data)) {
175 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
176 index, data, len);
Simon Glass25a9e982015-07-07 20:53:40 -0600177 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700178 }
179 return 0;
180}
181
Simon Glass527298c2015-07-07 20:53:41 -0600182static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
Simon Glass291391b2011-06-13 16:13:09 -0700183{
184 int len;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000185 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass291391b2011-06-13 16:13:09 -0700186
Simon Glass527298c2015-07-07 20:53:41 -0600187 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
188 USB_VENDOR_REQUEST_READ_REGISTER,
189 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
190 0, index, tmpbuf, sizeof(data),
191 USB_CTRL_GET_TIMEOUT);
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000192 *data = tmpbuf[0];
Simon Glass291391b2011-06-13 16:13:09 -0700193 if (len != sizeof(data)) {
194 debug("smsc95xx_read_reg failed: index=%d, len=%d",
195 index, len);
Simon Glass25a9e982015-07-07 20:53:40 -0600196 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700197 }
198
199 le32_to_cpus(data);
200 return 0;
201}
202
203/* Loop until the read is completed with timeout */
Simon Glass527298c2015-07-07 20:53:41 -0600204static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700205{
206 unsigned long start_time = get_timer(0);
207 u32 val;
208
209 do {
Simon Glass527298c2015-07-07 20:53:41 -0600210 smsc95xx_read_reg(udev, MII_ADDR, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700211 if (!(val & MII_BUSY_))
212 return 0;
Simon Glass527298c2015-07-07 20:53:41 -0600213 } while (get_timer(start_time) < 1000);
Simon Glass291391b2011-06-13 16:13:09 -0700214
Simon Glass25a9e982015-07-07 20:53:40 -0600215 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700216}
217
Simon Glass527298c2015-07-07 20:53:41 -0600218static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
Simon Glass291391b2011-06-13 16:13:09 -0700219{
220 u32 val, addr;
221
222 /* confirm MII not busy */
Simon Glass527298c2015-07-07 20:53:41 -0600223 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700224 debug("MII is busy in smsc95xx_mdio_read\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600225 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700226 }
227
228 /* set the address, index & direction (read from PHY) */
229 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
Simon Glass527298c2015-07-07 20:53:41 -0600230 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass291391b2011-06-13 16:13:09 -0700231
Simon Glass527298c2015-07-07 20:53:41 -0600232 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700233 debug("Timed out reading MII reg %02X\n", idx);
Simon Glass25a9e982015-07-07 20:53:40 -0600234 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700235 }
236
Simon Glass527298c2015-07-07 20:53:41 -0600237 smsc95xx_read_reg(udev, MII_DATA, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700238
239 return (u16)(val & 0xFFFF);
240}
241
Simon Glass527298c2015-07-07 20:53:41 -0600242static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
Simon Glass291391b2011-06-13 16:13:09 -0700243 int regval)
244{
245 u32 val, addr;
246
247 /* confirm MII not busy */
Simon Glass527298c2015-07-07 20:53:41 -0600248 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700249 debug("MII is busy in smsc95xx_mdio_write\n");
250 return;
251 }
252
253 val = regval;
Simon Glass527298c2015-07-07 20:53:41 -0600254 smsc95xx_write_reg(udev, MII_DATA, val);
Simon Glass291391b2011-06-13 16:13:09 -0700255
256 /* set the address, index & direction (write to PHY) */
257 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
Simon Glass527298c2015-07-07 20:53:41 -0600258 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass291391b2011-06-13 16:13:09 -0700259
Simon Glass527298c2015-07-07 20:53:41 -0600260 if (smsc95xx_phy_wait_not_busy(udev))
Simon Glass291391b2011-06-13 16:13:09 -0700261 debug("Timed out writing MII reg %02X\n", idx);
262}
263
Simon Glass527298c2015-07-07 20:53:41 -0600264static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700265{
266 unsigned long start_time = get_timer(0);
267 u32 val;
268
269 do {
Simon Glass527298c2015-07-07 20:53:41 -0600270 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700271 if (!(val & E2P_CMD_BUSY_))
272 return 0;
273 udelay(40);
274 } while (get_timer(start_time) < 1 * 1000 * 1000);
275
276 debug("EEPROM is busy\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600277 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700278}
279
Simon Glass527298c2015-07-07 20:53:41 -0600280static int smsc95xx_wait_eeprom(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700281{
282 unsigned long start_time = get_timer(0);
283 u32 val;
284
285 do {
Simon Glass527298c2015-07-07 20:53:41 -0600286 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700287 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
288 break;
289 udelay(40);
290 } while (get_timer(start_time) < 1 * 1000 * 1000);
291
292 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
293 debug("EEPROM read operation timeout\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600294 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700295 }
296 return 0;
297}
298
Simon Glass527298c2015-07-07 20:53:41 -0600299static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
Simon Glass291391b2011-06-13 16:13:09 -0700300 u8 *data)
301{
302 u32 val;
303 int i, ret;
304
Simon Glass527298c2015-07-07 20:53:41 -0600305 ret = smsc95xx_eeprom_confirm_not_busy(udev);
Simon Glass291391b2011-06-13 16:13:09 -0700306 if (ret)
307 return ret;
308
309 for (i = 0; i < length; i++) {
310 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
Simon Glass527298c2015-07-07 20:53:41 -0600311 smsc95xx_write_reg(udev, E2P_CMD, val);
Simon Glass291391b2011-06-13 16:13:09 -0700312
Simon Glass527298c2015-07-07 20:53:41 -0600313 ret = smsc95xx_wait_eeprom(udev);
Simon Glass291391b2011-06-13 16:13:09 -0700314 if (ret < 0)
315 return ret;
316
Simon Glass527298c2015-07-07 20:53:41 -0600317 smsc95xx_read_reg(udev, E2P_DATA, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700318 data[i] = val & 0xFF;
319 offset++;
320 }
321 return 0;
322}
323
324/*
325 * mii_nway_restart - restart NWay (autonegotiation) for this interface
326 *
327 * Returns 0 on success, negative on error.
328 */
Simon Glass527298c2015-07-07 20:53:41 -0600329static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
Simon Glass291391b2011-06-13 16:13:09 -0700330{
331 int bmcr;
332 int r = -1;
333
334 /* if autoneg is off, it's an error */
Simon Glass527298c2015-07-07 20:53:41 -0600335 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
Simon Glass291391b2011-06-13 16:13:09 -0700336
337 if (bmcr & BMCR_ANENABLE) {
338 bmcr |= BMCR_ANRESTART;
Simon Glass527298c2015-07-07 20:53:41 -0600339 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
Simon Glass291391b2011-06-13 16:13:09 -0700340 r = 0;
341 }
342 return r;
343}
344
Simon Glass527298c2015-07-07 20:53:41 -0600345static int smsc95xx_phy_initialize(struct usb_device *udev,
346 struct ueth_data *dev)
Simon Glass291391b2011-06-13 16:13:09 -0700347{
Simon Glass527298c2015-07-07 20:53:41 -0600348 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
349 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
350 ADVERTISE_ALL | ADVERTISE_CSMA |
351 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Simon Glass291391b2011-06-13 16:13:09 -0700352
353 /* read to clear */
Simon Glass527298c2015-07-07 20:53:41 -0600354 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
Simon Glass291391b2011-06-13 16:13:09 -0700355
Simon Glass527298c2015-07-07 20:53:41 -0600356 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
357 PHY_INT_MASK_DEFAULT_);
358 mii_nway_restart(udev, dev);
Simon Glass291391b2011-06-13 16:13:09 -0700359
360 debug("phy initialised succesfully\n");
361 return 0;
362}
363
Simon Glass527298c2015-07-07 20:53:41 -0600364static int smsc95xx_init_mac_address(unsigned char *enetaddr,
365 struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700366{
Simon Glass527298c2015-07-07 20:53:41 -0600367 int ret;
368
Simon Glass291391b2011-06-13 16:13:09 -0700369 /* try reading mac address from EEPROM */
Simon Glass527298c2015-07-07 20:53:41 -0600370 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
371 if (ret)
372 return ret;
373
374 if (is_valid_ethaddr(enetaddr)) {
375 /* eeprom values are valid so use them */
376 debug("MAC address read from EEPROM\n");
377 return 0;
Simon Glass291391b2011-06-13 16:13:09 -0700378 }
379
380 /*
381 * No eeprom, or eeprom values are invalid. Generating a random MAC
382 * address is not safe. Just return an error.
383 */
Simon Glass25a9e982015-07-07 20:53:40 -0600384 debug("Invalid MAC address read from EEPROM\n");
385
386 return -ENXIO;
Simon Glass291391b2011-06-13 16:13:09 -0700387}
388
Simon Glass527298c2015-07-07 20:53:41 -0600389static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
390 struct smsc95xx_private *priv,
391 unsigned char *enetaddr)
Simon Glass291391b2011-06-13 16:13:09 -0700392{
Simon Glass527298c2015-07-07 20:53:41 -0600393 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
394 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
Simon Glass291391b2011-06-13 16:13:09 -0700395 int ret;
396
397 /* set hardware address */
398 debug("** %s()\n", __func__);
Simon Glass527298c2015-07-07 20:53:41 -0600399 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
Wolfgang Grandegger0d9679e2011-11-14 23:19:15 +0000400 if (ret < 0)
Simon Glass291391b2011-06-13 16:13:09 -0700401 return ret;
Simon Glass291391b2011-06-13 16:13:09 -0700402
Simon Glass527298c2015-07-07 20:53:41 -0600403 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
Simon Glass291391b2011-06-13 16:13:09 -0700404 if (ret < 0)
405 return ret;
Wolfgang Grandegger0d9679e2011-11-14 23:19:15 +0000406
Simon Glass527298c2015-07-07 20:53:41 -0600407 debug("MAC %pM\n", enetaddr);
Lucas Stache1dbdf92012-08-22 11:04:57 +0000408 priv->have_hwaddr = 1;
Simon Glass527298c2015-07-07 20:53:41 -0600409
Simon Glass291391b2011-06-13 16:13:09 -0700410 return 0;
411}
412
413/* Enable or disable Tx & Rx checksum offload engines */
Simon Glass527298c2015-07-07 20:53:41 -0600414static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
415 int use_rx_csum)
Simon Glass291391b2011-06-13 16:13:09 -0700416{
417 u32 read_buf;
Simon Glass527298c2015-07-07 20:53:41 -0600418 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700419 if (ret < 0)
420 return ret;
421
422 if (use_tx_csum)
423 read_buf |= Tx_COE_EN_;
424 else
425 read_buf &= ~Tx_COE_EN_;
426
427 if (use_rx_csum)
428 read_buf |= Rx_COE_EN_;
429 else
430 read_buf &= ~Rx_COE_EN_;
431
Simon Glass527298c2015-07-07 20:53:41 -0600432 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700433 if (ret < 0)
434 return ret;
435
436 debug("COE_CR = 0x%08x\n", read_buf);
437 return 0;
438}
439
Simon Glass527298c2015-07-07 20:53:41 -0600440static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700441{
442 /* No multicast in u-boot */
Lucas Stache1dbdf92012-08-22 11:04:57 +0000443 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
Simon Glass291391b2011-06-13 16:13:09 -0700444}
445
446/* starts the TX path */
Simon Glass527298c2015-07-07 20:53:41 -0600447static void smsc95xx_start_tx_path(struct usb_device *udev,
448 struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700449{
450 u32 reg_val;
451
452 /* Enable Tx at MAC */
Lucas Stache1dbdf92012-08-22 11:04:57 +0000453 priv->mac_cr |= MAC_CR_TXEN_;
Simon Glass291391b2011-06-13 16:13:09 -0700454
Simon Glass527298c2015-07-07 20:53:41 -0600455 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700456
457 /* Enable Tx at SCSRs */
458 reg_val = TX_CFG_ON_;
Simon Glass527298c2015-07-07 20:53:41 -0600459 smsc95xx_write_reg(udev, TX_CFG, reg_val);
Simon Glass291391b2011-06-13 16:13:09 -0700460}
461
462/* Starts the Receive path */
Simon Glass527298c2015-07-07 20:53:41 -0600463static void smsc95xx_start_rx_path(struct usb_device *udev,
464 struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700465{
Lucas Stache1dbdf92012-08-22 11:04:57 +0000466 priv->mac_cr |= MAC_CR_RXEN_;
Simon Glass527298c2015-07-07 20:53:41 -0600467 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700468}
469
Simon Glass527298c2015-07-07 20:53:41 -0600470static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
471 struct smsc95xx_private *priv,
472 unsigned char *enetaddr)
Simon Glass291391b2011-06-13 16:13:09 -0700473{
474 int ret;
475 u32 write_buf;
476 u32 read_buf;
477 u32 burst_cap;
478 int timeout;
Simon Glass291391b2011-06-13 16:13:09 -0700479#define TIMEOUT_RESOLUTION 50 /* ms */
480 int link_detected;
481
482 debug("** %s()\n", __func__);
483 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
484
485 write_buf = HW_CFG_LRST_;
Simon Glass527298c2015-07-07 20:53:41 -0600486 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700487 if (ret < 0)
488 return ret;
489
490 timeout = 0;
491 do {
Simon Glass527298c2015-07-07 20:53:41 -0600492 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700493 if (ret < 0)
494 return ret;
495 udelay(10 * 1000);
496 timeout++;
497 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
498
499 if (timeout >= 100) {
500 debug("timeout waiting for completion of Lite Reset\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600501 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700502 }
503
504 write_buf = PM_CTL_PHY_RST_;
Simon Glass527298c2015-07-07 20:53:41 -0600505 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700506 if (ret < 0)
507 return ret;
508
509 timeout = 0;
510 do {
Simon Glass527298c2015-07-07 20:53:41 -0600511 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700512 if (ret < 0)
513 return ret;
514 udelay(10 * 1000);
515 timeout++;
516 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
517 if (timeout >= 100) {
518 debug("timeout waiting for PHY Reset\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600519 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700520 }
Simon Glass527298c2015-07-07 20:53:41 -0600521 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
522 0)
Lucas Stache1dbdf92012-08-22 11:04:57 +0000523 priv->have_hwaddr = 1;
524 if (!priv->have_hwaddr) {
Simon Glass291391b2011-06-13 16:13:09 -0700525 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600526 return -EADDRNOTAVAIL;
Simon Glass291391b2011-06-13 16:13:09 -0700527 }
Simon Glass527298c2015-07-07 20:53:41 -0600528 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
Simon Glass25a9e982015-07-07 20:53:40 -0600529 if (ret < 0)
530 return ret;
Simon Glass291391b2011-06-13 16:13:09 -0700531
Simon Glass527298c2015-07-07 20:53:41 -0600532 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700533 if (ret < 0)
534 return ret;
535 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
536
537 read_buf |= HW_CFG_BIR_;
Simon Glass527298c2015-07-07 20:53:41 -0600538 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700539 if (ret < 0)
540 return ret;
541
Simon Glass527298c2015-07-07 20:53:41 -0600542 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700543 if (ret < 0)
544 return ret;
545 debug("Read Value from HW_CFG after writing "
546 "HW_CFG_BIR_: 0x%08x\n", read_buf);
547
548#ifdef TURBO_MODE
549 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
550 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000551 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700552 } else {
553 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000554 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700555 }
556#else
557 burst_cap = 0;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000558 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700559#endif
Lucas Stache1dbdf92012-08-22 11:04:57 +0000560 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
Simon Glass291391b2011-06-13 16:13:09 -0700561
Simon Glass527298c2015-07-07 20:53:41 -0600562 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
Simon Glass291391b2011-06-13 16:13:09 -0700563 if (ret < 0)
564 return ret;
565
Simon Glass527298c2015-07-07 20:53:41 -0600566 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700567 if (ret < 0)
568 return ret;
569 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
570
571 read_buf = DEFAULT_BULK_IN_DELAY;
Simon Glass527298c2015-07-07 20:53:41 -0600572 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700573 if (ret < 0)
574 return ret;
575
Simon Glass527298c2015-07-07 20:53:41 -0600576 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700577 if (ret < 0)
578 return ret;
579 debug("Read Value from BULK_IN_DLY after writing: "
580 "0x%08x\n", read_buf);
581
Simon Glass527298c2015-07-07 20:53:41 -0600582 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700583 if (ret < 0)
584 return ret;
585 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
586
587#ifdef TURBO_MODE
588 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
589#endif
590 read_buf &= ~HW_CFG_RXDOFF_;
591
592#define NET_IP_ALIGN 0
593 read_buf |= NET_IP_ALIGN << 9;
594
Simon Glass527298c2015-07-07 20:53:41 -0600595 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700596 if (ret < 0)
597 return ret;
598
Simon Glass527298c2015-07-07 20:53:41 -0600599 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700600 if (ret < 0)
601 return ret;
602 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
603
604 write_buf = 0xFFFFFFFF;
Simon Glass527298c2015-07-07 20:53:41 -0600605 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700606 if (ret < 0)
607 return ret;
608
Simon Glass527298c2015-07-07 20:53:41 -0600609 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700610 if (ret < 0)
611 return ret;
612 debug("ID_REV = 0x%08x\n", read_buf);
613
Suriyan Ramasami98f686c2013-10-07 20:30:58 -0700614 /* Configure GPIO pins as LED outputs */
615 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
616 LED_GPIO_CFG_FDX_LED;
Simon Glass527298c2015-07-07 20:53:41 -0600617 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
Suriyan Ramasami98f686c2013-10-07 20:30:58 -0700618 if (ret < 0)
619 return ret;
620 debug("LED_GPIO_CFG set\n");
621
Simon Glass291391b2011-06-13 16:13:09 -0700622 /* Init Tx */
623 write_buf = 0;
Simon Glass527298c2015-07-07 20:53:41 -0600624 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700625 if (ret < 0)
626 return ret;
627
628 read_buf = AFC_CFG_DEFAULT;
Simon Glass527298c2015-07-07 20:53:41 -0600629 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700630 if (ret < 0)
631 return ret;
632
Simon Glass527298c2015-07-07 20:53:41 -0600633 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700634 if (ret < 0)
635 return ret;
636
637 /* Init Rx. Set Vlan */
638 write_buf = (u32)ETH_P_8021Q;
Simon Glass527298c2015-07-07 20:53:41 -0600639 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700640 if (ret < 0)
641 return ret;
642
643 /* Disable checksum offload engines */
Simon Glass527298c2015-07-07 20:53:41 -0600644 ret = smsc95xx_set_csums(udev, 0, 0);
Simon Glass291391b2011-06-13 16:13:09 -0700645 if (ret < 0) {
646 debug("Failed to set csum offload: %d\n", ret);
647 return ret;
648 }
Simon Glass527298c2015-07-07 20:53:41 -0600649 smsc95xx_set_multicast(priv);
Simon Glass291391b2011-06-13 16:13:09 -0700650
Simon Glass527298c2015-07-07 20:53:41 -0600651 ret = smsc95xx_phy_initialize(udev, dev);
Simon Glass25a9e982015-07-07 20:53:40 -0600652 if (ret < 0)
653 return ret;
Simon Glass527298c2015-07-07 20:53:41 -0600654 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700655 if (ret < 0)
656 return ret;
657
658 /* enable PHY interrupts */
659 read_buf |= INT_EP_CTL_PHY_INT_;
660
Simon Glass527298c2015-07-07 20:53:41 -0600661 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700662 if (ret < 0)
663 return ret;
664
Simon Glass527298c2015-07-07 20:53:41 -0600665 smsc95xx_start_tx_path(udev, priv);
666 smsc95xx_start_rx_path(udev, priv);
Simon Glass291391b2011-06-13 16:13:09 -0700667
668 timeout = 0;
669 do {
Simon Glass527298c2015-07-07 20:53:41 -0600670 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
Simon Glass291391b2011-06-13 16:13:09 -0700671 & BMSR_LSTATUS;
672 if (!link_detected) {
673 if (timeout == 0)
674 printf("Waiting for Ethernet connection... ");
675 udelay(TIMEOUT_RESOLUTION * 1000);
676 timeout += TIMEOUT_RESOLUTION;
677 }
678 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
679 if (link_detected) {
680 if (timeout != 0)
681 printf("done.\n");
682 } else {
683 printf("unable to connect.\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600684 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700685 }
686 return 0;
687}
688
Simon Glass527298c2015-07-07 20:53:41 -0600689static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
Simon Glass291391b2011-06-13 16:13:09 -0700690{
Simon Glass291391b2011-06-13 16:13:09 -0700691 int err;
692 int actual_len;
693 u32 tx_cmd_a;
694 u32 tx_cmd_b;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000695 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
696 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
Simon Glass291391b2011-06-13 16:13:09 -0700697
698 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
699 if (length > PKTSIZE)
Simon Glass25a9e982015-07-07 20:53:40 -0600700 return -ENOSPC;
Simon Glass291391b2011-06-13 16:13:09 -0700701
702 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
703 tx_cmd_b = (u32)length;
704 cpu_to_le32s(&tx_cmd_a);
705 cpu_to_le32s(&tx_cmd_b);
706
707 /* prepend cmd_a and cmd_b */
708 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
709 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
710 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
711 length);
712 err = usb_bulk_msg(dev->pusb_dev,
713 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
714 (void *)msg,
715 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
716 &actual_len,
717 USB_BULK_SEND_TIMEOUT);
718 debug("Tx: len = %u, actual = %u, err = %d\n",
719 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
720 actual_len, err);
Simon Glass527298c2015-07-07 20:53:41 -0600721
Simon Glass291391b2011-06-13 16:13:09 -0700722 return err;
723}
724
Simon Glass0990fcb2015-07-07 20:53:42 -0600725#ifndef CONFIG_DM_ETH
Simon Glass527298c2015-07-07 20:53:41 -0600726/*
727 * Smsc95xx callbacks
728 */
729static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
730{
731 struct ueth_data *dev = (struct ueth_data *)eth->priv;
732 struct usb_device *udev = dev->pusb_dev;
733 struct smsc95xx_private *priv =
734 (struct smsc95xx_private *)dev->dev_priv;
735
736 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
737}
738
739static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
740{
741 struct ueth_data *dev = (struct ueth_data *)eth->priv;
742
743 return smsc95xx_send_common(dev, packet, length);
744}
745
Simon Glass291391b2011-06-13 16:13:09 -0700746static int smsc95xx_recv(struct eth_device *eth)
747{
748 struct ueth_data *dev = (struct ueth_data *)eth->priv;
Simon Glassd62a1dc2015-07-07 20:53:39 -0600749 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
Simon Glass291391b2011-06-13 16:13:09 -0700750 unsigned char *buf_ptr;
751 int err;
752 int actual_len;
753 u32 packet_len;
754 int cur_buf_align;
755
756 debug("** %s()\n", __func__);
757 err = usb_bulk_msg(dev->pusb_dev,
Simon Glass527298c2015-07-07 20:53:41 -0600758 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
759 (void *)recv_buf, RX_URB_SIZE, &actual_len,
760 USB_BULK_RECV_TIMEOUT);
Simon Glassd62a1dc2015-07-07 20:53:39 -0600761 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
Simon Glass291391b2011-06-13 16:13:09 -0700762 actual_len, err);
763 if (err != 0) {
764 debug("Rx: failed to receive\n");
Simon Glass527298c2015-07-07 20:53:41 -0600765 return -err;
Simon Glass291391b2011-06-13 16:13:09 -0700766 }
Simon Glassd62a1dc2015-07-07 20:53:39 -0600767 if (actual_len > RX_URB_SIZE) {
Simon Glass291391b2011-06-13 16:13:09 -0700768 debug("Rx: received too many bytes %d\n", actual_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600769 return -ENOSPC;
Simon Glass291391b2011-06-13 16:13:09 -0700770 }
771
772 buf_ptr = recv_buf;
773 while (actual_len > 0) {
774 /*
775 * 1st 4 bytes contain the length of the actual data plus error
776 * info. Extract data length.
777 */
778 if (actual_len < sizeof(packet_len)) {
779 debug("Rx: incomplete packet length\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600780 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700781 }
782 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
783 le32_to_cpus(&packet_len);
784 if (packet_len & RX_STS_ES_) {
785 debug("Rx: Error header=%#x", packet_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600786 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700787 }
788 packet_len = ((packet_len & RX_STS_FL_) >> 16);
789
790 if (packet_len > actual_len - sizeof(packet_len)) {
791 debug("Rx: too large packet: %d\n", packet_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600792 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700793 }
794
795 /* Notify net stack */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500796 net_process_received_packet(buf_ptr + sizeof(packet_len),
797 packet_len - 4);
Simon Glass291391b2011-06-13 16:13:09 -0700798
799 /* Adjust for next iteration */
800 actual_len -= sizeof(packet_len) + packet_len;
801 buf_ptr += sizeof(packet_len) + packet_len;
802 cur_buf_align = (int)buf_ptr - (int)recv_buf;
803
804 if (cur_buf_align & 0x03) {
805 int align = 4 - (cur_buf_align & 0x03);
806
807 actual_len -= align;
808 buf_ptr += align;
809 }
810 }
811 return err;
812}
813
814static void smsc95xx_halt(struct eth_device *eth)
815{
816 debug("** %s()\n", __func__);
817}
818
Simon Glass527298c2015-07-07 20:53:41 -0600819static int smsc95xx_write_hwaddr(struct eth_device *eth)
820{
821 struct ueth_data *dev = eth->priv;
822 struct usb_device *udev = dev->pusb_dev;
823 struct smsc95xx_private *priv = dev->dev_priv;
824
825 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
826}
827
Simon Glass291391b2011-06-13 16:13:09 -0700828/*
829 * SMSC probing functions
830 */
831void smsc95xx_eth_before_probe(void)
832{
833 curr_eth_dev = 0;
834}
835
836struct smsc95xx_dongle {
837 unsigned short vendor;
838 unsigned short product;
839};
840
841static const struct smsc95xx_dongle smsc95xx_dongles[] = {
842 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
843 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
Lubomir Popove7dcece2013-04-01 04:50:55 +0000844 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
Stefan Roese2eb60902013-07-03 18:34:54 +0200845 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
Ilya Ledvich08ebd462014-03-12 10:36:31 +0200846 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
Simon Glass291391b2011-06-13 16:13:09 -0700847 { 0x0000, 0x0000 } /* END - Do not remove */
848};
849
850/* Probe to see if a new device is actually an SMSC device */
851int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
852 struct ueth_data *ss)
853{
854 struct usb_interface *iface;
855 struct usb_interface_descriptor *iface_desc;
856 int i;
857
858 /* let's examine the device now */
859 iface = &dev->config.if_desc[ifnum];
860 iface_desc = &dev->config.if_desc[ifnum].desc;
861
862 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
863 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
864 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
865 /* Found a supported dongle */
866 break;
867 }
868 if (smsc95xx_dongles[i].vendor == 0)
869 return 0;
870
871 /* At this point, we know we've got a live one */
872 debug("\n\nUSB Ethernet device detected\n");
873 memset(ss, '\0', sizeof(struct ueth_data));
874
875 /* Initialize the ueth_data structure with some useful info */
876 ss->ifnum = ifnum;
877 ss->pusb_dev = dev;
878 ss->subclass = iface_desc->bInterfaceSubClass;
879 ss->protocol = iface_desc->bInterfaceProtocol;
880
881 /*
882 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
883 * We will ignore any others.
884 */
885 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
886 /* is it an BULK endpoint? */
887 if ((iface->ep_desc[i].bmAttributes &
888 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
889 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
890 ss->ep_in =
891 iface->ep_desc[i].bEndpointAddress &
892 USB_ENDPOINT_NUMBER_MASK;
893 else
894 ss->ep_out =
895 iface->ep_desc[i].bEndpointAddress &
896 USB_ENDPOINT_NUMBER_MASK;
897 }
898
899 /* is it an interrupt endpoint? */
900 if ((iface->ep_desc[i].bmAttributes &
901 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
902 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
903 USB_ENDPOINT_NUMBER_MASK;
904 ss->irqinterval = iface->ep_desc[i].bInterval;
905 }
906 }
907 debug("Endpoints In %d Out %d Int %d\n",
908 ss->ep_in, ss->ep_out, ss->ep_int);
909
910 /* Do some basic sanity checks, and bail if we find a problem */
911 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
912 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
913 debug("Problems with device\n");
914 return 0;
915 }
916 dev->privptr = (void *)ss;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000917
918 /* alloc driver private */
919 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
920 if (!ss->dev_priv)
921 return 0;
922
Simon Glass291391b2011-06-13 16:13:09 -0700923 return 1;
924}
925
926int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
927 struct eth_device *eth)
928{
929 debug("** %s()\n", __func__);
930 if (!eth) {
931 debug("%s: missing parameter.\n", __func__);
932 return 0;
933 }
934 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
935 eth->init = smsc95xx_init;
936 eth->send = smsc95xx_send;
937 eth->recv = smsc95xx_recv;
938 eth->halt = smsc95xx_halt;
939 eth->write_hwaddr = smsc95xx_write_hwaddr;
940 eth->priv = ss;
941 return 1;
942}
Simon Glass0990fcb2015-07-07 20:53:42 -0600943#endif /* !CONFIG_DM_ETH */
944
945#ifdef CONFIG_DM_ETH
946static int smsc95xx_eth_start(struct udevice *dev)
947{
948 struct usb_device *udev = dev_get_parentdata(dev);
949 struct smsc95xx_private *priv = dev_get_priv(dev);
950 struct eth_pdata *pdata = dev_get_platdata(dev);
951
952 /* Driver-model Ethernet ensures we have this */
953 priv->have_hwaddr = 1;
954
955 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
956}
957
958void smsc95xx_eth_stop(struct udevice *dev)
959{
960 debug("** %s()\n", __func__);
961}
962
963int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
964{
965 struct smsc95xx_private *priv = dev_get_priv(dev);
966
967 return smsc95xx_send_common(&priv->ueth, packet, length);
968}
969
970int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
971{
972 struct smsc95xx_private *priv = dev_get_priv(dev);
973 struct ueth_data *ueth = &priv->ueth;
974 uint8_t *ptr;
975 int ret, len;
976 u32 packet_len;
977
978 len = usb_ether_get_rx_bytes(ueth, &ptr);
979 debug("%s: first try, len=%d\n", __func__, len);
980 if (!len) {
981 if (!(flags & ETH_RECV_CHECK_DEVICE))
982 return -EAGAIN;
983 ret = usb_ether_receive(ueth, RX_URB_SIZE);
984 if (ret == -EAGAIN)
985 return ret;
986
987 len = usb_ether_get_rx_bytes(ueth, &ptr);
988 debug("%s: second try, len=%d\n", __func__, len);
989 }
990
991 /*
992 * 1st 4 bytes contain the length of the actual data plus error info.
993 * Extract data length.
994 */
995 if (len < sizeof(packet_len)) {
996 debug("Rx: incomplete packet length\n");
997 goto err;
998 }
999 memcpy(&packet_len, ptr, sizeof(packet_len));
1000 le32_to_cpus(&packet_len);
1001 if (packet_len & RX_STS_ES_) {
1002 debug("Rx: Error header=%#x", packet_len);
1003 goto err;
1004 }
1005 packet_len = ((packet_len & RX_STS_FL_) >> 16);
1006
1007 if (packet_len > len - sizeof(packet_len)) {
1008 debug("Rx: too large packet: %d\n", packet_len);
1009 goto err;
1010 }
1011
1012 *packetp = ptr + sizeof(packet_len);
1013 return packet_len;
1014
1015err:
1016 usb_ether_advance_rxbuf(ueth, -1);
1017 return -EINVAL;
1018}
1019
1020static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1021{
1022 struct smsc95xx_private *priv = dev_get_priv(dev);
1023
1024 packet_len = ALIGN(packet_len, 4);
1025 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1026
1027 return 0;
1028}
1029
1030int smsc95xx_write_hwaddr(struct udevice *dev)
1031{
1032 struct usb_device *udev = dev_get_parentdata(dev);
1033 struct eth_pdata *pdata = dev_get_platdata(dev);
1034 struct smsc95xx_private *priv = dev_get_priv(dev);
1035
1036 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1037}
1038
1039static int smsc95xx_eth_probe(struct udevice *dev)
1040{
1041 struct smsc95xx_private *priv = dev_get_priv(dev);
1042 struct ueth_data *ueth = &priv->ueth;
1043
1044 return usb_ether_register(dev, ueth, RX_URB_SIZE);
1045}
1046
1047static const struct eth_ops smsc95xx_eth_ops = {
1048 .start = smsc95xx_eth_start,
1049 .send = smsc95xx_eth_send,
1050 .recv = smsc95xx_eth_recv,
1051 .free_pkt = smsc95xx_free_pkt,
1052 .stop = smsc95xx_eth_stop,
1053 .write_hwaddr = smsc95xx_write_hwaddr,
1054};
1055
1056U_BOOT_DRIVER(smsc95xx_eth) = {
1057 .name = "smsc95xx_eth",
1058 .id = UCLASS_ETH,
1059 .probe = smsc95xx_eth_probe,
1060 .ops = &smsc95xx_eth_ops,
1061 .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1062 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1063};
1064
1065static const struct usb_device_id smsc95xx_eth_id_table[] = {
1066 { USB_DEVICE(0x05ac, 0x1402) },
1067 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
1068 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
1069 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
1070 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
1071 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
1072 { } /* Terminating entry */
1073};
1074
1075U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
1076#endif