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wdenk3bac3512003-03-12 10:41:04 +00001/*
2**=====================================================================
3**
4** Copyright (C) 2000, 2001, 2002, 2003
5** The LEOX team <team@leox.org>, http://www.leox.org
6**
7** LEOX.org is about the development of free hardware and software resources
8** for system on chip.
9**
10** Description: U-Boot port on the LEOX's ELPT860 CPU board
11** ~~~~~~~~~~~
12**
13**=====================================================================
14**
15** This program is free software; you can redistribute it and/or
16** modify it under the terms of the GNU General Public License as
17** published by the Free Software Foundation; either version 2 of
18** the License, or (at your option) any later version.
19**
20** This program is distributed in the hope that it will be useful,
21** but WITHOUT ANY WARRANTY; without even the implied warranty of
22** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23** GNU General Public License for more details.
24**
25** You should have received a copy of the GNU General Public License
26** along with this program; if not, write to the Free Software
27** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28** MA 02111-1307 USA
29**
30**=====================================================================
31*/
32
33/*
34** Note 1: In this file, you have to provide the following functions:
35** ------
wdenkc837dcb2004-01-20 23:12:12 +000036** int board_early_init_f(void)
wdenk3bac3512003-03-12 10:41:04 +000037** int checkboard(void)
Becky Bruce9973e3c2008-06-09 16:03:40 -050038** phys_size_t initdram(int board_type)
wdenk3bac3512003-03-12 10:41:04 +000039** called from 'board_init_f()' into 'common/board.c'
40**
41** void reset_phy(void)
42** called from 'board_init_r()' into 'common/board.c'
43*/
44
45#include <common.h>
46#include <mpc8xx.h>
47
48/* ------------------------------------------------------------------------- */
49
50static long int dram_size (long int, long int *, long int);
51
52/* ------------------------------------------------------------------------- */
53
54#define _NOT_USED_ 0xFFFFFFFF
55
wdenkc83bf6a2004-01-06 22:38:14 +000056const uint init_sdram_table[] = {
57 /*
58 * Single Read. (Offset 0 in UPMA RAM)
59 */
60 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
61 0xFFFFFC04, /* last */
62 /*
63 * SDRAM Initialization (offset 5 in UPMA RAM)
64 *
65 * This is no UPM entry point. The following definition uses
66 * the remaining space to establish an initialization
67 * sequence, which is executed by a RUN command.
68 *
69 */
70 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
71 /*
72 * Burst Read. (Offset 8 in UPMA RAM)
73 */
74 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
75 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
76 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
77 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
78 /*
79 * Single Write. (Offset 18 in UPMA RAM)
80 */
81 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
82 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
83 /*
84 * Burst Write. (Offset 20 in UPMA RAM)
85 */
86 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
87 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
88 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
89 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
wdenk3bac3512003-03-12 10:41:04 +000090};
91
wdenkc83bf6a2004-01-06 22:38:14 +000092const uint sdram_table[] = {
93 /*
94 * Single Read. (Offset 0 in UPMA RAM)
95 */
96 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
97 0xFF0FFC00, /* last */
98 /*
99 * SDRAM Initialization (offset 5 in UPMA RAM)
100 *
101 * This is no UPM entry point. The following definition uses
102 * the remaining space to establish an initialization
103 * sequence, which is executed by a RUN command.
104 *
105 */
106 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
107 /*
108 * Burst Read. (Offset 8 in UPMA RAM)
109 */
110 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
111 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
112 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
113 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
114 /*
115 * Single Write. (Offset 18 in UPMA RAM)
116 */
117 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
118 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
119 _NOT_USED_,
120 /*
121 * Burst Write. (Offset 20 in UPMA RAM)
122 */
123 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
124 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
125 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
126 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
127 /*
128 * Refresh (Offset 30 in UPMA RAM)
129 */
130 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
131 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
132 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
133 /*
134 * Exception. (Offset 3c in UPMA RAM)
135 */
136 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
wdenk3bac3512003-03-12 10:41:04 +0000137};
138
139/* ------------------------------------------------------------------------- */
140
141#define CFG_PC4 0x0800
142
143#define CFG_DS1 CFG_PC4
144
145/*
146 * Very early board init code (fpga boot, etc.)
147 */
wdenkc837dcb2004-01-20 23:12:12 +0000148int board_early_init_f (void)
wdenk3bac3512003-03-12 10:41:04 +0000149{
wdenkc83bf6a2004-01-06 22:38:14 +0000150 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenk3bac3512003-03-12 10:41:04 +0000151
wdenkc83bf6a2004-01-06 22:38:14 +0000152 /*
153 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
154 */
155 immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
156 immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
157 immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
wdenk3bac3512003-03-12 10:41:04 +0000158
wdenkc83bf6a2004-01-06 22:38:14 +0000159 return (0); /* success */
wdenk3bac3512003-03-12 10:41:04 +0000160}
161
162/*
163 * Check Board Identity:
164 *
165 * Test ELPT860 ID string
166 *
167 * Return 1 if no second DRAM bank, otherwise returns 0
168 */
169
wdenkc83bf6a2004-01-06 22:38:14 +0000170int checkboard (void)
wdenk3bac3512003-03-12 10:41:04 +0000171{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200172 char *s = getenv ("serial#");
wdenk3bac3512003-03-12 10:41:04 +0000173
wdenkc83bf6a2004-01-06 22:38:14 +0000174 if (!s || strncmp (s, "ELPT860", 7))
175 printf ("### No HW ID - assuming ELPT860\n");
wdenk8bde7f72003-06-27 21:31:46 +0000176
wdenkc83bf6a2004-01-06 22:38:14 +0000177 return (0); /* success */
wdenk3bac3512003-03-12 10:41:04 +0000178}
179
180/* ------------------------------------------------------------------------- */
181
Becky Bruce9973e3c2008-06-09 16:03:40 -0500182phys_size_t initdram (int board_type)
wdenk3bac3512003-03-12 10:41:04 +0000183{
wdenkc83bf6a2004-01-06 22:38:14 +0000184 volatile immap_t *immap = (immap_t *) CFG_IMMR;
185 volatile memctl8xx_t *memctl = &immap->im_memctl;
186 long int size8, size9;
187 long int size_b0 = 0;
wdenk3bac3512003-03-12 10:41:04 +0000188
wdenkc83bf6a2004-01-06 22:38:14 +0000189 /*
190 * This sequence initializes SDRAM chips on ELPT860 board
191 */
192 upmconfig (UPMA, (uint *) init_sdram_table,
193 sizeof (init_sdram_table) / sizeof (uint));
wdenk3bac3512003-03-12 10:41:04 +0000194
wdenkc83bf6a2004-01-06 22:38:14 +0000195 memctl->memc_mptpr = 0x0200;
196 memctl->memc_mamr = 0x18002111;
wdenk3bac3512003-03-12 10:41:04 +0000197
wdenkc83bf6a2004-01-06 22:38:14 +0000198 memctl->memc_mar = 0x00000088;
199 memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
wdenk3bac3512003-03-12 10:41:04 +0000200
wdenkc83bf6a2004-01-06 22:38:14 +0000201 upmconfig (UPMA, (uint *) sdram_table,
202 sizeof (sdram_table) / sizeof (uint));
wdenk3bac3512003-03-12 10:41:04 +0000203
wdenkc83bf6a2004-01-06 22:38:14 +0000204 /*
205 * Preliminary prescaler for refresh (depends on number of
206 * banks): This value is selected for four cycles every 62.4 us
207 * with two SDRAM banks or four cycles every 31.2 us with one
208 * bank. It will be adjusted after memory sizing.
209 */
210 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
wdenk3bac3512003-03-12 10:41:04 +0000211
wdenkc83bf6a2004-01-06 22:38:14 +0000212 /*
213 * The following value is used as an address (i.e. opcode) for
214 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
215 * the port size is 32bit the SDRAM does NOT "see" the lower two
216 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
217 * MICRON SDRAMs:
218 * -> 0 00 010 0 010
219 * | | | | +- Burst Length = 4
220 * | | | +----- Burst Type = Sequential
221 * | | +------- CAS Latency = 2
222 * | +----------- Operating Mode = Standard
223 * +-------------- Write Burst Mode = Programmed Burst Length
224 */
225 memctl->memc_mar = 0x00000088;
wdenk3bac3512003-03-12 10:41:04 +0000226
wdenkc83bf6a2004-01-06 22:38:14 +0000227 /*
228 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
229 * preliminary addresses - these have to be modified after the
230 * SDRAM size has been determined.
231 */
232 memctl->memc_or1 = CFG_OR1_PRELIM;
233 memctl->memc_br1 = CFG_BR1_PRELIM;
wdenk3bac3512003-03-12 10:41:04 +0000234
wdenkc83bf6a2004-01-06 22:38:14 +0000235 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk3bac3512003-03-12 10:41:04 +0000236
wdenkc83bf6a2004-01-06 22:38:14 +0000237 udelay (200);
wdenk3bac3512003-03-12 10:41:04 +0000238
wdenkc83bf6a2004-01-06 22:38:14 +0000239 /* perform SDRAM initializsation sequence */
wdenk3bac3512003-03-12 10:41:04 +0000240
wdenkc83bf6a2004-01-06 22:38:14 +0000241 memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
242 udelay (1);
243 memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
244 udelay (1);
wdenk3bac3512003-03-12 10:41:04 +0000245
wdenkc83bf6a2004-01-06 22:38:14 +0000246 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
wdenk3bac3512003-03-12 10:41:04 +0000247
wdenk3bac3512003-03-12 10:41:04 +0000248 udelay (1000);
wdenk3bac3512003-03-12 10:41:04 +0000249
wdenkc83bf6a2004-01-06 22:38:14 +0000250 /*
251 * Check Bank 0 Memory Size for re-configuration
252 *
253 * try 8 column mode
254 */
255 size8 = dram_size (CFG_MAMR_8COL,
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200256 SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
wdenk3bac3512003-03-12 10:41:04 +0000257
wdenkc83bf6a2004-01-06 22:38:14 +0000258 udelay (1000);
wdenk8bde7f72003-06-27 21:31:46 +0000259
wdenkc83bf6a2004-01-06 22:38:14 +0000260 /*
261 * try 9 column mode
262 */
263 size9 = dram_size (CFG_MAMR_9COL,
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200264 SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
wdenk3bac3512003-03-12 10:41:04 +0000265
wdenkc83bf6a2004-01-06 22:38:14 +0000266 if (size8 < size9) { /* leave configuration at 9 columns */
267 size_b0 = size9;
268 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
269 } else { /* back to 8 columns */
wdenk8bde7f72003-06-27 21:31:46 +0000270
wdenkc83bf6a2004-01-06 22:38:14 +0000271 size_b0 = size8;
272 memctl->memc_mamr = CFG_MAMR_8COL;
273 udelay (500);
274 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
275 }
276
277 udelay (1000);
278
279 /*
280 * Adjust refresh rate depending on SDRAM type, both banks
281 * For types > 128 MBit leave it at the current (fast) rate
282 */
283 if (size_b0 < 0x02000000) {
284 /* reduce to 15.6 us (62.4 us / quad) */
285 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
286 udelay (1000);
287 }
288
289 /*
290 * Final mapping: map bigger bank first
291 */
292 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
293 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
294
295 {
296 unsigned long reg;
297
298 /* adjust refresh rate depending on SDRAM type, one bank */
299 reg = memctl->memc_mptpr;
300 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
301 memctl->memc_mptpr = reg;
302 }
303
304 udelay (10000);
305
306 return (size_b0);
wdenk3bac3512003-03-12 10:41:04 +0000307}
308
309/* ------------------------------------------------------------------------- */
310
311/*
312 * Check memory range for valid RAM. A simple memory test determines
313 * the actually available RAM size between addresses `base' and
314 * `base + maxsize'. Some (not all) hardware errors are detected:
315 * - short between address lines
316 * - short between data lines
317 */
318
wdenk8bde7f72003-06-27 21:31:46 +0000319static long int
wdenkc83bf6a2004-01-06 22:38:14 +0000320dram_size (long int mamr_value, long int *base, long int maxsize)
wdenk3bac3512003-03-12 10:41:04 +0000321{
wdenkc83bf6a2004-01-06 22:38:14 +0000322 volatile immap_t *immap = (immap_t *) CFG_IMMR;
323 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk8bde7f72003-06-27 21:31:46 +0000324
wdenkc83bf6a2004-01-06 22:38:14 +0000325 memctl->memc_mamr = mamr_value;
wdenk8bde7f72003-06-27 21:31:46 +0000326
wdenkc83bf6a2004-01-06 22:38:14 +0000327 return (get_ram_size (base, maxsize));
wdenk3bac3512003-03-12 10:41:04 +0000328}
329
330/* ------------------------------------------------------------------------- */
331
332#define CFG_PA1 0x4000
333#define CFG_PA2 0x2000
334
335#define CFG_LBKs (CFG_PA2 | CFG_PA1)
336
wdenkc83bf6a2004-01-06 22:38:14 +0000337void reset_phy (void)
wdenk3bac3512003-03-12 10:41:04 +0000338{
wdenkc83bf6a2004-01-06 22:38:14 +0000339 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenk8bde7f72003-06-27 21:31:46 +0000340
wdenkc83bf6a2004-01-06 22:38:14 +0000341 /*
342 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
343 * and no AUI loopback
344 */
345 immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
346 immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
347 immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
wdenk3bac3512003-03-12 10:41:04 +0000348}