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dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
dzu@denx.de6ca24c62006-04-21 18:30:47 +02002 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2004-2005
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10 *
11 * (C) Copyright 2006
12 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
13 *
dzu@denx.de6ca24c62006-04-21 18:30:47 +020014 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <common.h>
34#include <mpc5xxx.h>
35#include <pci.h>
36
37#ifdef CONFIG_VIDEO_SM501
38#include <sm501.h>
39#endif
40
41#if defined(CONFIG_MPC5200_DDR)
42#include "mt46v16m16-75.h"
43#else
44#include "mt48lc16m16a2-75.h"
45#endif
46
47#ifdef CONFIG_RTC_MPC5200
48#include <rtc.h>
Wolfgang Denk610cf362006-05-03 01:24:04 +020049#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +020050
51#ifdef CONFIG_PS2MULT
52void ps2mult_early_init(void);
53#endif
54
55#ifndef CFG_RAMBOOT
56static void sdram_start (int hi_addr)
57{
58 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
59
60 /* unlock mode register */
61 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
62 hi_addr_bit;
63 __asm__ volatile ("sync");
64
65 /* precharge all banks */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
67 hi_addr_bit;
68 __asm__ volatile ("sync");
69
70#if SDRAM_DDR
71 /* set mode register: extended mode */
72 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
73 __asm__ volatile ("sync");
74
75 /* set mode register: reset DLL */
76 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
77 __asm__ volatile ("sync");
78#endif
79
80 /* precharge all banks */
81 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
82 hi_addr_bit;
83 __asm__ volatile ("sync");
84
85 /* auto refresh */
86 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
87 hi_addr_bit;
88 __asm__ volatile ("sync");
89
90 /* set mode register */
91 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
92 __asm__ volatile ("sync");
93
94 /* normal operation */
95 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
96 __asm__ volatile ("sync");
97}
98#endif
99
100/*
101 * ATTENTION: Although partially referenced initdram does NOT make real use
102 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
103 * is something else than 0x00000000.
104 */
105
106#if defined(CONFIG_MPC5200)
Becky Bruce9973e3c2008-06-09 16:03:40 -0500107phys_size_t initdram (int board_type)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200108{
109 ulong dramsize = 0;
110 ulong dramsize2 = 0;
111#ifndef CFG_RAMBOOT
112 ulong test1, test2;
113
114 /* setup SDRAM chip selects */
115 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
116 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
117 __asm__ volatile ("sync");
118
119 /* setup config registers */
120 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
121 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
122 __asm__ volatile ("sync");
123
124#if SDRAM_DDR
125 /* set tap delay */
126 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
127 __asm__ volatile ("sync");
128#endif
129
130 /* find RAM size using SDRAM CS0 only */
131 sdram_start(0);
132 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
133 sdram_start(1);
134 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
135 if (test1 > test2) {
136 sdram_start(0);
137 dramsize = test1;
138 } else {
139 dramsize = test2;
140 }
141
142 /* memory smaller than 1MB is impossible */
143 if (dramsize < (1 << 20)) {
144 dramsize = 0;
145 }
146
147 /* set SDRAM CS0 size according to the amount of RAM found */
148 if (dramsize > 0) {
149 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
150 __builtin_ffs(dramsize >> 20) - 1;
151 } else {
152 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
153 }
154
155 /* let SDRAM CS1 start right after CS0 */
156 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
157
158 /* find RAM size using SDRAM CS1 only */
159 sdram_start(0);
160 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
161 sdram_start(1);
162 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
163 if (test1 > test2) {
164 sdram_start(0);
165 dramsize2 = test1;
166 } else {
167 dramsize2 = test2;
168 }
169
170 /* memory smaller than 1MB is impossible */
171 if (dramsize2 < (1 << 20)) {
172 dramsize2 = 0;
173 }
174
175 /* set SDRAM CS1 size according to the amount of RAM found */
176 if (dramsize2 > 0) {
177 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
178 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
179 } else {
180 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
181 }
182
183#else /* CFG_RAMBOOT */
184
185 /* retrieve size of memory connected to SDRAM CS0 */
186 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
187 if (dramsize >= 0x13) {
188 dramsize = (1 << (dramsize - 0x13)) << 20;
189 } else {
190 dramsize = 0;
191 }
192
193 /* retrieve size of memory connected to SDRAM CS1 */
194 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
195 if (dramsize2 >= 0x13) {
196 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
197 } else {
198 dramsize2 = 0;
199 }
200
201#endif /* CFG_RAMBOOT */
202
203 return dramsize;
204}
205
206#elif defined(CONFIG_MGT5100)
207
Becky Bruce9973e3c2008-06-09 16:03:40 -0500208phys_size_t initdram (int board_type)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200209{
210 ulong dramsize = 0;
211#ifndef CFG_RAMBOOT
212 ulong test1, test2;
213
214 /* setup and enable SDRAM chip selects */
215 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
216 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
217 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
218 __asm__ volatile ("sync");
219
220 /* setup config registers */
221 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
222 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
223
224 /* address select register */
225 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
226 __asm__ volatile ("sync");
227
228 /* find RAM size */
229 sdram_start(0);
230 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
231 sdram_start(1);
232 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
233 if (test1 > test2) {
234 sdram_start(0);
235 dramsize = test1;
236 } else {
237 dramsize = test2;
238 }
239
240 /* set SDRAM end address according to size */
241 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
242
243#else /* CFG_RAMBOOT */
244
245 /* Retrieve amount of SDRAM available */
246 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
247
248#endif /* CFG_RAMBOOT */
249
250 return dramsize;
251}
252
253#else
254#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
255#endif
256
257int checkboard (void)
258{
259#if defined (CONFIG_TQM5200)
260 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
261#endif
262
263#if defined (CONFIG_BC3450)
264 puts ("Dev: GERSYS BC3450\n");
265#endif
266
267 return 0;
268}
269
270void flash_preinit(void)
271{
272 /*
273 * Now, when we are in RAM, enable flash write
274 * access for detection process.
275 * Note that CS_BOOT cannot be cleared when
276 * executing in flash.
277 */
278#if defined(CONFIG_MGT5100)
279 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
280 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
281#endif
282 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
283}
284
285
286#ifdef CONFIG_PCI
287static struct pci_controller hose;
288
289extern void pci_mpc5xxx_init(struct pci_controller *);
290
291void pci_init_board(void)
292{
293 pci_mpc5xxx_init(&hose);
294}
295#endif
296
Jon Loeliger77a31852007-07-10 10:39:10 -0500297#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200298
299void init_ide_reset (void)
300{
301 debug ("init_ide_reset\n");
302
303 /* Configure PSC1_4 as GPIO output for ATA reset */
304 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
305 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
306}
307
308void ide_set_reset (int idereset)
309{
310 debug ("ide_reset(%d)\n", idereset);
311
312 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100313 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200314 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100315 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200316 }
317}
Jon Loeliger77a31852007-07-10 10:39:10 -0500318#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200319
320#ifdef CONFIG_POST
321/*
322 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
323 * is left open, no keypress is detected.
324 */
325int post_hotkeys_pressed(void)
326{
327 struct mpc5xxx_gpio *gpio;
328
329 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
330
331 /*
332 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
333 * CODEC or UART mode. Consumer IrDA should still be possible.
334 */
335 gpio->port_config &= ~(0x07000000);
336 gpio->port_config |= 0x03000000;
337
338 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
339 gpio->simple_gpioe |= 0x20000000;
340
341 /* Configure GPIO_IRDA_1 as input */
342 gpio->simple_ddr &= ~(0x20000000);
343
344 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
345}
346#endif
347
348#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
349
350void post_word_store (ulong a)
351{
352 volatile ulong *save_addr =
353 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
354
355 *save_addr = a;
356}
357
358ulong post_word_load (void)
359{
360 volatile ulong *save_addr =
361 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
362
363 return *save_addr;
364}
365#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
366
367
368#ifdef CONFIG_BOARD_EARLY_INIT_R
369int board_early_init_r (void)
370{
371#ifdef CONFIG_RTC_MPC5200
Wolfgang Denk610cf362006-05-03 01:24:04 +0200372 struct rtc_time t;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200373
374 /* set to Wed Dec 31 19:00:00 1969 */
375 t.tm_sec = t.tm_min = 0;
376 t.tm_hour = 19;
377 t.tm_mday = 31;
378 t.tm_mon = 12;
379 t.tm_year = 1969;
380 t.tm_wday = 3;
Wolfgang Denk610cf362006-05-03 01:24:04 +0200381
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200382 rtc_set(&t);
383#endif /* CONFIG_RTC_MPC5200 */
384
385#ifdef CONFIG_PS2MULT
386 ps2mult_early_init();
387#endif /* CONFIG_PS2MULT */
388 return (0);
389}
390#endif /* CONFIG_BOARD_EARLY_INIT_R */
391
392
393int last_stage_init (void)
394{
395 /*
396 * auto scan for really existing devices and re-set chip select
397 * configuration.
398 */
399 u16 save, tmp;
400 int restore;
401
402 /*
403 * Check for SRAM and SRAM size
404 */
405
406 /* save original SRAM content */
407 save = *(volatile u16 *)CFG_CS2_START;
408 restore = 1;
409
410 /* write test pattern to SRAM */
411 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
412 __asm__ volatile ("sync");
413 /*
414 * Put a different pattern on the data lines: otherwise they may float
415 * long enough to read back what we wrote.
416 */
417 tmp = *(volatile u16 *)CFG_FLASH_BASE;
418 if (tmp == 0xA5A5)
419 puts ("!! possible error in SRAM detection\n");
420
421 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
422 /* no SRAM at all, disable cs */
423 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
424 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
425 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
426 restore = 0;
427 __asm__ volatile ("sync");
428 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
429 /* make sure that we access a mirrored address */
430 *(volatile u16 *)CFG_CS2_START = 0x1111;
431 __asm__ volatile ("sync");
432 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
433 /* SRAM size = 512 kByte */
434 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
435 0x80000);
436 __asm__ volatile ("sync");
437 puts ("SRAM: 512 kB\n");
438 }
439 else
440 puts ("!! possible error in SRAM detection\n");
441 } else {
442 puts ("SRAM: 1 MB\n");
443 }
444 /* restore origianl SRAM content */
445 if (restore) {
446 *(volatile u16 *)CFG_CS2_START = save;
447 __asm__ volatile ("sync");
448 }
449
450 /*
451 * Check for Grafic Controller
452 */
453
454 /* save origianl FB content */
455 save = *(volatile u16 *)CFG_CS1_START;
456 restore = 1;
457
458 /* write test pattern to FB memory */
459 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
460 __asm__ volatile ("sync");
461 /*
462 * Put a different pattern on the data lines: otherwise they may float
463 * long enough to read back what we wrote.
464 */
465 tmp = *(volatile u16 *)CFG_FLASH_BASE;
466 if (tmp == 0xA5A5)
467 puts ("!! possible error in grafic controller detection\n");
468
469 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
470 /* no grafic controller at all, disable cs */
471 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
472 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
473 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
474 restore = 0;
475 __asm__ volatile ("sync");
476 } else {
477 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
478 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200479 /* restore origianl FB content */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200480 if (restore) {
481 *(volatile u16 *)CFG_CS1_START = save;
482 __asm__ volatile ("sync");
483 }
484
485 return 0;
486}
487
488#ifdef CONFIG_VIDEO_SM501
489
Wolfgang Denk610cf362006-05-03 01:24:04 +0200490#define DISPLAY_WIDTH 640
491#define DISPLAY_HEIGHT 480
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200492
493#ifdef CONFIG_VIDEO_SM501_8BPP
494#error CONFIG_VIDEO_SM501_8BPP not supported.
495#endif /* CONFIG_VIDEO_SM501_8BPP */
496
497#ifdef CONFIG_VIDEO_SM501_16BPP
498#error CONFIG_VIDEO_SM501_16BPP not supported.
499#endif /* CONFIG_VIDEO_SM501_16BPP */
500
501#ifdef CONFIG_VIDEO_SM501_32BPP
502static const SMI_REGS init_regs [] =
503{
504#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
505 /* FP only */
506 {0x00004, 0x0},
507 {0x00048, 0x00021807},
508 {0x0004C, 0x091a0a01},
509 {0x00054, 0x1},
510 {0x00040, 0x00021807},
511 {0x00044, 0x091a0a01},
512 {0x00054, 0x0},
513 {0x80000, 0x01013106},
514 {0x80004, 0xc428bb17},
515 {0x80000, 0x03013106},
516 {0x8000C, 0x00000000},
517 {0x80010, 0x0a000a00},
518 {0x80014, 0x02800000},
519 {0x80018, 0x01e00000},
520 {0x8001C, 0x00000000},
521 {0x80020, 0x01e00280},
522 {0x80024, 0x02fa027f},
523 {0x80028, 0x004a028b},
524 {0x8002C, 0x020c01df},
525 {0x80030, 0x000201e9},
526 {0x80200, 0x00010200},
527 {0x80000, 0x0f013106},
528#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
529 /* CRT only */
530 {0x00004, 0x0},
531 {0x00048, 0x00021807},
532 {0x0004C, 0x10090a01},
533 {0x00054, 0x1},
534 {0x00040, 0x00021807},
535 {0x00044, 0x10090a01},
536 {0x00054, 0x0},
537 {0x80200, 0x00010000},
538 {0x80204, 0x0},
539 {0x80208, 0x0A000A00},
540 {0x8020C, 0x02fa027f},
541 {0x80210, 0x004a028b},
542 {0x80214, 0x020c01df},
543 {0x80218, 0x000201e9},
544 {0x80200, 0x00013306},
545#else /* panel + CRT */
546 {0x00004, 0x0},
547 {0x00048, 0x00021807},
548 {0x0004C, 0x091a0a01},
549 {0x00054, 0x1},
550 {0x00040, 0x00021807},
551 {0x00044, 0x091a0a01},
552 {0x00054, 0x0},
553 {0x80000, 0x0f013106},
554 {0x80004, 0xc428bb17},
555 {0x8000C, 0x00000000},
556 {0x80010, 0x0a000a00},
557 {0x80014, 0x02800000},
558 {0x80018, 0x01e00000},
559 {0x8001C, 0x00000000},
560 {0x80020, 0x01e00280},
561 {0x80024, 0x02fa027f},
562 {0x80028, 0x004a028b},
563 {0x8002C, 0x020c01df},
564 {0x80030, 0x000201e9},
565 {0x80200, 0x00010000},
566#endif
567 {0, 0}
568};
569#endif /* CONFIG_VIDEO_SM501_32BPP */
570
571#ifdef CONFIG_CONSOLE_EXTRA_INFO
572/*
573 * Return text to be printed besides the logo.
574 */
575void video_get_info_str (int line_number, char *info)
576{
577 if (line_number == 1) {
578#if defined (CONFIG_TQM5200)
579 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
580#else
581#error No supported board selected
582#endif /* CONFIG_TQM5200 */
583
584#if defined (CONFIG_BC3450)
585 } else if (line_number == 2) {
586 strcpy (info, " Dev: GERSYS BC3450");
587#endif /* CONFIG_BC3450 */
588 }
589 else {
590 info [0] = '\0';
591 }
592}
593#endif
594
595/*
596 * Returns SM501 register base address. First thing called in the
597 * driver. Checks if SM501 is physically present.
598 */
599unsigned int board_video_init (void)
600{
601 u16 save, tmp;
602 int restore, ret;
603
604 /*
605 * Check for Grafic Controller
606 */
607
608 /* save origianl FB content */
609 save = *(volatile u16 *)CFG_CS1_START;
610 restore = 1;
611
612 /* write test pattern to FB memory */
613 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
614 __asm__ volatile ("sync");
615 /*
616 * Put a different pattern on the data lines: otherwise they may float
617 * long enough to read back what we wrote.
618 */
619 tmp = *(volatile u16 *)CFG_FLASH_BASE;
620 if (tmp == 0xA5A5)
621 puts ("!! possible error in grafic controller detection\n");
622
623 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
624 /* no grafic controller found */
625 restore = 0;
626 ret = 0;
627 } else {
628 ret = SM501_MMIO_BASE;
629 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200630
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200631 if (restore) {
632 *(volatile u16 *)CFG_CS1_START = save;
633 __asm__ volatile ("sync");
634 }
635 return ret;
636}
637
638/*
639 * Returns SM501 framebuffer address
640 */
641unsigned int board_video_get_fb (void)
642{
643 return SM501_FB_BASE;
644}
645
646/*
647 * Called after initializing the SM501 and before clearing the screen.
648 */
649void board_validate_screen (unsigned int base)
650{
651}
652
653/*
654 * Return a pointer to the initialization sequence.
655 */
656const SMI_REGS *board_get_regs (void)
657{
658 return init_regs;
659}
660
661int board_get_width (void)
662{
663 return DISPLAY_WIDTH;
664}
665
666int board_get_height (void)
667{
668 return DISPLAY_HEIGHT;
669}
670
671#endif /* CONFIG_VIDEO_SM501 */