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Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02001/*
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <asm/processor.h>
30
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010031
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020032#ifndef CFG_RAMBOOT
33static void sdram_start(int hi_addr)
34{
35 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
36
37 /* unlock mode register */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010038 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020039 __asm__ volatile ("sync");
40
41 /* precharge all banks */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010042 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020043 __asm__ volatile ("sync");
44
45#if SDRAM_DDR
46 /* set mode register: extended mode */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010047 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020048 __asm__ volatile ("sync");
49
50 /* set mode register: reset DLL */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010051 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020052 __asm__ volatile ("sync");
53#endif /* SDRAM_DDR */
54
55 /* precharge all banks */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010056 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020057 __asm__ volatile ("sync");
58
59 /* auto refresh */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010060 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020061 __asm__ volatile ("sync");
62
63 /* set mode register */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010064 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020065 __asm__ volatile ("sync");
66
67 /* normal operation */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010068 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020069 __asm__ volatile ("sync");
70}
71#endif /* !CFG_RAMBOOT */
72
73
Becky Bruce9973e3c2008-06-09 16:03:40 -050074phys_size_t initdram(int board_type)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020075{
76 ulong dramsize = 0;
77 ulong dramsize2 = 0;
78 uint svr, pvr;
79
80#ifndef CFG_RAMBOOT
81 ulong test1, test2;
82
83 /* setup SDRAM chip selects */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010084 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
85 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020086 __asm__ volatile ("sync");
87
88 /* setup config registers */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010089 *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
90 *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020091 __asm__ volatile ("sync");
92
93#if SDRAM_DDR
94 /* set tap delay */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +010095 *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020096 __asm__ volatile ("sync");
97#endif /* SDRAM_DDR */
98
99 /* find RAM size using SDRAM CS0 only */
100 sdram_start(0);
101 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
102 sdram_start(1);
103 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
104 if (test1 > test2) {
105 sdram_start(0);
106 dramsize = test1;
107 } else
108 dramsize = test2;
109
110 /* memory smaller than 1MB is impossible */
111 if (dramsize < (1 << 20))
112 dramsize = 0;
113
114 /* set SDRAM CS0 size according to the amount of RAM found */
115 if (dramsize > 0)
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100116 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200117 else
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100118 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200119
120 /* let SDRAM CS1 start right after CS0 */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100121 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200122
123 /* find RAM size using SDRAM CS1 only */
124 if (!dramsize)
125 sdram_start(0);
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100126 test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200127 if (!dramsize) {
128 sdram_start(1);
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100129 test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200130 }
131 if (test1 > test2) {
132 sdram_start(0);
133 dramsize2 = test1;
134 } else
135 dramsize2 = test2;
136
137 /* memory smaller than 1MB is impossible */
138 if (dramsize2 < (1 << 20))
139 dramsize2 = 0;
140
141 /* set SDRAM CS1 size according to the amount of RAM found */
142 if (dramsize2 > 0)
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100143 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200144 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
145 else
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100146 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200147
148#else /* CFG_RAMBOOT */
149
150 /* retrieve size of memory connected to SDRAM CS0 */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100151 dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200152 if (dramsize >= 0x13)
153 dramsize = (1 << (dramsize - 0x13)) << 20;
154 else
155 dramsize = 0;
156
157 /* retrieve size of memory connected to SDRAM CS1 */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100158 dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200159 if (dramsize2 >= 0x13)
160 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
161 else
162 dramsize2 = 0;
163
164#endif /* CFG_RAMBOOT */
165
166 /*
167 * On MPC5200B we need to set the special configuration delay in the
168 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
169 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
170 *
171 * "The SDelay should be written to a value of 0x00000004. It is
172 * required to account for changes caused by normal wafer processing
173 * parameters."
174 */
175 svr = get_svr();
176 pvr = get_pvr();
177 if ((SVR_MJREV(svr) >= 2) &&
178 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
179
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100180 *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200181 __asm__ volatile ("sync");
182 }
183
184 return dramsize + dramsize2;
185}
186
187
188int checkboard (void)
189{
190 puts("Board: MarelV38B\n");
191 return 0;
192}
193
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100194int board_early_init_f(void)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200195{
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100196#ifdef CONFIG_HW_WATCHDOG
197 /*
198 * Enable and configure the direction (output) of PSC3_9 - watchdog
199 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
200 * Manual.
201 */
202 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
203 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
204#endif /* CONFIG_HW_WATCHDOG */
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100205 return 0;
206}
207
208int board_early_init_r(void)
209{
210 /*
211 * Now, when we are in RAM, enable flash write access for the
212 * detection process. Note that CS_BOOT cannot be cleared when
213 * executing in flash.
214 */
215 *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100216
217 /*
218 * Enable GPIO_WKUP_7 to "read the status of the actual power
219 * situation". Default direction is input, so no need to set it
220 * explicitly.
221 */
222 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200223 return 0;
224}
225
226
Jon Loeligerd39b5742007-07-10 10:48:22 -0500227#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200228void init_ide_reset(void)
229{
230 debug("init_ide_reset\n");
231
232 /* Configure PSC1_4 as GPIO output for ATA reset */
233 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100234 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200235 /* Deassert reset */
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100236 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200237}
238
239
240void ide_set_reset(int idereset)
241{
242 debug("ide_reset(%d)\n", idereset);
243
244 if (idereset) {
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100245 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200246 /* Make a delay. MPC5200 spec says 25 usec min */
247 udelay(500000);
248 } else
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100249 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200250}
Jon Loeligerd39b5742007-07-10 10:48:22 -0500251#endif
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200252
253
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100254#ifdef CONFIG_HW_WATCHDOG
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200255void hw_watchdog_reset(void)
256{
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100257 /*
258 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
259 * we need a positive or negative transition on WDI i.e., our PSC3_9.
260 */
261 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200262}
Bartlomiej Sieka25721b52006-11-01 02:04:38 +0100263#endif /* CONFIG_HW_WATCHDOG */