| Rajeshwari Shinde | 998e5d3 | 2012-07-03 20:02:55 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Clock initialization routines |
| 3 | * |
| 4 | * Copyright (c) 2011 The Chromium OS Authors. |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __EXYNOS_CLOCK_INIT_H |
| 26 | #define __EXYNOS_CLOCK_INIT_H |
| 27 | |
| 28 | enum { |
| 29 | MEM_TIMINGS_MSR_COUNT = 4, |
| 30 | }; |
| 31 | |
| 32 | /* These are the ratio's for configuring ARM clock */ |
| 33 | struct arm_clk_ratios { |
| 34 | unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ |
| 35 | |
| 36 | unsigned apll_mdiv; |
| 37 | unsigned apll_pdiv; |
| 38 | unsigned apll_sdiv; |
| 39 | |
| 40 | unsigned arm2_ratio; |
| 41 | unsigned apll_ratio; |
| 42 | unsigned pclk_dbg_ratio; |
| 43 | unsigned atb_ratio; |
| 44 | unsigned periph_ratio; |
| 45 | unsigned acp_ratio; |
| 46 | unsigned cpud_ratio; |
| 47 | unsigned arm_ratio; |
| 48 | }; |
| 49 | |
| 50 | /* These are the memory timings for a particular memory type and speed */ |
| 51 | struct mem_timings { |
| 52 | enum mem_manuf mem_manuf; /* Memory manufacturer */ |
| 53 | enum ddr_mode mem_type; /* Memory type */ |
| 54 | unsigned frequency_mhz; /* Frequency of memory in MHz */ |
| 55 | |
| 56 | /* Here follow the timing parameters for the selected memory */ |
| 57 | unsigned apll_mdiv; |
| 58 | unsigned apll_pdiv; |
| 59 | unsigned apll_sdiv; |
| 60 | unsigned mpll_mdiv; |
| 61 | unsigned mpll_pdiv; |
| 62 | unsigned mpll_sdiv; |
| 63 | unsigned cpll_mdiv; |
| 64 | unsigned cpll_pdiv; |
| 65 | unsigned cpll_sdiv; |
| 66 | unsigned gpll_mdiv; |
| 67 | unsigned gpll_pdiv; |
| 68 | unsigned gpll_sdiv; |
| 69 | unsigned epll_mdiv; |
| 70 | unsigned epll_pdiv; |
| 71 | unsigned epll_sdiv; |
| 72 | unsigned vpll_mdiv; |
| 73 | unsigned vpll_pdiv; |
| 74 | unsigned vpll_sdiv; |
| 75 | unsigned bpll_mdiv; |
| 76 | unsigned bpll_pdiv; |
| 77 | unsigned bpll_sdiv; |
| 78 | unsigned pclk_cdrex_ratio; |
| 79 | unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; |
| 80 | |
| 81 | unsigned timing_ref; |
| 82 | unsigned timing_row; |
| 83 | unsigned timing_data; |
| 84 | unsigned timing_power; |
| 85 | |
| 86 | /* DQS, DQ, DEBUG offsets */ |
| 87 | unsigned phy0_dqs; |
| 88 | unsigned phy1_dqs; |
| 89 | unsigned phy0_dq; |
| 90 | unsigned phy1_dq; |
| 91 | unsigned phy0_tFS; |
| 92 | unsigned phy1_tFS; |
| 93 | unsigned phy0_pulld_dqs; |
| 94 | unsigned phy1_pulld_dqs; |
| 95 | |
| 96 | unsigned lpddr3_ctrl_phy_reset; |
| 97 | unsigned ctrl_start_point; |
| 98 | unsigned ctrl_inc; |
| 99 | unsigned ctrl_start; |
| 100 | unsigned ctrl_dll_on; |
| 101 | unsigned ctrl_ref; |
| 102 | |
| 103 | unsigned ctrl_force; |
| 104 | unsigned ctrl_rdlat; |
| 105 | unsigned ctrl_bstlen; |
| 106 | |
| 107 | unsigned fp_resync; |
| 108 | unsigned iv_size; |
| 109 | unsigned dfi_init_start; |
| 110 | unsigned aref_en; |
| 111 | |
| 112 | unsigned rd_fetch; |
| 113 | |
| 114 | unsigned zq_mode_dds; |
| 115 | unsigned zq_mode_term; |
| 116 | unsigned zq_mode_noterm; /* 1 to allow termination disable */ |
| 117 | |
| 118 | unsigned memcontrol; |
| 119 | unsigned memconfig; |
| 120 | |
| 121 | unsigned membaseconfig0; |
| 122 | unsigned membaseconfig1; |
| 123 | unsigned prechconfig_tp_cnt; |
| 124 | unsigned dpwrdn_cyc; |
| 125 | unsigned dsref_cyc; |
| 126 | unsigned concontrol; |
| 127 | /* Channel and Chip Selection */ |
| 128 | uint8_t dmc_channels; /* number of memory channels */ |
| 129 | uint8_t chips_per_channel; /* number of chips per channel */ |
| 130 | uint8_t chips_to_configure; /* number of chips to configure */ |
| 131 | uint8_t send_zq_init; /* 1 to send this command */ |
| 132 | unsigned impedance; /* drive strength impedeance */ |
| 133 | uint8_t gate_leveling_enable; /* check gate leveling is enabled */ |
| 134 | }; |
| 135 | |
| 136 | /** |
| 137 | * Get the correct memory timings for our selected memory type and speed. |
| 138 | * |
| 139 | * This function can be called from SPL or the main U-Boot. |
| 140 | * |
| 141 | * @return pointer to the memory timings that we should use |
| 142 | */ |
| 143 | struct mem_timings *clock_get_mem_timings(void); |
| 144 | |
| 145 | /* |
| 146 | * Initialize clock for the device |
| 147 | */ |
| 148 | void system_clock_init(void); |
| 149 | #endif |