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wdenkc7de8292002-11-19 11:04:11 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the AmigaOneG3SE board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_AMIGAONEG3SE 1
45
wdenkc837dcb2004-01-20 23:12:12 +000046#define CONFIG_BOARD_EARLY_INIT_F 1
wdenkc7de8292002-11-19 11:04:11 +000047#define CONFIG_MISC_INIT_R 1
48
49#define CONFIG_VERY_BIG_RAM 1
50
51#define CONFIG_CONS_INDEX 1
52#define CONFIG_BAUDRATE 9600
53#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
54
55#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */
56
57#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
58
59#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
60 CONFIG_BOOTP_BOOTFILESIZE)
61
62#define CONFIG_MAC_PARTITION
63#define CONFIG_DOS_PARTITION
64#define CONFIG_AMIGA_PARTITION
65
66#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
67 CFG_CMD_ASKENV | \
68 CFG_CMD_BSP | \
69 CFG_CMD_DATE | \
70 CFG_CMD_DHCP | \
71 CFG_CMD_ELF | \
72 CFG_CMD_NET | \
73 CFG_CMD_IDE | \
74 CFG_CMD_FDC | \
75 CFG_CMD_CACHE | \
76 CFG_CMD_CONSOLE| \
77 CFG_CMD_USB | \
78 CFG_CMD_BSP | \
79 CFG_CMD_PCI )
80
81/* CFG_CMD_MII | \ */
82
83#define CONFIG_PCI 1
84/* #define CONFIG_PCI_SCAN_SHOW 1 */
85#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
86
87/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
88 */
89#include <cmd_confdefs.h>
90
91
92/*
93 * Miscellaneous configurable options
94 */
95#define CFG_LONGHELP /* undef to save memory */
wdenk7c7a23b2002-12-07 00:20:59 +000096#define CFG_PROMPT "] " /* Monitor Command Prompt */
wdenkc7de8292002-11-19 11:04:11 +000097
98#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
99/* #undef CFG_HUSH_PARSER */
100#ifdef CFG_HUSH_PARSER
101#define CFG_PROMPT_HUSH_PS2 "> "
102#endif
103#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
104
105/* Print Buffer Size
106 */
107#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
108
109#define CFG_MAXARGS 64 /* max number of command args */
110#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
111#define CFG_LOAD_ADDR 0x00500000 /* Default load address */
112
113/*-----------------------------------------------------------------------
114 * Start addresses for the final memory configuration
115 * (Set up by the startup code)
116 * Please note that CFG_SDRAM_BASE _must_ start at 0
117 */
118#define CFG_SDRAM_BASE 0x00000000
119#define CFG_FLASH_BASE 0xFFF00000
120#define CFG_FLASH_MAX_SIZE 0x00080000
121/* Maximum amount of RAM.
122 */
123#define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */
124
125#define CFG_RESET_ADDRESS 0xFFF00100
126
127#define CFG_MONITOR_BASE TEXT_BASE
128
129#define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */
130#define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */
131
132#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
133 CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
134#define CFG_RAMBOOT
135#else
136#undef CFG_RAMBOOT
137#endif
138
139#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
140#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
141
142/*-----------------------------------------------------------------------
143 * Definitions for initial stack pointer and data area
144 */
145
146/* Size in bytes reserved for initial data
147 */
wdenk7c7a23b2002-12-07 00:20:59 +0000148/* HJF: used to be 0x400000 */
wdenk8bde7f72003-06-27 21:31:46 +0000149#define CFG_INIT_RAM_ADDR 0x40000000
wdenkc7de8292002-11-19 11:04:11 +0000150#define CFG_INIT_RAM_END 0x8000
151#define CFG_GBL_DATA_SIZE 128
152#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
153#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
154
155#define CFG_INIT_RAM_LOCK
156
157/*
158 * Temporary buffer for serial data until the real serial driver
159 * is initialised (memtest will destroy this buffer)
160 */
161#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR
162#define CFG_SCONSOLE_SIZE 0x0002000
163
164/* SDRAM 0 - 256MB
165 */
166
wdenk7c7a23b2002-12-07 00:20:59 +0000167/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
wdenkc7de8292002-11-19 11:04:11 +0000168#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
169#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
wdenk7c7a23b2002-12-07 00:20:59 +0000170#define CFG_DBAT0U CFG_IBAT0U*/
wdenkc7de8292002-11-19 11:04:11 +0000171
wdenk7c7a23b2002-12-07 00:20:59 +0000172#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
173#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
174#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
175#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
176/* PCI Range
wdenkc7de8292002-11-19 11:04:11 +0000177 */
wdenk7c7a23b2002-12-07 00:20:59 +0000178#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
179#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
180#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
181#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
182/* HJF:
wdenk8bde7f72003-06-27 21:31:46 +0000183#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
wdenkc7de8292002-11-19 11:04:11 +0000184#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk8bde7f72003-06-27 21:31:46 +0000185#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
wdenkc7de8292002-11-19 11:04:11 +0000186#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk7c7a23b2002-12-07 00:20:59 +0000187*/
wdenkc7de8292002-11-19 11:04:11 +0000188
189/* Init RAM in the CPU DCache (no backing memory)
190 */
191#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
192#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk7c7a23b2002-12-07 00:20:59 +0000193/* This used to be commented out */
wdenk8bde7f72003-06-27 21:31:46 +0000194#define CFG_IBAT2L CFG_DBAT2L
wdenk7c7a23b2002-12-07 00:20:59 +0000195/* This here too */
wdenk8bde7f72003-06-27 21:31:46 +0000196#define CFG_IBAT2U CFG_DBAT2U
wdenk7c7a23b2002-12-07 00:20:59 +0000197
wdenkc7de8292002-11-19 11:04:11 +0000198
199/* I/O and PCI memory at 0xf0000000
200 */
201#define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
202#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
203
204#define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
205#define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
206
207/*
208 * Low Level Configuration Settings
209 * (address mappings, register initial values, etc.)
210 */
211#define CFG_HZ 1000
212#define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */
213#define CFG_CPU_CLK 133000000
214#define CFG_BUS_CLK 133000000
215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
220 */
221#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222
223/*-----------------------------------------------------------------------
224 * FLASH organization
225 */
226#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
227#define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */
228
229#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
230#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
231
232/*
233 * Environment is stored in NVRAM.
234 */
235#define CFG_ENV_IS_IN_NVRAM 1
236#define CFG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to
237 * protect softex's settings for now.
238 * Original 768 bytes where not enough.
239 */
240#define CFG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */
241
242#define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */
243#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
244#define CONFIG_ENV_OVERWRITE 1
245
246/*-----------------------------------------------------------------------
247 * Cache Configuration
248 */
249#define CFG_CACHELINE_SIZE 32
250#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
251# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
252#endif
253
254/*
255 * L2 cache
256 */
257#define CFG_L2
258#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
259 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
260#define L2_ENABLE (L2_INIT | L2CR_L2E)
261
262/*
263 * Internal Definitions
264 *
265 * Boot Flags
266 */
267#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
268#define BOOTFLAG_WARM 0x02 /* Software reboot */
269
270
271/*-----------------------------------------------------------------------
272 * IDE ATAPI Configuration
273 */
274
275#define CONFIG_ATAPI 1
276#define CFG_IDE_MAXBUS 2
277#define CFG_IDE_MAXDEVICE 4
278#define CONFIG_ISO_PARTITION 1
279
280#define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */
281#define CFG_ATA_IDE0_OFFSET 0x1F0
282#define CFG_ATA_IDE1_OFFSET 0x170
283
284#define CFG_ATA_REG_OFFSET 0
285#define CFG_ATA_DATA_OFFSET 0
286#define CFG_ATA_ALT_OFFSET 0x0200
287
288/*-----------------------------------------------------------------------
289 * Disk-On-Chip configuration
290 */
291
292#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
293
294#define CFG_DOC_SUPPORT_2000
295#undef CFG_DOC_SUPPORT_MILLENNIUM
296
297/*-----------------------------------------------------------------------
298 RTC
299*/
300#define CONFIG_RTC_MC146818
301
302/*-----------------------------------------------------------------------
303 * NS16550 Configuration
304 */
305
306#define CFG_NS16550
307
308#define CFG_NS16550_COM1 0xFE0003F8
309#define CFG_NS16550_COM2 0xFE0002F8
310
311#define CFG_NS16550_REG_SIZE 1
312
313/* base address for ISA I/O
314 */
315#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
316
317/* ISA Interrupt stuff (taken from JWL) */
318
319#define ISA_INT1_OCW1 0x21
320#define ISA_INT2_OCW1 0xA1
321#define ISA_INT1_OCW2 0x20
322#define ISA_INT2_OCW2 0xA0
323#define ISA_INT1_OCW3 0x20
324#define ISA_INT2_OCW3 0xA0
325
326#define ISA_INT1_ICW1 0x20
327#define ISA_INT2_ICW1 0xA0
328#define ISA_INT1_ICW2 0x21
329#define ISA_INT2_ICW2 0xA1
330#define ISA_INT1_ICW3 0x21
331#define ISA_INT2_ICW3 0xA1
332#define ISA_INT1_ICW4 0x21
333#define ISA_INT2_ICW4 0xA1
334
335
336/*
337 * misc
338 */
339
340#define CONFIG_NET_MULTI
341#define CFG_BOARD_ASM_INIT
342#define CONFIG_LAST_STAGE_INIT
343
344/* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */
345/* #define CONFIG_IPADDR 192.168.0.2 */
346/* #define CONFIG_NETMASK 255.255.255.240 */
347/* #define CONFIG_GATEWAYIP 192.168.0.3 */
348
349#define CONFIG_3COM
350/* #define CONFIG_BOOTP_RANDOM_DELAY */
351#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
352 CONFIG_BOOTP_BOOTFILESIZE)
353
354/*
355 * USB configuration
356 */
357#define CONFIG_USB_UHCI 1
358#define CONFIG_USB_STORAGE 1
359#define CONFIG_USB_KEYBOARD 1
360#define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
361
362/*
363 * Autoboot stuff
364 */
365#define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */
366#define CONFIG_PREBOOT ""
367#define CONFIG_BOOTCOMMAND "fdcboot; diskboot"
368#define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d "
369#define CONFIG_MENUKEY ' '
370#define CONFIG_MENUCOMMAND "menu"
371/* #define CONFIG_AUTOBOOT_KEYED */
372
373/*
374 * Extra ENV stuff
375 */
376#define CONFIG_EXTRA_ENV_SETTINGS \
377 "stdout=vga\0" \
378 "stdin=ps2kbd\0" \
379 "ide_doreset=on\0" \
380 "ide_maxbus=2\0" \
381 "ide_cd_timeout=30\0" \
382 "menucmd=menu\0" \
383 "pci_irqa=9\0" \
384 "pci_irqa_select=edge\0" \
385 "pci_irqb=10\0" \
386 "pci_irqb_select=edge\0" \
387 "pci_irqc=11\0" \
388 "pci_irqc_select=edge\0" \
wdenk7c7a23b2002-12-07 00:20:59 +0000389 "pci_irqd=7\0" \
wdenkc7de8292002-11-19 11:04:11 +0000390 "pci_irqd_select=edge\0"
391
392
393/* #define CONFIG_MII 1 */
394/* #define CONFIG_BITBANGMII 1 */
395
396
397#endif /* __CONFIG_H */