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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_BMW 1
47
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
49
50#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
wdenkc6097192002-11-03 00:24:07 +000051#define CONFIG_TIGON3 1
52
53#define CONFIG_CONS_INDEX 1
54#define CONFIG_BAUDRATE 9600
55#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
56
57#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
58
59#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
60#define CONFIG_BOOTDELAY 5
61
62#define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
63#define DOC_PASSIVE_PROBE 1
64#define CFG_DOC_SUPPORT_2000 1
65#define CFG_DOC_SUPPORT_MILLENNIUM 1
66#define CFG_DOC_SHORT_TIMEOUT 1
67#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
68 CFG_CMD_DATE | \
69 CFG_CMD_DOC | \
70 CFG_CMD_ELF | \
71 0 )
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010072
73/* CFG_CMD_DOC required legacy NAND support */
74#define CFG_NAND_LEGACY
75
wdenkc6097192002-11-03 00:24:07 +000076#if 0
77#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
78 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
79
80#define CONFIG_PCI 1
81#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
82#endif
83
84/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
85 */
86#include <cmd_confdefs.h>
87
88
89/*
90 * Miscellaneous configurable options
91 */
92#define CFG_LONGHELP /* undef to save memory */
93#define CFG_PROMPT "=>" /* Monitor Command Prompt */
94#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
95
96/* Print Buffer Size
97 */
98#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
99
100#define CFG_MAXARGS 8 /* Max number of command args */
101#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
102#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
103
104/*-----------------------------------------------------------------------
105 * Start addresses for the final memory configuration
106 * (Set up by the startup code)
107 * Please note that CFG_SDRAM_BASE _must_ start at 0
108 */
109#define CFG_SDRAM_BASE 0x00000000
110
111#define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
112#define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
113#define CFG_FLASH_BASE CFG_MONITOR_BASE
114#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
115
116/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
117 * reset vector is actually located at FFB00100, but the 8245
118 * takes care of us.
119 */
120#define CFG_RESET_ADDRESS 0xFFF00100
121
122#define CFG_EUMB_ADDR 0xFC000000
123
124#define CFG_MONITOR_BASE TEXT_BASE
125
126#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
127#define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
128
129#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
130#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
131
132 /* Maximum amount of RAM.
133 */
134#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
135
136
137#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
138#undef CFG_RAMBOOT
139#else
140#define CFG_RAMBOOT
141#endif
142
143
144/*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area
146 */
147#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
148#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
149#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
150#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
151#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
152
153/*
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
157 * For the detail description refer to the MPC8240 user's manual.
158 */
159
160#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
161#define CFG_HZ 1000
162
163#define CFG_ETH_DEV_FN 0x7800
164#define CFG_ETH_IOBASE 0x00104000
165
166 /* Bit-field values for MCCR1.
167 */
168#define CFG_ROMNAL 0xf
169#define CFG_ROMFAL 0x1f
170#define CFG_DBUS_SIZE 0x3
171
172 /* Bit-field values for MCCR2.
173 */
174#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
175#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
176
177 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
178 */
179#define CFG_BSTOPRE 0 /* FIXME: was 192 */
180
181 /* Bit-field values for MCCR3.
182 */
183#define CFG_REFREC 2 /* Refresh to activate interval */
184
185 /* Bit-field values for MCCR4.
186 */
187#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
188#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
189#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
190#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
191#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
192#define CFG_ACTORW 0xa /* FIXME was 2 */
193#define CFG_REGISTERD_TYPE_BUFFER 1
194
195#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
196
197#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
198
199/* Memory bank settings.
200 * Only bits 20-29 are actually used from these vales to set the
201 * start/end addresses. The upper two bits will always be 0, and the lower
202 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
203 * address. Refer to the MPC8240 book.
204 */
205
206#define CFG_BANK0_START 0x00000000
207#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
208#define CFG_BANK0_ENABLE 1
209#define CFG_BANK1_START 0x3ff00000
210#define CFG_BANK1_END 0x3fffffff
211#define CFG_BANK1_ENABLE 0
212#define CFG_BANK2_START 0x3ff00000
213#define CFG_BANK2_END 0x3fffffff
214#define CFG_BANK2_ENABLE 0
215#define CFG_BANK3_START 0x3ff00000
216#define CFG_BANK3_END 0x3fffffff
217#define CFG_BANK3_ENABLE 0
218#define CFG_BANK4_START 0x3ff00000
219#define CFG_BANK4_END 0x3fffffff
220#define CFG_BANK4_ENABLE 0
221#define CFG_BANK5_START 0x3ff00000
222#define CFG_BANK5_END 0x3fffffff
223#define CFG_BANK5_ENABLE 0
224#define CFG_BANK6_START 0x3ff00000
225#define CFG_BANK6_END 0x3fffffff
226#define CFG_BANK6_ENABLE 0
227#define CFG_BANK7_START 0x3ff00000
228#define CFG_BANK7_END 0x3fffffff
229#define CFG_BANK7_ENABLE 0
230
231#define CFG_ODCR 0xff
232
233#define CONFIG_PCI 1 /* Include PCI support */
234#undef CONFIG_PCI_PNP
235
236/* PCI Memory space(s) */
237#define PCI_MEM_SPACE1_START 0x80000000
238#define PCI_MEM_SPACE2_START 0xfd000000
239
240/* ROM Spaces */
241#include "../board/bmw/bmw.h"
242
243/* BAT configuration */
244#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
245#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
246
247#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
248#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
249
250#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
251#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
252
253#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
254#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
255
256#define CFG_DBAT0L CFG_IBAT0L
257#define CFG_DBAT0U CFG_IBAT0U
258#define CFG_DBAT1L CFG_IBAT1L
259#define CFG_DBAT1U CFG_IBAT1U
260#define CFG_DBAT2L CFG_IBAT2L
261#define CFG_DBAT2U CFG_IBAT2U
262#define CFG_DBAT3L CFG_IBAT3L
263#define CFG_DBAT3U CFG_IBAT3U
264
265/*
266 * For booting Linux, the board info and command line data
267 * have to be in the first 8 MB of memory, since this is
268 * the maximum mapped by the Linux kernel during initialization.
269 */
270#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
271
272/*
273 * FLASH organization
274 */
275#define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */
276#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
277
278#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
279#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
280
281/*
282 * Warining: environment is not EMBEDDED in the U-Boot code.
283 * It's stored in flash separately.
284 */
285#define CFG_ENV_IS_IN_NVRAM 1
286#define CONFIG_ENV_OVERWRITE 1
287#define CFG_NVRAM_ACCESS_ROUTINE 1
288#define CFG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
289#define CFG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
290#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
291
292/*
293 * Cache Configuration
294 */
295#define CFG_CACHELINE_SIZE 32
296#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
297# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
298#endif
299
300/*
301 * Internal Definitions
302 *
303 * Boot Flags
304 */
305#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
306#define BOOTFLAG_WARM 0x02 /* Software reboot */
307
308
309#endif /* __CONFIG_H */