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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_SANDPOINT 1
41
42#if 0
43#define USE_DINK32 1
44#else
45#undef USE_DINK32
46#endif
47
48#define CONFIG_CONS_INDEX 1
wdenk149dded2003-09-10 18:20:28 +000049#define CONFIG_BAUDRATE 9600
50
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52
53#define CONFIG_TIMESTAMP /* Print image info with timestamp */
54
55#define CONFIG_PREBOOT "echo;" \
56 "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
57 "echo"
58
59#undef CONFIG_BOOTARGS
60
61#define CONFIG_EXTRA_ENV_SETTINGS \
62 "netdev=eth0\0" \
63 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064 "nfsroot=${serverip}:${rootpath}\0" \
wdenk149dded2003-09-10 18:20:28 +000065 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "addip=setenv bootargs ${bootargs} " \
67 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
68 ":${hostname}:${netdev}:off panic=1\0" \
69 "net_self=tftp ${kernel_addr} ${bootfile};" \
70 "tftp ${ramdisk_addr} ${ramdisk};" \
wdenk149dded2003-09-10 18:20:28 +000071 "run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
73 "net_nfs=tftp ${kernel_addr} ${bootfile};" \
wdenk149dded2003-09-10 18:20:28 +000074 "run nfsargs addip;bootm\0" \
75 "rootpath=/opt/eldk/ppc_82xx\0" \
76 "bootfile=/tftpboot/SP8240/uImage\0" \
77 "ramdisk=/tftpboot/SP8240/uRamdisk\0" \
78 "kernel_addr=200000\0" \
79 "ramdisk_addr=400000\0" \
80 ""
81#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc6097192002-11-03 00:24:07 +000082
wdenk414eec32005-04-02 22:37:54 +000083#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
84 CFG_CMD_DHCP | \
85 CFG_CMD_ELF | \
86 CFG_CMD_I2C | \
87 CFG_CMD_SDRAM | \
88 CFG_CMD_EEPROM | \
89 CFG_CMD_NFS | \
90 CFG_CMD_PCI | \
91 CFG_CMD_SNTP )
wdenkc6097192002-11-03 00:24:07 +000092
93/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
94#include <cmd_confdefs.h>
95
wdenk149dded2003-09-10 18:20:28 +000096#define CONFIG_DRAM_SPEED 100 /* MHz */
wdenkc6097192002-11-03 00:24:07 +000097
98/*
99 * Miscellaneous configurable options
100 */
101#define CFG_LONGHELP 1 /* undef to save memory */
102#define CFG_PROMPT "=> " /* Monitor Command Prompt */
103#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105#define CFG_MAXARGS 16 /* max number of command args */
106#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107#define CFG_LOAD_ADDR 0x00100000 /* default load address */
108#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
109
110/*-----------------------------------------------------------------------
111 * PCI stuff
112 *-----------------------------------------------------------------------
113 */
114#define CONFIG_PCI /* include pci support */
115#undef CONFIG_PCI_PNP
116
117#define CONFIG_NET_MULTI /* Multi ethernet cards support */
118
119#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000120#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +0000121
122#define PCI_ENET0_IOADDR 0x80000000
123#define PCI_ENET0_MEMADDR 0x80000000
124#define PCI_ENET1_IOADDR 0x81000000
125#define PCI_ENET1_MEMADDR 0x81000000
126
127
128/*-----------------------------------------------------------------------
129 * Start addresses for the final memory configuration
130 * (Set up by the startup code)
131 * Please note that CFG_SDRAM_BASE _must_ start at 0
132 */
133#define CFG_SDRAM_BASE 0x00000000
134#define CFG_MAX_RAM_SIZE 0x10000000
135
136#define CFG_RESET_ADDRESS 0xFFF00100
137
138#if defined (USE_DINK32)
139#define CFG_MONITOR_LEN 0x00030000
140#define CFG_MONITOR_BASE 0x00090000
141#define CFG_RAMBOOT 1
142#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
143#define CFG_INIT_RAM_END 0x10000
144#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
145#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
146#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
147#else
148#undef CFG_RAMBOOT
149#define CFG_MONITOR_LEN 0x00030000
150#define CFG_MONITOR_BASE TEXT_BASE
151
152/*#define CFG_GBL_DATA_SIZE 256*/
153#define CFG_GBL_DATA_SIZE 128
154
155#define CFG_INIT_RAM_ADDR 0x40000000
156#define CFG_INIT_RAM_END 0x1000
157#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
158
159#endif
160
161#define CFG_FLASH_BASE 0xFFF00000
162#if 0
163#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
164#else
165#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
166#endif
167#define CFG_ENV_IS_IN_FLASH 1
168#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
169#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
170
171#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
172
173#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
174#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
175
176#define CFG_EUMB_ADDR 0xFC000000
177
178#define CFG_ISA_MEM 0xFD000000
179#define CFG_ISA_IO 0xFE000000
180
181#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
182#define CFG_FLASH_RANGE_SIZE 0x01000000
183#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
184#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
185
186/*
187 * select i2c support configuration
188 *
189 * Supported configurations are {none, software, hardware} drivers.
190 * If the software driver is chosen, there are some additional
191 * configuration items that the driver uses to drive the port pins.
192 */
193#define CONFIG_HARD_I2C 1 /* To enable I2C support */
194#undef CONFIG_SOFT_I2C /* I2C bit-banged */
195#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
196#define CFG_I2C_SLAVE 0x7F
197
198#ifdef CONFIG_SOFT_I2C
199#error "Soft I2C is not configured properly. Please review!"
200#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
201#define I2C_ACTIVE (iop->pdir |= 0x00010000)
202#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
203#define I2C_READ ((iop->pdat & 0x00010000) != 0)
204#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
205 else iop->pdat &= ~0x00010000
206#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
207 else iop->pdat &= ~0x00020000
208#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
209#endif /* CONFIG_SOFT_I2C */
210
211
212#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
213#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
214#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
215#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
216
217
218#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
219#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
220
221/*-----------------------------------------------------------------------
222 * Definitions for initial stack pointer and data area (in DPRAM)
223 */
224
225
226#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
227#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
228#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
229#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
230
231#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
232#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
233
234/*
235 * NS87308 Configuration
236 */
237#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
238
239#define CFG_NS87308_BADDR_10 1
240
241#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
242 CFG_NS87308_UART2 | \
243 CFG_NS87308_POWRMAN | \
244 CFG_NS87308_RTC_APC )
245
246#undef CFG_NS87308_PS2MOD
247
248#define CFG_NS87308_CS0_BASE 0x0076
249#define CFG_NS87308_CS0_CONF 0x30
250#define CFG_NS87308_CS1_BASE 0x0075
251#define CFG_NS87308_CS1_CONF 0x30
252#define CFG_NS87308_CS2_BASE 0x0074
253#define CFG_NS87308_CS2_CONF 0x30
254
255/*
256 * NS16550 Configuration
257 */
258#define CFG_NS16550
259#define CFG_NS16550_SERIAL
260
261#define CFG_NS16550_REG_SIZE 1
262
263#define CFG_NS16550_CLK 1843200
264
265#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
266#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
267
268/*
269 * Low Level Configuration Settings
270 * (address mappings, register initial values, etc.)
271 * You should know what you are doing if you make changes here.
272 */
273
274#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenk7cb22f92003-12-27 19:24:54 +0000275#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
wdenkc6097192002-11-03 00:24:07 +0000276
277#define CFG_ROMNAL 7 /*rom/flash next access time */
278#define CFG_ROMFAL 11 /*rom/flash access time */
279
280#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
281
282/* the following are for SDRAM only*/
283#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
284#define CFG_REFREC 8 /* Refresh to activate interval */
285#define CFG_RDLAT 4 /* data latency from read command */
286#define CFG_PRETOACT 3 /* Precharge to activate interval */
287#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
288#define CFG_ACTORW 3 /* Activate to R/W */
289#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
290#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
291#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
292
293#define CFG_REGISTERD_TYPE_BUFFER 1
294
295/* memory bank settings*/
296/*
297 * only bits 20-29 are actually used from these vales to set the
298 * start/end address the upper two bits will be 0, and the lower 20
299 * bits will be set to 0x00000 for a start address, or 0xfffff for an
300 * end address
301 */
302#define CFG_BANK0_START 0x00000000
303#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
304#define CFG_BANK0_ENABLE 1
305#define CFG_BANK1_START 0x3ff00000
306#define CFG_BANK1_END 0x3fffffff
307#define CFG_BANK1_ENABLE 0
308#define CFG_BANK2_START 0x3ff00000
309#define CFG_BANK2_END 0x3fffffff
310#define CFG_BANK2_ENABLE 0
311#define CFG_BANK3_START 0x3ff00000
312#define CFG_BANK3_END 0x3fffffff
313#define CFG_BANK3_ENABLE 0
314#define CFG_BANK4_START 0x00000000
315#define CFG_BANK4_END 0x00000000
316#define CFG_BANK4_ENABLE 0
317#define CFG_BANK5_START 0x00000000
318#define CFG_BANK5_END 0x00000000
319#define CFG_BANK5_ENABLE 0
320#define CFG_BANK6_START 0x00000000
321#define CFG_BANK6_END 0x00000000
322#define CFG_BANK6_ENABLE 0
323#define CFG_BANK7_START 0x00000000
324#define CFG_BANK7_END 0x00000000
325#define CFG_BANK7_ENABLE 0
326/*
327 * Memory bank enable bitmask, specifying which of the banks defined above
328 are actually present. MSB is for bank #7, LSB is for bank #0.
329 */
330#define CFG_BANK_ENABLE 0x01
331
332#define CFG_ODCR 0xff /* configures line driver impedances, */
333 /* see 8240 book for bit definitions */
334#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
335 /* currently accessed page in memory */
336 /* see 8240 book for details */
337
338/* SDRAM 0 - 256MB */
339#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
340#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
341
342/* stack in DCACHE @ 1GB (no backing mem) */
343#if defined(USE_DINK32)
344#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
345#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
346#else
347#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
348#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
349#endif
350
351/* PCI memory */
352#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
353#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
354
355/* Flash, config addrs, etc */
356#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
357#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
358
359#define CFG_DBAT0L CFG_IBAT0L
360#define CFG_DBAT0U CFG_IBAT0U
361#define CFG_DBAT1L CFG_IBAT1L
362#define CFG_DBAT1U CFG_IBAT1U
363#define CFG_DBAT2L CFG_IBAT2L
364#define CFG_DBAT2U CFG_IBAT2U
365#define CFG_DBAT3L CFG_IBAT3L
366#define CFG_DBAT3U CFG_IBAT3U
367
368/*
369 * For booting Linux, the board info and command line data
370 * have to be in the first 8 MB of memory, since this is
371 * the maximum mapped by the Linux kernel during initialization.
372 */
373#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
374/*-----------------------------------------------------------------------
375 * FLASH organization
376 */
377#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
378#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
379
380#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
381#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
382
383/*-----------------------------------------------------------------------
384 * Cache Configuration
385 */
386#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
387#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
388# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
389#endif
390
391
392/*
393 * Internal Definitions
394 *
395 * Boot Flags
396 */
397#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
398#define BOOTFLAG_WARM 0x02 /* Software reboot */
399
400
401/* values according to the manual */
402
403#define CONFIG_DRAM_50MHZ 1
404#define CONFIG_SDRAM_50MHZ
405
406#undef NR_8259_INTS
407#define NR_8259_INTS 1
408
409
410#define CONFIG_DISK_SPINUP_TIME 1000000
411
412
413#endif /* __CONFIG_H */