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wdenkfabd46a2004-07-10 23:11:10 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the CERF250 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkfabd46a2004-07-10 23:11:10 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_CERF250 1 /* on Cerf PXA Board */
39#define BOARD_LATE_INIT 1
40#define CONFIG_BAUDRATE 38400
41
42#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43
44/*
45 * Size of malloc() pool
46 */
47#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
48#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
49
50/*
51 * Hardware drivers
52 */
53#define CONFIG_DRIVER_SMC91111
54#define CONFIG_SMC91111_BASE 0x04000300
55#define CONFIG_SMC_USE_32_BIT
56
57/*
58 * select serial console configuration
59 */
60#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */
61
62/* allow to overwrite serial and ethaddr */
63#define CONFIG_ENV_OVERWRITE
64#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
65
66/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67#include <cmd_confdefs.h>
68
69#define CONFIG_BOOTDELAY 3
70#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
71#define CONFIG_NETMASK 255.255.255.0
72#define CONFIG_IPADDR 192.168.0.5
73#define CONFIG_SERVERIP 192.168.0.2
74#define CONFIG_BOOTCOMMAND "bootm 0xC0000"
75#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
76#define CONFIG_CMDLINE_TAG
77
78#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
79#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
80#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
81#endif
82
83/*
84 * Miscellaneous configurable options
85 */
86#define CFG_HUSH_PARSER 1
87#define CFG_PROMPT_HUSH_PS2 "> "
88
89#define CFG_LONGHELP /* undef to save memory */
90#ifdef CFG_HUSH_PARSER
91#define CFG_PROMPT "uboot$ " /* Monitor Command Prompt */
92#else
93#define CFG_PROMPT "=> " /* Monitor Command Prompt */
94#endif
95#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
96#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
97 /* Print Buffer Size */
98#define CFG_MAXARGS 16 /* max number of command args */
99#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
100#define CFG_DEVICE_NULLDEV 1
101
102#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
103#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
104
105#undef CFG_CLKS_IN_HZ
106
107#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
108
109#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
110#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
111
112#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
113
114
115/*
116 * Stack sizes
117 *
118 * The stack sizes are set up in start.S using the settings below
119 */
120#define CONFIG_STACKSIZE (128*1024) /* regular stack */
121#ifdef CONFIG_USE_IRQ
122#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
123#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
124#endif
125
126/*
127 * Physical Memory Map
128 */
129#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
130#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
131#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
132#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
133#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
134#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
135#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
136#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
137#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
138
139#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
140#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
141#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
142#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
143#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
144
145#define CFG_DRAM_BASE 0xa0000000
146#define CFG_DRAM_SIZE 0x04000000
147
148#define CFG_FLASH_BASE PHYS_FLASH_1
149
150/*
151 * GPIO settings
152 */
153
154
155#define CFG_GPSR0_VAL 0x00408030
156#define CFG_GPSR1_VAL 0x00BFA882
157#define CFG_GPSR2_VAL 0x0001C000
158#define CFG_GPCR0_VAL 0xC0031100
159#define CFG_GPCR1_VAL 0xFC400300
160#define CFG_GPCR2_VAL 0x00003FFF
161#define CFG_GPDR0_VAL 0xC0439330
162#define CFG_GPDR1_VAL 0xFCFFAB82
163#define CFG_GPDR2_VAL 0x0001FFFF
164#define CFG_GAFR0_L_VAL 0x80000000
165#define CFG_GAFR0_U_VAL 0xA5000010
166#define CFG_GAFR1_L_VAL 0x60008018
167#define CFG_GAFR1_U_VAL 0xAAA5AAAA
168#define CFG_GAFR2_L_VAL 0xAAA0000A
169#define CFG_GAFR2_U_VAL 0x00000002
170
171#define CFG_PSSR_VAL 0x20
172
173/*
174 * Memory settings
175 */
176#define CFG_MSC0_VAL 0x12447FF0
177#define CFG_MSC1_VAL 0x12BC5554
178#define CFG_MSC2_VAL 0x7FF97FF1
179#define CFG_MDCNFG_VAL 0x00001AC9
180#define CFG_MDREFR_VAL 0x03CDC017
181#define CFG_MDMRS_VAL 0x00000000
182
183/*
184 * PCMCIA and CF Interfaces
185 */
186#define CFG_MECR_VAL 0x00000000
187#define CFG_MCMEM0_VAL 0x00010504
188#define CFG_MCMEM1_VAL 0x00010504
189#define CFG_MCATT0_VAL 0x00010504
190#define CFG_MCATT1_VAL 0x00010504
191#define CFG_MCIO0_VAL 0x00004715
192#define CFG_MCIO1_VAL 0x00004715
193
194#define _LED 0x08000010 /*check this */
195#define LED_BLANK 0x08000040
196#define LED_GPIO 0x10
197
198/*
199 * FLASH and environment organization
200 */
201#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
202#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
203
204/* timeout values are in ticks */
205#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
206#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
207
208#define CFG_MONITOR_LEN 0x40000 /* 256 KiB */
209#define CFG_ENV_IS_IN_FLASH 1
210#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
211#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
212
213
214#endif /* __CONFIG_H */