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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
Masahiro Yamadab6036bc2015-01-13 12:44:35 +09007config DM_I2C
8 bool "Enable Driver Model for I2C drivers"
9 depends on DM
10 help
Przemyslaw Marczak705fcf42015-03-31 18:57:17 +020011 Enable driver model for I2C. The I2C uclass interface: probe, read,
12 write and speed, is implemented with the bus drivers operations,
13 which provide methods for bus setting and data transfer. Each chip
14 device (bus child) info is kept as parent platdata. The interface
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
16 uclass, but the device drivers not, then DM_I2C_COMPAT config can
17 be used as compatibility layer.
Masahiro Yamada26f820f2015-01-13 12:44:36 +090018
Simon Glass4bba9d32015-02-13 12:20:48 -070019config DM_I2C_COMPAT
20 bool "Enable I2C compatibility layer"
21 depends on DM
22 help
23 Enable old-style I2C functions for compatibility with existing code.
24 This option can be enabled as a temporary measure to avoid needing
25 to convert all code for a board in a single commit. It should not
26 be enabled for any board in an official release.
27
Simon Glasscc456bd2015-08-03 08:19:23 -060028config I2C_CROS_EC_TUNNEL
29 tristate "Chrome OS EC tunnel I2C bus"
30 depends on CROS_EC
31 help
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
34 This will work whatever the interface used to talk to the EC (SPI,
35 I2C or LPC). Some Chromebooks use this when the hardware design
36 does not allow direct access to the main PMIC from the AP.
37
Simon Glassf48eaf02015-08-03 08:19:24 -060038config I2C_CROS_EC_LDO
39 bool "Provide access to LDOs on the Chrome OS EC"
40 depends on CROS_EC
41 ---help---
42 On many Chromebooks the main PMIC is inaccessible to the AP. This is
43 often dealt with by using an I2C pass-through interface provided by
44 the EC. On some unfortunate models (e.g. Spring) the pass-through
45 is not available, and an LDO message is available instead. This
46 option enables a driver which provides very basic access to those
47 regulators, via the EC. We implement this as an I2C bus which
48 emulates just the TPS65090 messages we know about. This is done to
49 avoid duplicating the logic in the TPS65090 regulator driver for
50 enabling/disabling an LDO.
Simon Glasscc456bd2015-08-03 08:19:23 -060051
Lukasz Majewskie46f8a32017-03-21 12:08:25 +010052config I2C_SET_DEFAULT_BUS_NUM
53 bool "Set default I2C bus number"
54 depends on DM_I2C
55 help
56 Set default number of I2C bus to be accessed. This option provides
57 behaviour similar to old (i.e. pre DM) I2C bus driver.
58
59config I2C_DEFAULT_BUS_NUMBER
60 hex "I2C default bus number"
61 depends on I2C_SET_DEFAULT_BUS_NUM
62 default 0x0
63 help
64 Number of default I2C bus to use
65
Przemyslaw Marczakc54473c2015-03-31 18:57:18 +020066config DM_I2C_GPIO
67 bool "Enable Driver Model for software emulated I2C bus driver"
68 depends on DM_I2C && DM_GPIO
69 help
70 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
71 configuration is given by the device tree. Kernel-style device tree
72 bindings are supported.
73 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
74
Songjun Wu8800e0f2016-06-20 13:22:38 +080075config SYS_I2C_AT91
76 bool "Atmel I2C driver"
77 depends on DM_I2C && ARCH_AT91
78 help
79 Add support for the Atmel I2C driver. A serious problem is that there
80 is no documented way to issue repeated START conditions for more than
81 two messages, as needed to support combined I2C messages. Use the
82 i2c-gpio driver unless your system can cope with this limitation.
83 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
84
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +020085config SYS_I2C_FSL
86 bool "Freescale I2C bus driver"
87 depends on DM_I2C
88 help
89 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
90 MPC85xx processors.
91
Moritz Fischerfdec2d22015-12-28 09:47:11 -080092config SYS_I2C_CADENCE
93 tristate "Cadence I2C Controller"
94 depends on DM_I2C && (ARCH_ZYNQ || ARM64)
95 help
96 Say yes here to select Cadence I2C Host Controller. This controller is
97 e.g. used by Xilinx Zynq.
98
Stefan Roesee32d0db2016-04-28 09:47:17 +020099config SYS_I2C_DW
100 bool "Designware I2C Controller"
101 default n
102 help
103 Say yes here to select the Designware I2C Host Controller. This
104 controller is used in various SoCs, e.g. the ST SPEAr, Altera
105 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
106
Stefan Roese3a370522016-04-28 09:47:19 +0200107config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
108 bool "DW I2C Enable Status Register not supported"
109 depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
110 TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
111 default y
112 help
113 Some versions of the Designware I2C controller do not support the
114 enable status register. This config option can be enabled in such
115 cases.
116
maxims@google.com4dc038f2017-04-17 12:00:30 -0700117config SYS_I2C_ASPEED
118 bool "Aspeed I2C Controller"
119 depends on DM_I2C && ARCH_ASPEED
120 help
121 Say yes here to select Aspeed I2C Host Controller. The driver
122 supports AST2500 and AST2400 controllers, but is very limited.
123 Only single master mode is supported and only byte-by-byte
124 synchronous reads and writes are supported, no Pool Buffers or DMA.
125
Simon Glassabb0b012016-01-17 16:11:44 -0700126config SYS_I2C_INTEL
127 bool "Intel I2C/SMBUS driver"
128 depends on DM_I2C
129 help
130 Add support for the Intel SMBUS driver. So far this driver is just
131 a stub which perhaps some basic init. There is no implementation of
132 the I2C API meaning that any I2C operations will immediately fail
133 for now.
134
Peng Fan7ee3f142017-02-24 09:54:18 +0800135config SYS_I2C_IMX_LPI2C
136 bool "NXP i.MX LPI2C driver"
Peng Fan7ee3f142017-02-24 09:54:18 +0800137 help
138 Add support for the NXP i.MX LPI2C driver.
139
Jagan Teki72c8c102016-12-06 00:00:57 +0100140config SYS_I2C_MXC
141 bool "NXP i.MX I2C driver"
142 depends on MX6
143 help
144 Add support for the NXP i.MX I2C driver. This supports upto for bus
145 channels and operating on standard mode upto 100 kbits/s and fast
146 mode upto 400 kbits/s.
147
Adam Forddaa0f052017-08-07 13:11:34 -0500148config SYS_I2C_OMAP24XX
149 bool "TI OMAP2+ I2C driver"
150 depends on ARCH_OMAP2PLUS
151 help
152 Add support for the OMAP2+ I2C driver.
153
Simon Glass34374692015-08-30 16:55:39 -0600154config SYS_I2C_ROCKCHIP
155 bool "Rockchip I2C driver"
156 depends on DM_I2C
157 help
158 Add support for the Rockchip I2C driver. This is used with various
159 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
160 have several I2C ports and all are provided, controled by the
161 device tree.
162
Simon Glass1174aad2015-03-06 13:19:04 -0700163config SYS_I2C_SANDBOX
164 bool "Sandbox I2C driver"
165 depends on SANDBOX && DM_I2C
166 help
167 Enable I2C support for sandbox. This is an emulation of a real I2C
168 bus. Devices can be attached to the bus using the device tree
Masahiro Yamadac77c7db2017-02-11 12:39:55 +0900169 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass1174aad2015-03-06 13:19:04 -0700170
Jaehoon Chung1d61ad92017-01-09 14:47:52 +0900171config SYS_I2C_S3C24X0
172 bool "Samsung I2C driver"
173 depends on ARCH_EXYNOS4 && DM_I2C
174 help
175 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass1174aad2015-03-06 13:19:04 -0700176
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200177config SYS_I2C_STM32F7
178 bool "STMicroelectronics STM32F7 I2C support"
179 depends on (STM32F7 || STM32H7) && DM_I2C
180 help
181 Enable this option to add support for STM32 I2C controller
182 introduced with STM32F7/H7 SoCs. This I2C controller supports :
183 _ Slave and master modes
184 _ Multimaster capability
185 _ Standard-mode (up to 100 kHz)
186 _ Fast-mode (up to 400 kHz)
187 _ Fast-mode Plus (up to 1 MHz)
188 _ 7-bit and 10-bit addressing mode
189 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
190 _ All 7-bit addresses acknowledge mode
191 _ General call
192 _ Programmable setup and hold times
193 _ Easy to use event management
194 _ Optional clock stretching
195 _ Software reset
196
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900197config SYS_I2C_UNIPHIER
198 bool "UniPhier I2C driver"
199 depends on ARCH_UNIPHIER && DM_I2C
200 default y
201 help
Masahiro Yamadab6ef3a32015-05-29 17:30:01 +0900202 Support for UniPhier I2C controller driver. This I2C controller
203 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900204
205config SYS_I2C_UNIPHIER_F
206 bool "UniPhier FIFO-builtin I2C driver"
207 depends on ARCH_UNIPHIER && DM_I2C
208 default y
209 help
Masahiro Yamadab6ef3a32015-05-29 17:30:01 +0900210 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900211 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass3d1957f2015-08-03 08:19:21 -0600212
mario.six@gdsys.cc14a6ff22016-07-21 11:57:10 +0200213config SYS_I2C_MVTWSI
214 bool "Marvell I2C driver"
215 depends on DM_I2C
216 help
217 Support for Marvell I2C controllers as used on the orion5x and
218 kirkwood SoC families.
219
Stephen Warren34f1c9f2016-08-08 11:28:27 -0600220config TEGRA186_BPMP_I2C
221 bool "Enable Tegra186 BPMP-based I2C driver"
222 depends on TEGRA186_BPMP
223 help
224 Support for Tegra I2C controllers managed by the BPMP (Boot and
225 Power Management Processor). On Tegra186, some I2C controllers are
226 directly controlled by the main CPU, whereas others are controlled
227 by the BPMP, and can only be accessed by the main CPU via IPC
228 requests to the BPMP. This driver covers the latter case.
229
Adam Fordfc760cc2017-08-11 06:39:34 -0500230config SYS_I2C_BUS_MAX
231 int "Max I2C busses"
232 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
233 default 2 if TI816X
234 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
235 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
236 default 5 if OMAP54XX
237 help
238 Define the maximum number of available I2C buses.
239
Simon Glass3d1957f2015-08-03 08:19:21 -0600240source "drivers/i2c/muxes/Kconfig"
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900241
242endmenu