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rickb841b6e2017-05-18 14:37:53 +08001/*
2 * Andestech ATCPIT100 timer driver
3 *
4 * (C) Copyright 2016
5 * Rick Chen, NDS32 Software Engineering, rick@andestech.com
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <timer.h>
13#include <linux/io.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
18
19/*
20 * Definition of register offsets
21 */
22
23/* ID and Revision Register */
24#define ID_REV 0x0
25
26/* Configuration Register */
27#define CFG 0x10
28
29/* Interrupt Enable Register */
30#define INT_EN 0x14
31#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
32
33/* Interrupt Status Register */
34#define INT_STA 0x18
35#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
36
37/* Channel Enable Register */
38#define CH_EN 0x1C
39#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
40
41/* Ch n Control REgister */
42#define CH_CTL(n) (0x20+0x10*n)
43/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
44#define APB_CLK (1<<3)
45/* Channel mode , bit 0~2 */
46#define TMR_32 1
47#define TMR_16 2
48#define TMR_8 3
49#define PWM 4
50
51#define CH_REL(n) (0x24+0x10*n)
52#define CH_CNT(n) (0x28+0x10*n)
53
54struct atctmr_timer_regs {
55 u32 id_rev; /* 0x00 */
56 u32 reservd[3]; /* 0x04 ~ 0x0c */
57 u32 cfg; /* 0x10 */
58 u32 int_en; /* 0x14 */
59 u32 int_st; /* 0x18 */
60 u32 ch_en; /* 0x1c */
61 u32 ch0_ctrl; /* 0x20 */
62 u32 ch0_reload; /* 0x24 */
63 u32 ch0_cntr; /* 0x28 */
64 u32 reservd1; /* 0x2c */
65 u32 ch1_ctrl; /* 0x30 */
66 u32 ch1_reload; /* 0x34 */
67 u32 int_mask; /* 0x38 */
68};
69
70struct atftmr_timer_platdata {
71 unsigned long *regs;
72};
73
74static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
75{
76 struct atftmr_timer_platdata *plat = dev->platdata;
77 u32 val;
78 val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
79 *count = timer_conv_64(val);
80 return 0;
81}
82
83static int atctmr_timer_probe(struct udevice *dev)
84{
85 struct atftmr_timer_platdata *plat = dev->platdata;
86 REG32_TMR(CH_REL(1)) = 0xffffffff;
87 REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
88 REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
89 return 0;
90}
91
92static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
93{
94 struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
Simon Glassa821c4a2017-05-17 17:18:05 -060095 plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
rickb841b6e2017-05-18 14:37:53 +080096 return 0;
97}
98
99static const struct timer_ops ag101p_timer_ops = {
100 .get_count = atftmr_timer_get_count,
101};
102
103static const struct udevice_id ag101p_timer_ids[] = {
104 { .compatible = "andestech,atcpit100" },
105 {}
106};
107
108U_BOOT_DRIVER(altera_timer) = {
109 .name = "ae3xx_timer",
110 .id = UCLASS_TIMER,
111 .of_match = ag101p_timer_ids,
112 .ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
113 .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
114 .probe = atctmr_timer_probe,
115 .ops = &ag101p_timer_ops,
116 .flags = DM_FLAG_PRE_RELOC,
117};